]>
Commit | Line | Data |
---|---|---|
878ddf1f | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
f0ec738d | 14 | pcibus.h\r |
878ddf1f | 15 | \r |
16 | Abstract:\r | |
17 | \r | |
18 | PCI Bus Driver\r | |
19 | \r | |
20 | Revision History\r | |
21 | \r | |
22 | --*/\r | |
23 | \r | |
24 | #ifndef _EFI_PCI_BUS_H\r | |
25 | #define _EFI_PCI_BUS_H\r | |
26 | \r | |
27 | \r | |
f0ec738d | 28 | #include <IndustryStandard/pci22.h>\r |
878ddf1f | 29 | #include <IndustryStandard/Acpi.h>\r |
30 | #include "ComponentName.h"\r | |
31 | \r | |
32 | //\r | |
33 | // Driver Produced Protocol Prototypes\r | |
34 | //\r | |
35 | \r | |
36 | #define VGABASE1 0x3B0\r | |
37 | #define VGALIMIT1 0x3BB\r | |
38 | \r | |
39 | #define VGABASE2 0x3C0\r | |
40 | #define VGALIMIT2 0x3DF\r | |
41 | \r | |
42 | #define ISABASE 0x100\r | |
43 | #define ISALIMIT 0x3FF\r | |
44 | \r | |
45 | typedef enum {\r | |
46 | PciBarTypeUnknown = 0,\r | |
47 | PciBarTypeIo16,\r | |
48 | PciBarTypeIo32,\r | |
49 | PciBarTypeMem32,\r | |
50 | PciBarTypePMem32,\r | |
51 | PciBarTypeMem64,\r | |
52 | PciBarTypePMem64,\r | |
53 | PciBarTypeIo,\r | |
54 | PciBarTypeMem,\r | |
55 | PciBarTypeMaxType\r | |
56 | } PCI_BAR_TYPE;\r | |
57 | \r | |
58 | typedef struct {\r | |
59 | UINT64 BaseAddress;\r | |
60 | UINT64 Length;\r | |
61 | UINT64 Alignment;\r | |
62 | PCI_BAR_TYPE BarType;\r | |
63 | BOOLEAN Prefetchable;\r | |
64 | UINT8 MemType;\r | |
65 | UINT8 Offset;\r | |
66 | } PCI_BAR;\r | |
67 | \r | |
68 | #define PPB_BAR_0 0\r | |
69 | #define PPB_BAR_1 1\r | |
70 | #define PPB_IO_RANGE 2\r | |
71 | #define PPB_MEM32_RANGE 3\r | |
72 | #define PPB_PMEM32_RANGE 4\r | |
73 | #define PPB_PMEM64_RANGE 5\r | |
74 | #define PPB_MEM64_RANGE 0xFF\r | |
75 | \r | |
76 | #define P2C_BAR_0 0\r | |
77 | #define P2C_MEM_1 1\r | |
78 | #define P2C_MEM_2 2\r | |
79 | #define P2C_IO_1 3\r | |
80 | #define P2C_IO_2 4\r | |
81 | \r | |
82 | #define PCI_IO_DEVICE_SIGNATURE EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')\r | |
83 | \r | |
84 | #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r | |
85 | #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r | |
86 | #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r | |
87 | #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r | |
88 | #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r | |
89 | #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r | |
90 | #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r | |
91 | \r | |
92 | #define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r | |
93 | //\r | |
94 | // Define resource status constant\r | |
95 | //\r | |
96 | #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r | |
97 | #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r | |
98 | #define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r | |
99 | \r | |
100 | //\r | |
101 | // Define option for attribute\r | |
102 | //\r | |
103 | #define EFI_SET_SUPPORTS 0\r | |
104 | #define EFI_SET_ATTRIBUTES 1\r | |
105 | \r | |
106 | typedef struct _PCI_IO_DEVICE {\r | |
107 | UINT32 Signature;\r | |
108 | EFI_HANDLE Handle;\r | |
109 | EFI_PCI_IO_PROTOCOL PciIo;\r | |
110 | LIST_ENTRY Link;\r | |
111 | \r | |
112 | EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r | |
113 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r | |
114 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r | |
115 | \r | |
116 | //\r | |
117 | // PCI configuration space header type\r | |
118 | //\r | |
119 | PCI_TYPE00 Pci;\r | |
120 | \r | |
121 | //\r | |
122 | // Bus number, Device number, Function number\r | |
123 | //\r | |
124 | UINT8 BusNumber;\r | |
125 | UINT8 DeviceNumber;\r | |
126 | UINT8 FunctionNumber;\r | |
127 | \r | |
128 | //\r | |
129 | // BAR for this PCI Device\r | |
130 | //\r | |
131 | PCI_BAR PciBar[PCI_MAX_BAR];\r | |
132 | \r | |
133 | //\r | |
134 | // The bridge device this pci device is subject to\r | |
135 | //\r | |
136 | struct _PCI_IO_DEVICE *Parent;\r | |
137 | \r | |
138 | //\r | |
139 | // A linked list for children Pci Device if it is bridge device\r | |
140 | //\r | |
141 | LIST_ENTRY ChildList;\r | |
142 | \r | |
143 | //\r | |
144 | // TURE if the PCI bus driver creates the handle for this PCI device\r | |
145 | //\r | |
146 | BOOLEAN Registered;\r | |
147 | \r | |
148 | //\r | |
149 | // TRUE if the PCI bus driver successfully allocates the resource required by\r | |
150 | // this PCI device\r | |
151 | //\r | |
152 | BOOLEAN Allocated;\r | |
153 | \r | |
154 | //\r | |
155 | // The attribute this PCI device currently set\r | |
156 | //\r | |
157 | UINT64 Attributes;\r | |
158 | \r | |
159 | //\r | |
160 | // The attributes this PCI device actually supports\r | |
161 | //\r | |
162 | UINT64 Supports;\r | |
163 | \r | |
164 | //\r | |
165 | // The resource decode the bridge supports\r | |
166 | //\r | |
167 | UINT32 Decodes;\r | |
168 | \r | |
169 | //\r | |
170 | // The OptionRom Size\r | |
171 | //\r | |
172 | UINT64 RomSize;\r | |
173 | \r | |
174 | //\r | |
175 | // The OptionRom Size\r | |
176 | //\r | |
177 | UINT64 RomBase;\r | |
178 | \r | |
179 | //\r | |
180 | // TRUE if all OpROM (in device or in platform specific position) have been processed\r | |
181 | //\r | |
182 | BOOLEAN AllOpRomProcessed;\r | |
183 | \r | |
184 | //\r | |
185 | // TRUE if there is any EFI driver in the OptionRom\r | |
186 | //\r | |
187 | BOOLEAN BusOverride;\r | |
188 | \r | |
189 | //\r | |
190 | // A list tracking reserved resource on a bridge device\r | |
191 | //\r | |
192 | LIST_ENTRY ReservedResourceList;\r | |
193 | \r | |
194 | //\r | |
195 | // A list tracking image handle of platform specific overriding driver\r | |
196 | //\r | |
197 | LIST_ENTRY OptionRomDriverList;\r | |
198 | \r | |
199 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r | |
200 | EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r | |
201 | \r | |
202 | BOOLEAN IsPciExp;\r | |
203 | \r | |
204 | } PCI_IO_DEVICE;\r | |
205 | \r | |
206 | \r | |
207 | #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r | |
208 | CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r | |
209 | \r | |
210 | #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r | |
211 | CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r | |
212 | \r | |
213 | #define PCI_IO_DEVICE_FROM_LINK(a) \\r | |
214 | CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r | |
215 | \r | |
216 | //\r | |
217 | // Global Variables\r | |
218 | //\r | |
219 | extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r | |
220 | extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r | |
221 | extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r | |
222 | extern LIST_ENTRY gPciDevicePool;\r | |
223 | extern BOOLEAN gFullEnumeration;\r | |
224 | extern UINTN gPciHostBridgeNumber;\r | |
225 | extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r | |
226 | extern UINT64 gAllOne;\r | |
227 | extern UINT64 gAllZero;\r | |
228 | \r | |
229 | extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r | |
230 | \r | |
231 | #include "PciIo.h"\r | |
232 | #include "PciCommand.h"\r | |
233 | #include "PciDeviceSupport.h"\r | |
234 | #include "PciEnumerator.h"\r | |
235 | #include "PciEnumeratorSupport.h"\r | |
236 | #include "PciDriverOverride.h"\r | |
237 | #include "PciRomTable.h"\r | |
238 | #include "PciOptionRomSupport.h"\r | |
239 | #include "PciPowerManagement.h"\r | |
240 | #include "PciHotPlugSupport.h"\r | |
241 | #include "PciLib.h"\r | |
242 | \r | |
92dda53e | 243 | //\r |
244 | // PCI Bus Support Function Prototypes\r | |
245 | //\r | |
246 | EFI_STATUS\r | |
247 | EFIAPI\r | |
248 | PciBusDriverBindingSupported (\r | |
249 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
250 | IN EFI_HANDLE Controller,\r | |
251 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
252 | );\r | |
253 | \r | |
254 | EFI_STATUS\r | |
255 | EFIAPI\r | |
256 | PciBusDriverBindingStart (\r | |
257 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
258 | IN EFI_HANDLE Controller,\r | |
259 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
260 | );\r | |
261 | \r | |
262 | EFI_STATUS\r | |
263 | EFIAPI\r | |
264 | PciBusDriverBindingStop (\r | |
265 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
266 | IN EFI_HANDLE Controller,\r | |
267 | IN UINTN NumberOfChildren,\r | |
268 | IN EFI_HANDLE *ChildHandleBuffer\r | |
269 | );\r | |
270 | \r | |
878ddf1f | 271 | #endif\r |