[mirror_edk2.git] / EdkModulePkg / Core / DxeIplPeim / x64 / VirtualMemory.h

/*++ \r
\r
Copyright (c) 2006, Intel Corporation                                                         \r
All rights reserved. This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
  VirtualMemory.h\r
  \r
Abstract:\r
\r
  x64 Long Mode Virtual Memory Management Definitions  \r
\r
  References:\r
    1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
    4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
--*/  \r
#ifndef _VIRTUAL_MEMORY_H_\r
#define _VIRTUAL_MEMORY_H_\r
\r
\r
#pragma pack(1)\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
\r
//\r
// Page-Directory Offset 4K\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:1;             // Must Be Zero\r
    UINT64  Reserved2:1;              // Reserved\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} x64_PAGE_DIRECTORY_ENTRY_4K;\r
\r
//\r
// Page Table Entry 4K\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  PAT:1;                    // 0 = Ignore Page Attribute Table \r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} x64_PAGE_TABLE_ENTRY_4K;\r
\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1 \r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} x64_PAGE_TABLE_ENTRY_2M;\r
\r
typedef union {\r
  UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
  UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
  UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
  UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
  UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
  UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
  UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
  UINT64  Reserved:57;\r
} x64_PAGE_TABLE_ENTRY_COMMON;\r
\r
typedef union {\r
  x64_PAGE_TABLE_ENTRY_4K     Page4k;\r
  x64_PAGE_TABLE_ENTRY_2M     Page2Mb;\r
  x64_PAGE_TABLE_ENTRY_COMMON Common;\r
} x64_PAGE_TABLE_ENTRY;\r
\r
//\r
// MTRR Definitions\r
//\r
typedef enum {\r
  Uncached       = 0,\r
  WriteCombining = 1,\r
  WriteThrough   = 4,\r
  WriteProtected = 5,\r
  WriteBack      = 6\r
} x64_MTRR_MEMORY_TYPE;\r
\r
typedef union {\r
  struct {\r
    UINT32  VCNT:8;         // The number of Variable Range MTRRs\r
    UINT32  FIX:1;          // 1=Fixed Range MTRRs supported.  0=Fixed Range MTRRs not supported\r
    UINT32  Reserved_0;     // Reserved\r
    UINT32  WC:1;           // Write combining memory type supported\r
    UINT32  Reserved_1:21;  // Reserved\r
    UINT32  Reserved_2:32;  // Reserved\r
  } Bits;\r
  UINT64  Uint64;\r
} x64_MTRRCAP_MSR;\r
\r
typedef union {\r
  struct {\r
    UINT32  Type:8;         // Default Memory Type\r
    UINT32  Reserved_0:2;   // Reserved\r
    UINT32  FE:1;           // 1=Fixed Range MTRRs enabled.  0=Fixed Range MTRRs disabled\r
    UINT32  E:1;            // 1=MTRRs enabled, 0=MTRRs disabled\r
    UINT32  Reserved_1:20;  // Reserved\r
    UINT32  Reserved_2:32;  // Reserved\r
  } Bits;\r
  UINT64  Uint64;\r
} x64_MTRR_DEF_TYPE_MSR;\r
\r
typedef union {\r
  UINT8   Type[8];          // The 8 Memory Type values in the 64-bit MTRR\r
  UINT64  Uint64;           // The full 64-bit MSR\r
} x64_MTRR_FIXED_RANGE_MSR;\r
\r
typedef struct {\r
  x64_MTRRCAP_MSR           Capabilities;   // MTRR Capabilities MSR value\r
  x64_MTRR_DEF_TYPE_MSR     DefaultType;    // Default Memory Type MSR Value\r
  x64_MTRR_FIXED_RANGE_MSR  Fixed[11];      // The 11 Fixed MTRR MSR Values\r
} x64_MTRR_FIXED_RANGE;\r
\r
\r
typedef union {\r
  struct {\r
    UINT64  Type:8;         // Memory Type\r
    UINT64  Reserved0:4;    // Reserved\r
    UINT64  PhysBase:40;    // The physical base address(bits 35..12) of the MTRR\r
    UINT64  Reserved1:12 ;  // Reserved\r
  } Bits;\r
  UINT64  Uint64;\r
} x64_MTRR_PHYSBASE_MSR;\r
\r
typedef union {\r
  struct {\r
    UINT64  Reserved0:11;  // Reserved\r
    UINT64  Valid:1;        // 1=MTRR is valid, 0=MTRR is not valid\r
    UINT64  PhysMask:40;    // The physical address mask (bits 35..12) of the MTRR\r
    UINT64  Reserved1:12;  // Reserved\r
  } Bits;\r
  UINT64  Uint64;\r
} x64_MTRR_PHYSMASK_MSR;\r
\r
typedef struct {\r
  x64_MTRR_PHYSBASE_MSR  PhysBase;  // Variable MTRR Physical Base MSR\r
  x64_MTRR_PHYSMASK_MSR  PhysMask;  // Variable MTRR Physical Mask MSR\r
} x64_MTRR_VARIABLE_RANGE;\r
\r
#pragma pack()\r
\r
x64_MTRR_MEMORY_TYPE\r
EfiGetMTRRMemoryType (\r
  IN  EFI_PHYSICAL_ADDRESS      Address\r
  )\r
;\r
\r
BOOLEAN\r
CanNotUse2MBPage (\r
  IN  EFI_PHYSICAL_ADDRESS  BaseAddress\r
  )\r
;\r
\r
VOID\r
Convert2MBPageTo4KPages (  \r
  IN  x64_PAGE_TABLE_ENTRY_2M   *PageDirectoryEntry2MB, \r
  IN  EFI_PHYSICAL_ADDRESS        PageAddress\r
  )\r
;\r
\r
EFI_PHYSICAL_ADDRESS\r
CreateIdentityMappingPageTables (\r
  IN UINT32                NumberOfProcessorPhysicalAddressBits\r
  )\r
;\r
\r
#endif \r
Commit	Line	Data
878ddf1f	1	/*++ \r
	2	\r
	3	Copyright (c) 2006, Intel Corporation \r
	4	All rights reserved. This program and the accompanying materials \r
	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	VirtualMemory.h\r
	14	\r
	15	Abstract:\r
	16	\r
	17	x64 Long Mode Virtual Memory Management Definitions \r
	18	\r
	19	References:\r
	20	1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	21	2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	22	3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
	23	4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
	24	--*/ \r
	25	#ifndef _VIRTUAL_MEMORY_H_\r
	26	#define _VIRTUAL_MEMORY_H_\r
	27	\r
	28	\r
	29	#pragma pack(1)\r
	30	\r
	31	//\r
	32	// Page-Map Level-4 Offset (PML4) and\r
	33	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	34	//\r
	35	\r
	36	typedef union {\r
	37	struct {\r
	38	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	39	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	40	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	41	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	42	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	43	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	44	UINT64 Reserved:1; // Reserved\r
	45	UINT64 MustBeZero:2; // Must Be Zero\r
	46	UINT64 Available:3; // Available for use by system software\r
	47	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	48	UINT64 AvabilableHigh:11; // Available for use by system software\r
	49	UINT64 Nx:1; // No Execute bit\r
	50	} Bits;\r
	51	UINT64 Uint64;\r
	52	} x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
	53	\r
	54	//\r
	55	// Page-Directory Offset 4K\r
	56	//\r
	57	typedef union {\r
	58	struct {\r
	59	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	60	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	61	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	62	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	63	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	64	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
65	UINT64 Reserved:1; // Reserved\r
66	UINT64 MustBeZero:1; // Must Be Zero\r
67	UINT64 Reserved2:1; // Reserved\r
68	UINT64 Available:3; // Available for use by system software\r
69	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
70	UINT64 AvabilableHigh:11; // Available for use by system software\r
71	UINT64 Nx:1; // No Execute bit\r
72	} Bits;\r
73	UINT64 Uint64;\r
74	} x64_PAGE_DIRECTORY_ENTRY_4K;\r
75	\r
76	//\r
77	// Page Table Entry 4K\r
78	//\r
79	typedef union {\r
80	struct {\r
81	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
82	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
83	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
84	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
85	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
86	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
87	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
88	UINT64 PAT:1; // 0 = Ignore Page Attribute Table \r
89	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
90	UINT64 Available:3; // Available for use by system software\r
91	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
92	UINT64 AvabilableHigh:11; // Available for use by system software\r
93	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
94	} Bits;\r
95	UINT64 Uint64;\r
96	} x64_PAGE_TABLE_ENTRY_4K;\r
97	\r
98	\r
99	//\r
100	// Page Table Entry 2MB\r
101	//\r
102	typedef union {\r
103	struct {\r
104	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
105	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
106	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
107	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
108	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
109	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
110	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
111	UINT64 MustBe1:1; // Must be 1 \r
112	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
113	UINT64 Available:3; // Available for use by system software\r
114	UINT64 PAT:1; //\r
115	UINT64 MustBeZero:8; // Must be zero;\r
116	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
117	UINT64 AvabilableHigh:11; // Available for use by system software\r
118	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
119	} Bits;\r
120	UINT64 Uint64;\r
121	} x64_PAGE_TABLE_ENTRY_2M;\r
122	\r
123	typedef union {\r
124	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
125	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
126	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
127	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
128	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
129	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
130	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
131	UINT64 Reserved:57;\r
132	} x64_PAGE_TABLE_ENTRY_COMMON;\r
133	\r
134	typedef union {\r
135	x64_PAGE_TABLE_ENTRY_4K Page4k;\r
136	x64_PAGE_TABLE_ENTRY_2M Page2Mb;\r
137	x64_PAGE_TABLE_ENTRY_COMMON Common;\r
138	} x64_PAGE_TABLE_ENTRY;\r
139	\r
140	//\r
141	// MTRR Definitions\r
142	//\r
143	typedef enum {\r
144	Uncached = 0,\r
145	WriteCombining = 1,\r
146	WriteThrough = 4,\r
147	WriteProtected = 5,\r
148	WriteBack = 6\r
149	} x64_MTRR_MEMORY_TYPE;\r
150	\r
151	typedef union {\r
152	struct {\r
153	UINT32 VCNT:8; // The number of Variable Range MTRRs\r
154	UINT32 FIX:1; // 1=Fixed Range MTRRs supported. 0=Fixed Range MTRRs not supported\r
155	UINT32 Reserved_0; // Reserved\r
156	UINT32 WC:1; // Write combining memory type supported\r
157	UINT32 Reserved_1:21; // Reserved\r
158	UINT32 Reserved_2:32; // Reserved\r
159	} Bits;\r
160	UINT64 Uint64;\r
161	} x64_MTRRCAP_MSR;\r
162	\r
163	typedef union {\r
164	struct {\r
165	UINT32 Type:8; // Default Memory Type\r
166	UINT32 Reserved_0:2; // Reserved\r
167	UINT32 FE:1; // 1=Fixed Range MTRRs enabled. 0=Fixed Range MTRRs disabled\r
168	UINT32 E:1; // 1=MTRRs enabled, 0=MTRRs disabled\r
169	UINT32 Reserved_1:20; // Reserved\r
170	UINT32 Reserved_2:32; // Reserved\r
171	} Bits;\r
172	UINT64 Uint64;\r
173	} x64_MTRR_DEF_TYPE_MSR;\r
174	\r
175	typedef union {\r
176	UINT8 Type[8]; // The 8 Memory Type values in the 64-bit MTRR\r
177	UINT64 Uint64; // The full 64-bit MSR\r
178	} x64_MTRR_FIXED_RANGE_MSR;\r
179	\r
180	typedef struct {\r
181	x64_MTRRCAP_MSR Capabilities; // MTRR Capabilities MSR value\r
182	x64_MTRR_DEF_TYPE_MSR DefaultType; // Default Memory Type MSR Value\r
183	x64_MTRR_FIXED_RANGE_MSR Fixed[11]; // The 11 Fixed MTRR MSR Values\r
184	} x64_MTRR_FIXED_RANGE;\r
185	\r
186	\r
187	typedef union {\r
188	struct {\r
189	UINT64 Type:8; // Memory Type\r
190	UINT64 Reserved0:4; // Reserved\r
191	UINT64 PhysBase:40; // The physical base address(bits 35..12) of the MTRR\r
192	UINT64 Reserved1:12 ; // Reserved\r
193	} Bits;\r
194	UINT64 Uint64;\r
195	} x64_MTRR_PHYSBASE_MSR;\r
196	\r
197	typedef union {\r
198	struct {\r
199	UINT64 Reserved0:11; // Reserved\r
200	UINT64 Valid:1; // 1=MTRR is valid, 0=MTRR is not valid\r
201	UINT64 PhysMask:40; // The physical address mask (bits 35..12) of the MTRR\r
202	UINT64 Reserved1:12; // Reserved\r
203	} Bits;\r
204	UINT64 Uint64;\r
205	} x64_MTRR_PHYSMASK_MSR;\r
206	\r
207	typedef struct {\r
208	x64_MTRR_PHYSBASE_MSR PhysBase; // Variable MTRR Physical Base MSR\r
209	x64_MTRR_PHYSMASK_MSR PhysMask; // Variable MTRR Physical Mask MSR\r
210	} x64_MTRR_VARIABLE_RANGE;\r
211	\r
212	#pragma pack()\r
213	\r
214	x64_MTRR_MEMORY_TYPE\r
215	EfiGetMTRRMemoryType (\r
216	IN EFI_PHYSICAL_ADDRESS Address\r
217	)\r
218	;\r
219	\r
220	BOOLEAN\r
221	CanNotUse2MBPage (\r
222	IN EFI_PHYSICAL_ADDRESS BaseAddress\r
223	)\r
224	;\r
225	\r
226	VOID\r
227	Convert2MBPageTo4KPages ( \r
228	IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB, \r
229	IN EFI_PHYSICAL_ADDRESS PageAddress\r
230	)\r
231	;\r
232	\r
233	EFI_PHYSICAL_ADDRESS\r
234	CreateIdentityMappingPageTables (\r
235	IN UINT32 NumberOfProcessorPhysicalAddressBits\r
236	)\r
237	;\r
238	\r
239	#endif \r