| 878ddf1f |
1 | /*++\r |
| 2 | \r |
| 3 | Copyright (c) 2006, Intel Corporation \r |
| 4 | All rights reserved. This program and the accompanying materials \r |
| 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r |
| 7 | http://opensource.org/licenses/bsd-license.php \r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | \r |
| 12 | Module Name:\r |
| 13 | \r |
| 14 | PeHotRelocateEx.h\r |
| 15 | \r |
| 16 | Abstract:\r |
| 17 | \r |
| 18 | Fixes Intel Itanium(TM) specific relocation types\r |
| 19 | \r |
| 20 | \r |
| 21 | Revision History\r |
| 22 | \r |
| 23 | --*/\r |
| 24 | \r |
| 25 | #ifndef _PEHOTRELOCATE_EX_H_\r |
| 26 | #define _PEHOTRELOCATE_EX_H_\r |
| 27 | \r |
| 28 | #define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \\r |
| 29 | Value |= (((UINT64) ((*(Address) >> InstPos) & (((UINT64) 1 << Size) - 1))) << ValPos)\r |
| 30 | \r |
| 31 | #define INS_IMM64(Value, Address, Size, InstPos, ValPos) \\r |
| 32 | * (UINT32 *) Address = \\r |
| 33 | (*(UINT32 *) Address &~(((1 << Size) - 1) << InstPos)) | \\r |
| 34 | ((UINT32) ((((UINT64) Value >> ValPos) & (((UINT64) 1 << Size) - 1))) << InstPos)\r |
| 35 | \r |
| 36 | #define IMM64_IMM7B_INST_WORD_X 3\r |
| 37 | #define IMM64_IMM7B_SIZE_X 7\r |
| 38 | #define IMM64_IMM7B_INST_WORD_POS_X 4\r |
| 39 | #define IMM64_IMM7B_VAL_POS_X 0\r |
| 40 | \r |
| 41 | #define IMM64_IMM9D_INST_WORD_X 3\r |
| 42 | #define IMM64_IMM9D_SIZE_X 9\r |
| 43 | #define IMM64_IMM9D_INST_WORD_POS_X 18\r |
| 44 | #define IMM64_IMM9D_VAL_POS_X 7\r |
| 45 | \r |
| 46 | #define IMM64_IMM5C_INST_WORD_X 3\r |
| 47 | #define IMM64_IMM5C_SIZE_X 5\r |
| 48 | #define IMM64_IMM5C_INST_WORD_POS_X 13\r |
| 49 | #define IMM64_IMM5C_VAL_POS_X 16\r |
| 50 | \r |
| 51 | #define IMM64_IC_INST_WORD_X 3\r |
| 52 | #define IMM64_IC_SIZE_X 1\r |
| 53 | #define IMM64_IC_INST_WORD_POS_X 12\r |
| 54 | #define IMM64_IC_VAL_POS_X 21\r |
| 55 | \r |
| 56 | #define IMM64_IMM41a_INST_WORD_X 1\r |
| 57 | #define IMM64_IMM41a_SIZE_X 10\r |
| 58 | #define IMM64_IMM41a_INST_WORD_POS_X 14\r |
| 59 | #define IMM64_IMM41a_VAL_POS_X 22\r |
| 60 | \r |
| 61 | #define IMM64_IMM41b_INST_WORD_X 1\r |
| 62 | #define IMM64_IMM41b_SIZE_X 8\r |
| 63 | #define IMM64_IMM41b_INST_WORD_POS_X 24\r |
| 64 | #define IMM64_IMM41b_VAL_POS_X 32\r |
| 65 | \r |
| 66 | #define IMM64_IMM41c_INST_WORD_X 2\r |
| 67 | #define IMM64_IMM41c_SIZE_X 23\r |
| 68 | #define IMM64_IMM41c_INST_WORD_POS_X 0\r |
| 69 | #define IMM64_IMM41c_VAL_POS_X 40\r |
| 70 | \r |
| 71 | #define IMM64_SIGN_INST_WORD_X 3\r |
| 72 | #define IMM64_SIGN_SIZE_X 1\r |
| 73 | #define IMM64_SIGN_INST_WORD_POS_X 27\r |
| 74 | #define IMM64_SIGN_VAL_POS_X 63\r |
| 75 | \r |
| 76 | #endif\r |
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