EmbeddedPkg/Lan9118Dxe: Remove link check in SNP initialization
[mirror_edk2.git] / EmbeddedPkg / Drivers / Lan9118Dxe / Lan9118DxeUtil.c
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1/** @file\r
2*\r
3* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
4*\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12*\r
13**/\r
14\r
15#include "Lan9118Dxe.h"\r
16\r
b0fdce95 17STATIC EFI_MAC_ADDRESS mZeroMac = { { 0 } };\r
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18\r
19/**\r
20 This internal function reverses bits for 32bit data.\r
21\r
22 @param Value The data to be reversed.\r
23\r
24 @return Data reversed.\r
25\r
26**/\r
27UINT32\r
28ReverseBits (\r
29 UINT32 Value\r
30 )\r
31{\r
32 UINTN Index;\r
33 UINT32 NewValue;\r
34\r
35 NewValue = 0;\r
36 for (Index = 0; Index < 32; Index++) {\r
37 if ((Value & (1 << Index)) != 0) {\r
38 NewValue = NewValue | (1 << (31 - Index));\r
39 }\r
40 }\r
41\r
42 return NewValue;\r
43}\r
44\r
45/*\r
46** Create Ethernet CRC\r
47**\r
48** INFO USED:\r
49** 1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check\r
50**\r
51** 2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html\r
52**\r
53** 3: http://en.wikipedia.org/wiki/Computation_of_CRC\r
54*/\r
55UINT32\r
56GenEtherCrc32 (\r
57 IN EFI_MAC_ADDRESS *Mac,\r
58 IN UINT32 AddrLen\r
59 )\r
60{\r
61 INT32 Iter;\r
62 UINT32 Remainder;\r
63 UINT8 *Ptr;\r
64\r
65 Iter = 0;\r
66 Remainder = 0xFFFFFFFF; // 0xFFFFFFFF is standard seed for Ethernet\r
67\r
68 // Convert Mac Address to array of bytes\r
69 Ptr = (UINT8*)Mac;\r
70\r
71 // Generate the Crc bit-by-bit (LSB first)\r
72 while (AddrLen--) {\r
73 Remainder ^= *Ptr++;\r
74 for (Iter = 0;Iter < 8;Iter++) {\r
75 // Check if exponent is set\r
76 if (Remainder & 1) {\r
77 Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;\r
78 } else {\r
79 Remainder = (Remainder >> 1) ^ 0;\r
80 }\r
81 }\r
82 }\r
83\r
84 // Reverse the bits before returning (to Big Endian)\r
85 //TODO: Need to be reviewed. Do we want to do a bit reverse or a byte reverse (in this case use SwapBytes32())\r
86 return ReverseBits (Remainder);\r
87}\r
88\r
89// Function to read from MAC indirect registers\r
90UINT32\r
91IndirectMACRead32 (\r
92 UINT32 Index\r
93 )\r
94{\r
95 UINT32 MacCSR;\r
96\r
97 // Check index is in the range\r
98 ASSERT(Index <= 12);\r
99\r
100 // Wait until CSR busy bit is cleared\r
101 while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
102\r
103 // Set CSR busy bit to ensure read will occur\r
104 // Set the R/W bit to indicate we are reading\r
105 // Set the index of CSR Address to access desired register\r
106 MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);\r
107\r
108 // Write to the register\r
109 MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
110\r
111 // Wait until CSR busy bit is cleared\r
112 while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
113\r
114 // Now read from data register to get read value\r
115 return MmioRead32 (LAN9118_MAC_CSR_DATA);\r
116}\r
117\r
118// Function to write to MAC indirect registers\r
119UINT32\r
120IndirectMACWrite32 (\r
121 UINT32 Index,\r
122 UINT32 Value\r
123 )\r
124{\r
125 UINT32 ValueWritten;\r
126 UINT32 MacCSR;\r
127\r
128 // Check index is in the range\r
129 ASSERT(Index <= 12);\r
130\r
131 // Wait until CSR busy bit is cleared\r
132 while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
133\r
134 // Set CSR busy bit to ensure read will occur\r
135 // Set the R/W bit to indicate we are writing\r
136 // Set the index of CSR Address to access desired register\r
137 MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);\r
138\r
139 // Now write the value to the register before issuing the write command\r
140 ValueWritten = MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r
141\r
142 // Write the config to the register\r
143 MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
144\r
145 // Wait until CSR busy bit is cleared\r
146 while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
147\r
148 return ValueWritten;\r
149}\r
150\r
151// Function to read from MII register (PHY Access)\r
152UINT32\r
153IndirectPHYRead32 (\r
154 UINT32 Index\r
155 )\r
156{\r
157 UINT32 ValueRead;\r
158 UINT32 MiiAcc;\r
159\r
160 // Check it is a valid index\r
161 ASSERT(Index < 31);\r
162\r
163 // Wait for busy bit to clear\r
164 while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
165\r
166 // Clear the R/W bit to indicate we are reading\r
167 // Set the index of the MII register\r
168 // Set the PHY Address\r
169 // Set the MII busy bit to allow read\r
170 MiiAcc = MII_ACC_MII_READ | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r
171\r
172 // Now write this config to register\r
173 IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r
174\r
175 // Wait for busy bit to clear\r
176 while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
177\r
178 // Now read the value of the register\r
179 ValueRead = (IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_DATA) & 0xFFFF); // only lower 16 bits are valid for any PHY register\r
180\r
181 return ValueRead;\r
182}\r
183\r
184\r
185// Function to write to the MII register (PHY Access)\r
186UINT32\r
187IndirectPHYWrite32 (\r
188 UINT32 Index,\r
189 UINT32 Value\r
190 )\r
191{\r
192 UINT32 MiiAcc;\r
193 UINT32 ValueWritten;\r
194\r
195 // Check it is a valid index\r
196 ASSERT(Index < 31);\r
197\r
198 // Wait for busy bit to clear\r
199 while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
200\r
201 // Clear the R/W bit to indicate we are reading\r
202 // Set the index of the MII register\r
203 // Set the PHY Address\r
204 // Set the MII busy bit to allow read\r
205 MiiAcc = MII_ACC_MII_WRITE | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r
206\r
207 // Write the desired value to the register first\r
208 ValueWritten = IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_DATA, (Value & 0xFFFF));\r
209\r
210 // Now write the config to register\r
211 IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r
212\r
213 // Wait for operation to terminate\r
214 while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r
215\r
216 return ValueWritten;\r
217}\r
218\r
219\r
220/* ---------------- EEPROM Operations ------------------ */\r
221\r
222\r
223// Function to read from EEPROM memory\r
224UINT32\r
225IndirectEEPROMRead32 (\r
226 UINT32 Index\r
227 )\r
228{\r
229 UINT32 EepromCmd;\r
230\r
231 // Set the busy bit to ensure read will occur\r
232 EepromCmd = E2P_EPC_BUSY | E2P_EPC_CMD_READ;\r
233\r
234 // Set the index to access desired EEPROM memory location\r
235 EepromCmd |= E2P_EPC_ADDRESS(Index);\r
236\r
237 // Write to Eeprom command register\r
238 MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
239 gBS->Stall (LAN9118_STALL);\r
240\r
241 // Wait until operation has completed\r
242 while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
243\r
244 // Check that operation didn't time out\r
245 if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
246 DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));\r
247 return 0;\r
248 }\r
249\r
250 // Wait until operation has completed\r
251 while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
252\r
253 // Finally read the value\r
254 return MmioRead32 (LAN9118_E2P_DATA);\r
255}\r
256\r
257// Function to write to EEPROM memory\r
258UINT32\r
259IndirectEEPROMWrite32 (\r
260 UINT32 Index,\r
261 UINT32 Value\r
262 )\r
263{\r
264 UINT32 ValueWritten;\r
265 UINT32 EepromCmd;\r
266\r
267 ValueWritten = 0;\r
268\r
269 // Read the EEPROM Command register\r
270 EepromCmd = MmioRead32 (LAN9118_E2P_CMD);\r
271\r
272 // Set the busy bit to ensure read will occur\r
273 EepromCmd |= ((UINT32)1 << 31);\r
274\r
275 // Set the EEPROM command to write(0b011)\r
276 EepromCmd &= ~(7 << 28); // Clear the command first\r
277 EepromCmd |= (3 << 28); // Write 011\r
278\r
279 // Set the index to access desired EEPROM memory location\r
280 EepromCmd |= (Index & 0xF);\r
281\r
282 // Write the value to the data register first\r
283 ValueWritten = MmioWrite32 (LAN9118_E2P_DATA, Value);\r
284\r
285 // Write to Eeprom command register\r
286 MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
287 gBS->Stall (LAN9118_STALL);\r
288\r
289 // Wait until operation has completed\r
290 while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
291\r
292 // Check that operation didn't time out\r
293 if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
294 DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));\r
295 return 0;\r
296 }\r
297\r
298 // Wait until operation has completed\r
299 while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
300\r
301 return ValueWritten;\r
302}\r
303\r
304/* ---------------- General Operations ----------------- */\r
305\r
306VOID\r
307Lan9118SetMacAddress (\r
308 EFI_MAC_ADDRESS *Mac,\r
309 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
310 )\r
311{\r
312 IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRL,\r
313 (Mac->Addr[0] & 0xFF) |\r
314 ((Mac->Addr[1] & 0xFF) << 8) |\r
315 ((Mac->Addr[2] & 0xFF) << 16) |\r
316 ((Mac->Addr[3] & 0xFF) << 24)\r
317 );\r
318\r
319 IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRH,\r
320 (UINT32)(Mac->Addr[4] & 0xFF) |\r
321 ((Mac->Addr[5] & 0xFF) << 8)\r
322 );\r
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323}\r
324\r
325VOID\r
326Lan9118ReadMacAddress (\r
327 OUT EFI_MAC_ADDRESS *MacAddress\r
328 )\r
329{\r
330 UINT32 MacAddrHighValue;\r
331 UINT32 MacAddrLowValue;\r
332\r
333 // Read the Mac Addr high register\r
334 MacAddrHighValue = (IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRH) & 0xFFFF);\r
335 // Read the Mac Addr low register\r
336 MacAddrLowValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRL);\r
337\r
338 SetMem (MacAddress, sizeof(*MacAddress), 0);\r
339 MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);\r
340 MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;\r
341 MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;\r
342 MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;\r
343 MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);\r
344 MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;\r
345}\r
346\r
347/*\r
348 * Power up the 9118 and find its MAC address.\r
349 *\r
350 * This operation can be carried out when the LAN9118 is in any power state\r
351 *\r
352 */\r
353EFI_STATUS\r
354Lan9118Initialize (\r
355 IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
356 )\r
357{\r
358 UINTN Timeout;\r
359 UINT64 DefaultMacAddress;\r
360\r
361 // Attempt to wake-up the device if it is in a lower power state\r
362 if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
363 DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));\r
364 MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
365 gBS->Stall (LAN9118_STALL);\r
366 }\r
367\r
368 // Check that device is active\r
369 Timeout = 20;\r
370 while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Timeout) {\r
371 gBS->Stall (LAN9118_STALL);\r
372 }\r
373 if (!Timeout) {\r
374 return EFI_TIMEOUT;\r
375 }\r
376\r
377 // Check that EEPROM isn't active\r
378 Timeout = 20;\r
379 while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Timeout){\r
380 gBS->Stall (LAN9118_STALL);\r
381 }\r
382 if (!Timeout) {\r
383 return EFI_TIMEOUT;\r
384 }\r
385\r
386 // Check if a MAC address was loaded from EEPROM, and if it was, set it as the\r
387 // current address.\r
388 if ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r
389 DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));\r
390\r
391 // If we had an address before (set by StationAddess), continue to use it\r
392 if (CompareMem (&Snp->Mode->CurrentAddress, &mZeroMac, NET_ETHER_ADDR_LEN)) {\r
393 Lan9118SetMacAddress (&Snp->Mode->CurrentAddress, Snp);\r
394 } else {\r
395 // If there are no cached addresses, then fall back to a default\r
396 DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));\r
397 DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);\r
398 Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);\r
11bbc257 399 CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);\r
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400 }\r
401 } else {\r
402 // Store the MAC address that was loaded from EEPROM\r
403 Lan9118ReadMacAddress (&Snp->Mode->CurrentAddress);\r
404 CopyMem (&Snp->Mode->PermanentAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);\r
405 }\r
406\r
407 // Clear and acknowledge interrupts\r
408 MmioWrite32 (LAN9118_INT_EN, 0);\r
409 MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
410 MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
411\r
412 // Do self tests here?\r
413\r
414 return EFI_SUCCESS;\r
415}\r
416\r
417\r
418// Perform software reset on the LAN9118\r
419// Return 0 on success, -1 on error\r
420EFI_STATUS\r
421SoftReset (\r
422 UINT32 Flags,\r
423 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
424 )\r
425{\r
426 UINT32 HwConf;\r
427 UINT32 ResetTime;\r
428\r
429 // Initialize variable\r
430 ResetTime = 0;\r
431\r
432 // Stop Rx and Tx\r
433 StopTx (STOP_TX_MAC | STOP_TX_CFG | STOP_TX_CLEAR, Snp);\r
434 StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO\r
435\r
436 // Issue the reset\r
437 HwConf = MmioRead32 (LAN9118_HW_CFG);\r
438 HwConf |= 1;\r
439\r
440 // Set the Must Be One (MBO) bit\r
441 if (((HwConf & HWCFG_MBO) >> 20) == 0) {\r
442 HwConf |= HWCFG_MBO;\r
443 }\r
444\r
445 // Check that EEPROM isn't active\r
446 while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
447\r
448 // Write the configuration\r
449 MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
450 gBS->Stall (LAN9118_STALL);\r
451\r
452 // Wait for reset to complete\r
453 while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
454\r
455 gBS->Stall (LAN9118_STALL);\r
456 ResetTime += 1;\r
457\r
458 // If time taken exceeds 100us, then there was an error condition\r
459 if (ResetTime > 1000) {\r
460 Snp->Mode->State = EfiSimpleNetworkStopped;\r
461 return EFI_TIMEOUT;\r
462 }\r
463 }\r
464\r
465 // Check that EEPROM isn't active\r
466 while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
467\r
468 // TODO we probably need to re-set the mac address here.\r
469\r
470 // Clear and acknowledge all interrupts\r
471 if (Flags & SOFT_RESET_CLEAR_INT) {\r
472 MmioWrite32 (LAN9118_INT_EN, 0);\r
473 MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
474 MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
475 }\r
476\r
477 // Do self tests here?\r
478 if (Flags & SOFT_RESET_SELF_TEST) {\r
479\r
480 }\r
481\r
482 return EFI_SUCCESS;\r
483}\r
484\r
485\r
486// Perform PHY software reset\r
42589b9a 487EFI_STATUS\r
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488PhySoftReset (\r
489 UINT32 Flags,\r
490 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
491 )\r
492{\r
493 UINT32 PmtCtrl = 0;\r
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494\r
495 // PMT PHY reset takes precedence over BCR\r
496 if (Flags & PHY_RESET_PMT) {\r
497 PmtCtrl = MmioRead32 (LAN9118_PMT_CTRL);\r
498 PmtCtrl |= MPTCTRL_PHY_RST;\r
499 MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r
500\r
501 // Wait for completion\r
502 while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
503 gBS->Stall (LAN9118_STALL);\r
504 }\r
505 // PHY Basic Control Register reset\r
fffa8522 506 } else if (Flags & PHY_RESET_BCR) {\r
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507 IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);\r
508\r
509 // Wait for completion\r
510 while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {\r
511 gBS->Stall (LAN9118_STALL);\r
512 }\r
513 }\r
514\r
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515 // Clear and acknowledge all interrupts\r
516 if (Flags & PHY_SOFT_RESET_CLEAR_INT) {\r
517 MmioWrite32 (LAN9118_INT_EN, 0);\r
518 MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
519 MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
520 }\r
521\r
42589b9a 522 return EFI_SUCCESS;\r
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523}\r
524\r
525\r
526// Configure hardware for LAN9118\r
527EFI_STATUS\r
528ConfigureHardware (\r
529 UINT32 Flags,\r
530 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
531 )\r
532{\r
533 UINT32 GpioConf;\r
534\r
535 // Check if we want to use LEDs on GPIO\r
536 if (Flags & HW_CONF_USE_LEDS) {\r
537 GpioConf = MmioRead32 (LAN9118_GPIO_CFG);\r
538\r
539 // Enable GPIO as LEDs and Config as Push-Pull driver\r
540 GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |\r
541 GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;\r
542\r
543 // Write the configuration\r
544 MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
545 gBS->Stall (LAN9118_STALL);\r
546 }\r
547\r
548 return EFI_SUCCESS;\r
549}\r
550\r
551// Configure flow control\r
552EFI_STATUS\r
553ConfigureFlow (\r
554 UINT32 Flags,\r
555 UINT32 HighTrig,\r
556 UINT32 LowTrig,\r
557 UINT32 BPDuration,\r
558 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
559 )\r
560{\r
561 return EFI_SUCCESS;\r
562}\r
563\r
564// Do auto-negotiation\r
565EFI_STATUS\r
566AutoNegotiate (\r
567 UINT32 Flags,\r
568 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
569 )\r
570{\r
571 UINT32 PhyControl;\r
572 UINT32 PhyStatus;\r
573 UINT32 Features;\r
574 UINT32 TimeOut;\r
575\r
576 // First check that auto-negotiation is supported\r
577 PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r
578 if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {\r
579 DEBUG ((EFI_D_ERROR, "Auto-negotiation not supported.\n"));\r
580 return EFI_DEVICE_ERROR;\r
581 }\r
582\r
583 // Check that link is up first\r
584 if ((PhyStatus & PHYSTS_LINK_STS) == 0) {\r
585 // Wait until it is up or until Time Out\r
586 TimeOut = 2000;\r
587 while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {\r
588 gBS->Stall (LAN9118_STALL);\r
589 TimeOut--;\r
590 if (!TimeOut) {\r
591 DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));\r
592 return EFI_TIMEOUT;\r
593 }\r
594 }\r
595 }\r
596\r
597 // Configure features to advertise\r
598 Features = IndirectPHYRead32 (PHY_INDEX_AUTO_NEG_ADVERT);\r
599\r
600 if ((Flags & AUTO_NEGOTIATE_ADVERTISE_ALL) > 0) {\r
601 // Link speed capabilities\r
602 Features |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD);\r
603\r
604 // Pause frame capabilities\r
605 Features &= ~(PHYANA_PAUSE_OP_MASK);\r
606 Features |= 3 << 10;\r
607 }\r
608\r
609 // Write the features\r
610 IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);\r
611\r
612 // Read control register\r
613 PhyControl = IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL);\r
614\r
615 // Enable Auto-Negotiation\r
616 if ((PhyControl & PHYCR_AUTO_EN) == 0) {\r
617 PhyControl |= PHYCR_AUTO_EN;\r
618 }\r
619\r
620 // Restart auto-negotiation\r
621 PhyControl |= PHYCR_RST_AUTO;\r
622\r
623 // Enable collision test if required to do so\r
624 if (Flags & AUTO_NEGOTIATE_COLLISION_TEST) {\r
625 PhyControl |= PHYCR_COLL_TEST;\r
626 } else {\r
627 PhyControl &= ~ PHYCR_COLL_TEST;\r
628 }\r
629\r
630 // Write this configuration\r
631 IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PhyControl);\r
632\r
633 // Wait until process has completed\r
634 while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0);\r
635\r
636 return EFI_SUCCESS;\r
637}\r
638\r
639// Check the Link Status and take appropriate action\r
640EFI_STATUS\r
641CheckLinkStatus (\r
642 UINT32 Flags,\r
643 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
644 )\r
645{\r
646 // Get the PHY Status\r
647 UINT32 PhyBStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r
648\r
649 if (PhyBStatus & PHYSTS_LINK_STS) {\r
650 return EFI_SUCCESS;\r
651 } else {\r
652 return EFI_DEVICE_ERROR;\r
653 }\r
654}\r
655\r
656// Stop the transmitter\r
657EFI_STATUS\r
658StopTx (\r
659 UINT32 Flags,\r
660 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
661 )\r
662{\r
663 UINT32 MacCsr;\r
664 UINT32 TxCfg;\r
665\r
666 MacCsr = 0;\r
667 TxCfg = 0;\r
668\r
669 // Check if we want to clear tx\r
670 if (Flags & STOP_TX_CLEAR) {\r
671 TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
672 TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
673 MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
674 gBS->Stall (LAN9118_STALL);\r
675 }\r
676\r
677 // Check if already stopped\r
678 if (Flags & STOP_TX_MAC) {\r
679 MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
680\r
681 if (MacCsr & MACCR_TX_EN) {\r
682 MacCsr &= ~MACCR_TX_EN;\r
683 IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
684 }\r
685 }\r
686\r
687 if (Flags & STOP_TX_CFG) {\r
688 TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
689\r
690 if (TxCfg & TXCFG_TX_ON) {\r
691 TxCfg |= TXCFG_STOP_TX;\r
692 MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
693 gBS->Stall (LAN9118_STALL);\r
694\r
695 // Wait for Tx to finish transmitting\r
696 while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
697 }\r
698 }\r
699\r
700 return EFI_SUCCESS;\r
701}\r
702\r
703// Stop the receiver\r
704EFI_STATUS\r
705StopRx (\r
706 UINT32 Flags,\r
707 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
708 )\r
709{\r
710 UINT32 MacCsr;\r
711 UINT32 RxCfg;\r
712\r
713 RxCfg = 0;\r
714\r
715 // Check if already stopped\r
716 MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
717\r
718 if (MacCsr & MACCR_RX_EN) {\r
719 MacCsr &= ~ MACCR_RX_EN;\r
720 IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
721 }\r
722\r
723 // Check if we want to clear receiver FIFOs\r
724 if (Flags & STOP_RX_CLEAR) {\r
725 RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
726 RxCfg |= RXCFG_RX_DUMP;\r
727 MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
728 gBS->Stall (LAN9118_STALL);\r
729\r
730 while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
731 }\r
732\r
733 return EFI_SUCCESS;\r
734}\r
735\r
736// Start the transmitter\r
737EFI_STATUS\r
738StartTx (\r
739 UINT32 Flags,\r
740 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
741 )\r
742{\r
743 UINT32 MacCsr;\r
744 UINT32 TxCfg;\r
745\r
746 MacCsr = 0;\r
747 TxCfg = 0;\r
748\r
749 // Check if we want to clear tx\r
750 if (Flags & START_TX_CLEAR) {\r
751 TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
752 TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
753 MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
754 gBS->Stall (LAN9118_STALL);\r
755 }\r
756\r
757 // Check if tx was started from MAC and enable if not\r
758 if (Flags & START_TX_MAC) {\r
759 MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
760 gBS->Stall (LAN9118_STALL);\r
761 if ((MacCsr & MACCR_TX_EN) == 0) {\r
762 MacCsr |= MACCR_TX_EN;\r
763 IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
764 gBS->Stall (LAN9118_STALL);\r
765 }\r
766 }\r
767\r
768 // Check if tx was started from TX_CFG and enable if not\r
769 if (Flags & START_TX_CFG) {\r
770 TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
771 gBS->Stall (LAN9118_STALL);\r
772 if ((TxCfg & TXCFG_TX_ON) == 0) {\r
773 TxCfg |= TXCFG_TX_ON;\r
774 MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
775 gBS->Stall (LAN9118_STALL);\r
776 }\r
777 }\r
778\r
779 // Set the tx data trigger level\r
780\r
781 return EFI_SUCCESS;\r
782}\r
783\r
784// Start the receiver\r
785EFI_STATUS\r
786StartRx (\r
787 UINT32 Flags,\r
788 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
789 )\r
790{\r
791 UINT32 MacCsr;\r
792 UINT32 RxCfg;\r
793\r
794 RxCfg = 0;\r
795\r
796 // Check if already started\r
797 MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
798\r
799 if ((MacCsr & MACCR_RX_EN) == 0) {\r
800 // Check if we want to clear receiver FIFOs before starting\r
801 if (Flags & START_RX_CLEAR) {\r
802 RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
803 RxCfg |= RXCFG_RX_DUMP;\r
804 MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
805 gBS->Stall (LAN9118_STALL);\r
806\r
807 while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
808 }\r
809\r
810 MacCsr |= MACCR_RX_EN;\r
811 IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
812 gBS->Stall (LAN9118_STALL);\r
813 }\r
814\r
815 return EFI_SUCCESS;\r
816}\r
817\r
818// Check Tx Data available space\r
819UINT32\r
820TxDataFreeSpace (\r
821 UINT32 Flags,\r
822 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
823 )\r
824{\r
825 UINT32 TxInf;\r
826 UINT32 FreeSpace;\r
827\r
828 // Get the amount of free space from information register\r
829 TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r
830 FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);\r
831\r
832 return FreeSpace; // Value in bytes\r
833}\r
834\r
835// Check Tx Status used space\r
836UINT32\r
837TxStatusUsedSpace (\r
838 UINT32 Flags,\r
839 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
840 )\r
841{\r
842 UINT32 TxInf;\r
843 UINT32 UsedSpace;\r
844\r
845 // Get the amount of used space from information register\r
846 TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r
847 UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;\r
848\r
849 return UsedSpace << 2; // Value in bytes\r
850}\r
851\r
852// Check Rx Data used space\r
853UINT32\r
854RxDataUsedSpace (\r
855 UINT32 Flags,\r
856 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
857 )\r
858{\r
859 UINT32 RxInf;\r
860 UINT32 UsedSpace;\r
861\r
862 // Get the amount of used space from information register\r
863 RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r
864 UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);\r
865\r
866 return UsedSpace; // Value in bytes (rounded up to nearest DWORD)\r
867}\r
868\r
869// Check Rx Status used space\r
870UINT32\r
871RxStatusUsedSpace (\r
872 UINT32 Flags,\r
873 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
874 )\r
875{\r
876 UINT32 RxInf;\r
877 UINT32 UsedSpace;\r
878\r
879 // Get the amount of used space from information register\r
880 RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r
881 UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;\r
882\r
883 return UsedSpace << 2; // Value in bytes\r
884}\r
885\r
886\r
887// Change the allocation of FIFOs\r
888EFI_STATUS\r
889ChangeFifoAllocation (\r
890 IN UINT32 Flags,\r
891 IN OUT UINTN *TxDataSize OPTIONAL,\r
892 IN OUT UINTN *RxDataSize OPTIONAL,\r
893 IN OUT UINT32 *TxStatusSize OPTIONAL,\r
894 IN OUT UINT32 *RxStatusSize OPTIONAL,\r
895 IN OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
896 )\r
897{\r
898 UINT32 HwConf;\r
899 UINT32 TxFifoOption;\r
900\r
901 // Check that desired sizes don't exceed limits\r
902 if (*TxDataSize > TX_FIFO_MAX_SIZE)\r
903 return EFI_INVALID_PARAMETER;\r
904\r
905#if defined(RX_FIFO_MIN_SIZE) && defined(RX_FIFO_MAX_SIZE)\r
906 if (*RxDataSize > RX_FIFO_MAX_SIZE) {\r
907 return EFI_INVALID_PARAMETER;\r
908 }\r
909#endif\r
910\r
911 if (Flags & ALLOC_USE_DEFAULT) {\r
912 return EFI_SUCCESS;\r
913 }\r
914\r
915 // If we use the FIFOs (always use this first)\r
916 if (Flags & ALLOC_USE_FIFOS) {\r
917 // Read the current value of allocation\r
918 HwConf = MmioRead32 (LAN9118_HW_CFG);\r
919 TxFifoOption = (HwConf >> 16) & 0xF;\r
920\r
921 // Choose the correct size (always use larger than requested if possible)\r
922 if (*TxDataSize < TX_FIFO_MIN_SIZE) {\r
923 *TxDataSize = TX_FIFO_MIN_SIZE;\r
924 *RxDataSize = 13440;\r
925 *RxStatusSize = 896;\r
926 TxFifoOption = 2;\r
927 } else if ((*TxDataSize > TX_FIFO_MIN_SIZE) && (*TxDataSize <= 2560)) {\r
928 *TxDataSize = 2560;\r
929 *RxDataSize = 12480;\r
930 *RxStatusSize = 832;\r
931 TxFifoOption = 3;\r
932 } else if ((*TxDataSize > 2560) && (*TxDataSize <= 3584)) {\r
933 *TxDataSize = 3584;\r
934 *RxDataSize = 11520;\r
935 *RxStatusSize = 768;\r
936 TxFifoOption = 4;\r
937 } else if ((*TxDataSize > 3584) && (*TxDataSize <= 4608)) { // default option\r
938 *TxDataSize = 4608;\r
939 *RxDataSize = 10560;\r
940 *RxStatusSize = 704;\r
941 TxFifoOption = 5;\r
942 } else if ((*TxDataSize > 4608) && (*TxDataSize <= 5632)) {\r
943 *TxDataSize = 5632;\r
944 *RxDataSize = 9600;\r
945 *RxStatusSize = 640;\r
946 TxFifoOption = 6;\r
947 } else if ((*TxDataSize > 5632) && (*TxDataSize <= 6656)) {\r
948 *TxDataSize = 6656;\r
949 *RxDataSize = 8640;\r
950 *RxStatusSize = 576;\r
951 TxFifoOption = 7;\r
952 } else if ((*TxDataSize > 6656) && (*TxDataSize <= 7680)) {\r
953 *TxDataSize = 7680;\r
954 *RxDataSize = 7680;\r
955 *RxStatusSize = 512;\r
956 TxFifoOption = 8;\r
957 } else if ((*TxDataSize > 7680) && (*TxDataSize <= 8704)) {\r
958 *TxDataSize = 8704;\r
959 *RxDataSize = 6720;\r
960 *RxStatusSize = 448;\r
961 TxFifoOption = 9;\r
962 } else if ((*TxDataSize > 8704) && (*TxDataSize <= 9728)) {\r
963 *TxDataSize = 9728;\r
964 *RxDataSize = 5760;\r
965 *RxStatusSize = 384;\r
966 TxFifoOption = 10;\r
967 } else if ((*TxDataSize > 9728) && (*TxDataSize <= 10752)) {\r
968 *TxDataSize = 10752;\r
969 *RxDataSize = 4800;\r
970 *RxStatusSize = 320;\r
971 TxFifoOption = 11;\r
972 } else if ((*TxDataSize > 10752) && (*TxDataSize <= 11776)) {\r
973 *TxDataSize = 11776;\r
974 *RxDataSize = 3840;\r
975 *RxStatusSize = 256;\r
976 TxFifoOption = 12;\r
977 } else if ((*TxDataSize > 11776) && (*TxDataSize <= 12800)) {\r
978 *TxDataSize = 12800;\r
979 *RxDataSize = 2880;\r
980 *RxStatusSize = 192;\r
981 TxFifoOption = 13;\r
982 } else if ((*TxDataSize > 12800) && (*TxDataSize <= 13824)) {\r
983 *TxDataSize = 13824;\r
984 *RxDataSize = 1920;\r
985 *RxStatusSize = 128;\r
986 TxFifoOption = 14;\r
987 }\r
988 } else {\r
989 ASSERT(0); // Untested code path\r
990 HwConf = 0;\r
991 TxFifoOption = 0;\r
992 }\r
993\r
994 // Do we need DMA?\r
995 if (Flags & ALLOC_USE_DMA) {\r
996 return EFI_UNSUPPORTED; // Unsupported as of now\r
997 }\r
998 // Clear and assign the new size option\r
999 HwConf &= ~(0xF0000);\r
1000 HwConf |= ((TxFifoOption & 0xF) << 16);\r
1001 MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
1002 gBS->Stall (LAN9118_STALL);\r
1003\r
1004 return EFI_SUCCESS;\r
1005}\r