]>
Commit | Line | Data |
---|---|---|
46f2c53b OM |
1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
878b807a | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
46f2c53b OM |
6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #ifndef __LAN9118_DXE_UTIL_H__\r | |
10 | #define __LAN9118_DXE_UTIL_H__\r | |
11 | \r | |
12 | // Most common CRC32 Polynomial for little endian machines\r | |
13 | #define CRC_POLYNOMIAL 0xEDB88320\r | |
14 | \r | |
15 | /**\r | |
16 | This internal function reverses bits for 32bit data.\r | |
17 | \r | |
18 | @param Value The data to be reversed.\r | |
19 | \r | |
20 | @return Data reversed.\r | |
21 | \r | |
22 | **/\r | |
23 | UINT32\r | |
24 | ReverseBits (\r | |
25 | UINT32 Value\r | |
26 | );\r | |
27 | \r | |
28 | // Create an Ethernet CRC\r | |
29 | UINT32\r | |
30 | GenEtherCrc32 (\r | |
31 | IN EFI_MAC_ADDRESS *Mac,\r | |
32 | IN UINT32 AddrLen\r | |
33 | );\r | |
34 | \r | |
73683a24 MR |
35 | UINT32\r |
36 | Lan9118RawMmioRead32(\r | |
37 | UINTN Address,\r | |
38 | UINTN Delay\r | |
39 | );\r | |
40 | #define Lan9118MmioRead32(a) \\r | |
41 | Lan9118RawMmioRead32(a, a ## _RD_DELAY)\r | |
42 | \r | |
43 | UINT32\r | |
44 | Lan9118RawMmioWrite32(\r | |
45 | UINTN Address,\r | |
46 | UINT32 Value,\r | |
47 | UINTN Delay\r | |
48 | );\r | |
49 | #define Lan9118MmioWrite32(a, v) \\r | |
50 | Lan9118RawMmioWrite32(a, v, a ## _WR_DELAY)\r | |
51 | \r | |
46f2c53b OM |
52 | /* ------------------ MAC CSR Access ------------------- */\r |
53 | \r | |
54 | // Read from MAC indirect registers\r | |
55 | UINT32\r | |
56 | IndirectMACRead32 (\r | |
57 | UINT32 Index\r | |
58 | );\r | |
59 | \r | |
60 | \r | |
61 | // Write to indirect registers\r | |
62 | UINT32\r | |
63 | IndirectMACWrite32 (\r | |
64 | UINT32 Index,\r | |
65 | UINT32 Value\r | |
66 | );\r | |
67 | \r | |
68 | \r | |
69 | /* --------------- PHY Registers Access ---------------- */\r | |
70 | \r | |
71 | // Read from MII register (PHY Access)\r | |
72 | UINT32\r | |
73 | IndirectPHYRead32(\r | |
74 | UINT32 Index\r | |
75 | );\r | |
76 | \r | |
77 | \r | |
78 | // Write to the MII register (PHY Access)\r | |
79 | UINT32\r | |
80 | IndirectPHYWrite32(\r | |
81 | UINT32 Index,\r | |
82 | UINT32 Value\r | |
83 | );\r | |
84 | \r | |
85 | /* ---------------- EEPROM Operations ------------------ */\r | |
86 | \r | |
87 | // Read from EEPROM memory\r | |
88 | UINT32\r | |
89 | IndirectEEPROMRead32 (\r | |
90 | UINT32 Index\r | |
91 | );\r | |
92 | \r | |
93 | // Write to EEPROM memory\r | |
94 | UINT32\r | |
95 | IndirectEEPROMWrite32 (\r | |
96 | UINT32 Index,\r | |
97 | UINT32 Value\r | |
98 | );\r | |
99 | \r | |
100 | /* ---------------- General Operations ----------------- */\r | |
101 | \r | |
102 | VOID\r | |
103 | Lan9118SetMacAddress (\r | |
104 | EFI_MAC_ADDRESS *Mac,\r | |
105 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
106 | );\r | |
107 | \r | |
108 | // Initialise the LAN9118\r | |
109 | EFI_STATUS\r | |
110 | Lan9118Initialize (\r | |
111 | IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
112 | );\r | |
113 | \r | |
114 | // Flags for software reset\r | |
115 | #define SOFT_RESET_CHECK_MAC_ADDR_LOAD BIT0\r | |
116 | #define SOFT_RESET_CLEAR_INT BIT1\r | |
117 | #define SOFT_RESET_SELF_TEST BIT2\r | |
118 | \r | |
119 | // Perform software reset on the LAN9118\r | |
120 | EFI_STATUS\r | |
121 | SoftReset (\r | |
122 | UINT32 Flags,\r | |
123 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
124 | );\r | |
125 | \r | |
126 | // Flags for PHY reset\r | |
127 | #define PHY_RESET_PMT BIT0\r | |
128 | #define PHY_RESET_BCR BIT1\r | |
6382e5df | 129 | #define PHY_SOFT_RESET_CLEAR_INT BIT2\r |
46f2c53b OM |
130 | \r |
131 | // Perform PHY software reset\r | |
42589b9a | 132 | EFI_STATUS\r |
46f2c53b OM |
133 | PhySoftReset (\r |
134 | UINT32 Flags,\r | |
135 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
136 | );\r | |
137 | \r | |
138 | // Flags for Hardware configuration\r | |
139 | #define HW_CONF_USE_LEDS BIT0\r | |
140 | \r | |
141 | // Configure hardware for LAN9118\r | |
142 | EFI_STATUS\r | |
143 | ConfigureHardware (\r | |
144 | UINT32 Flags,\r | |
145 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
146 | );\r | |
147 | \r | |
148 | // Configure flow control\r | |
149 | EFI_STATUS\r | |
150 | ConfigureFlow (\r | |
151 | UINT32 Flags,\r | |
152 | UINT32 HighTrig,\r | |
153 | UINT32 LowTrig,\r | |
154 | UINT32 BPDuration,\r | |
155 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
156 | );\r | |
157 | \r | |
158 | // Flags for auto negotiation\r | |
159 | #define AUTO_NEGOTIATE_COLLISION_TEST BIT0\r | |
160 | #define AUTO_NEGOTIATE_ADVERTISE_ALL BIT1\r | |
161 | \r | |
162 | // Do auto-negotiation\r | |
163 | EFI_STATUS\r | |
164 | AutoNegotiate (\r | |
165 | UINT32 Flags,\r | |
166 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
167 | );\r | |
168 | \r | |
169 | // Check the Link Status and take appropriate action\r | |
170 | EFI_STATUS\r | |
171 | CheckLinkStatus (\r | |
172 | UINT32 Flags,\r | |
173 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
174 | );\r | |
175 | \r | |
176 | // Stop transmitter flags\r | |
177 | #define STOP_TX_MAC BIT0\r | |
178 | #define STOP_TX_CFG BIT1\r | |
179 | #define STOP_TX_CLEAR BIT2\r | |
180 | \r | |
181 | // Stop the transmitter\r | |
182 | EFI_STATUS\r | |
183 | StopTx (\r | |
184 | UINT32 Flags,\r | |
185 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
186 | );\r | |
187 | \r | |
188 | // Stop receiver flags\r | |
189 | #define STOP_RX_CLEAR BIT0\r | |
190 | \r | |
191 | // Stop the receiver\r | |
192 | EFI_STATUS\r | |
193 | StopRx (\r | |
194 | UINT32 Flags,\r | |
195 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
196 | );\r | |
197 | \r | |
198 | // Start transmitter flags\r | |
199 | #define START_TX_MAC BIT0\r | |
200 | #define START_TX_CFG BIT1\r | |
201 | #define START_TX_CLEAR BIT2\r | |
202 | \r | |
203 | // Start the transmitter\r | |
204 | EFI_STATUS\r | |
205 | StartTx (\r | |
206 | UINT32 Flags,\r | |
207 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
208 | );\r | |
209 | \r | |
210 | // Stop receiver flags\r | |
211 | #define START_RX_CLEAR BIT0\r | |
212 | \r | |
213 | // Start the receiver\r | |
214 | EFI_STATUS\r | |
215 | StartRx (\r | |
216 | UINT32 Flags,\r | |
217 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
218 | );\r | |
219 | \r | |
220 | // Check Tx Data available space\r | |
221 | UINT32\r | |
222 | TxDataFreeSpace (\r | |
223 | UINT32 Flags,\r | |
224 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
225 | );\r | |
226 | \r | |
227 | // Check Tx Status used space\r | |
228 | UINT32\r | |
229 | TxStatusUsedSpace (\r | |
230 | UINT32 Flags,\r | |
231 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
232 | );\r | |
233 | \r | |
234 | // Check Rx Data used space\r | |
235 | UINT32\r | |
236 | RxDataUsedSpace (\r | |
237 | UINT32 Flags,\r | |
238 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
239 | );\r | |
240 | \r | |
241 | // Check Rx Status used space\r | |
242 | UINT32\r | |
243 | RxStatusUsedSpace (\r | |
244 | UINT32 Flags,\r | |
245 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
246 | );\r | |
247 | \r | |
248 | \r | |
249 | // Flags for FIFO allocation\r | |
250 | #define ALLOC_USE_DEFAULT BIT0\r | |
251 | #define ALLOC_USE_FIFOS BIT1\r | |
252 | #define ALLOC_USE_DMA BIT2\r | |
253 | \r | |
254 | // FIFO min and max sizes\r | |
255 | #define TX_FIFO_MIN_SIZE 0x00000600\r | |
256 | #define TX_FIFO_MAX_SIZE 0x00003600\r | |
257 | //#define RX_FIFO_MIN_SIZE\r | |
258 | //#define RX_FIFO_MAX_SIZE\r | |
259 | \r | |
260 | // Change the allocation of FIFOs\r | |
261 | EFI_STATUS\r | |
262 | ChangeFifoAllocation (\r | |
263 | IN UINT32 Flags,\r | |
264 | IN OUT UINTN *TxDataSize OPTIONAL,\r | |
265 | IN OUT UINTN *RxDataSize OPTIONAL,\r | |
266 | IN OUT UINT32 *TxStatusSize OPTIONAL,\r | |
267 | IN OUT UINT32 *RxStatusSize OPTIONAL,\r | |
268 | IN OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
269 | );\r | |
270 | \r | |
271 | VOID\r | |
272 | Lan9118ReadMacAddress (\r | |
273 | OUT EFI_MAC_ADDRESS *Mac\r | |
274 | );\r | |
275 | \r | |
276 | #endif // __LAN9118_DXE_UTIL_H__\r |