projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| f6342447 OM |
1 | /** @file\r |
| 2 | * Header containing the structure specific to the Silicon Image I3132 Sata PCI card\r | |
| 3 | *\r | |
| 4 | * Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r | |
| 5 | *\r | |
| 878b807a | 6 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| f6342447 OM |
7 | *\r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | #ifndef __SATASII3132_H\r | |
| 11 | #define __SATASII3132_H\r | |
| 12 | \r | |
| 13 | #include <PiDxe.h>\r | |
| 14 | \r | |
| 15 | #include <Protocol/AtaPassThru.h>\r | |
| 16 | #include <Protocol/PciIo.h>\r | |
| 17 | \r | |
| 18 | #include <Library/UefiLib.h>\r | |
| 19 | #include <Library/DebugLib.h>\r | |
| 20 | #include <Library/PcdLib.h>\r | |
| 21 | #include <Library/BaseMemoryLib.h>\r | |
| 22 | #include <Library/UefiBootServicesTableLib.h>\r | |
| 23 | \r | |
| 24 | #include <IndustryStandard/Pci.h>\r | |
| 25 | \r | |
| 26 | #define SATA_SII3132_DEVICE_ID 0x3132\r | |
| 27 | #define SATA_SII3132_VENDOR_ID 0x1095\r | |
| 28 | \r | |
| 29 | #define SII3132_PORT_SIGNATURE_PMP 0x96690101\r | |
| 30 | #define SII3132_PORT_SIGNATURE_ATAPI 0xEB140101\r | |
| 31 | #define SII3132_PORT_SIGNATURE_ATA 0x00000101\r | |
| 32 | \r | |
| 33 | /*\r | |
| 34 | * Silicon Image SiI3132 Registers\r | |
| 35 | */\r | |
| 36 | #define SII3132_GLOBAL_CONTROL_REG 0x40\r | |
| 37 | #define SII3132_GLOBAL_FLASHADDR_REG 0x70\r | |
| 38 | \r | |
| 39 | #define SII3132_PORT_STATUS_REG 0x1000\r | |
| 40 | #define SII3132_PORT_CONTROLSET_REG 0x1000\r | |
| 41 | #define SII3132_PORT_CONTROLCLEAR_REG 0x1004\r | |
| 42 | #define SII3132_PORT_INTSTATUS_REG 0x1008\r | |
| 43 | #define SII3132_PORT_ENABLEINT_REG 0x1010\r | |
| 44 | #define SII3132_PORT_INTCLEAR_REG 0x1014\r | |
| 45 | #define SII3132_PORT_32BITACTIVADDR_REG 0x101C\r | |
| 46 | #define SII3132_PORT_CMDEXECFIFO_REG 0x1020\r | |
| 47 | #define SII3132_PORT_CMDERROR_REG 0x1024\r | |
| 48 | #define SII3132_PORT_ERRCOUNTDECODE 0x1040\r | |
| 49 | #define SII3132_PORT_ERRCOUNTCRC 0x1044\r | |
| 50 | #define SII3132_PORT_ERRCOUNTHANDSHAKE 0x1048\r | |
| 51 | #define SII3132_PORT_SLOTSTATUS_REG 0x1800\r | |
| 52 | #define SII3132_PORT_CMDACTIV_REG 0x1C00\r | |
| 53 | #define SII3132_PORT_SSTATUS_REG 0x1F04\r | |
| 54 | \r | |
| 55 | #define SII3132_PORT_CONTROL_RESET (1 << 0)\r | |
| 56 | #define SII3132_PORT_DEVICE_RESET (1 << 1)\r | |
| 57 | #define SII3132_PORT_CONTROL_INT (1 << 2)\r | |
| 58 | #define SII3132_PORT_CONTROL_32BITACTIVATION (1 << 10)\r | |
| 59 | \r | |
| 60 | #define SII3132_PORT_STATUS_PORTREADY 0x80000000\r | |
| 61 | \r | |
| 62 | #define SII3132_PORT_INT_CMDCOMPL (1 << 0)\r | |
| 63 | #define SII3132_PORT_INT_CMDERR (1 << 1)\r | |
| 64 | #define SII3132_PORT_INT_PORTRDY (1 << 2)\r | |
| 65 | \r | |
| 66 | #define SATA_SII3132_MAXPORT 2\r | |
| 67 | \r | |
| 68 | #define PRB_CTRL_ATA 0x0\r | |
| 69 | #define PRB_CTRL_PROT_OVERRIDE 0x1\r | |
| 70 | #define PRB_CTRL_RESTRANSMIT 0x2\r | |
| 71 | #define PRB_CTRL_EXT_CMD 0x4\r | |
| 72 | #define PRB_CTRL_RCV 0x8\r | |
| 73 | #define PRB_CTRL_PKT_READ 0x10\r | |
| 74 | #define PRB_CTRL_PKT_WRITE 0x20\r | |
| 75 | #define PRB_CTRL_INT_MASK 0x40\r | |
| 76 | #define PRB_CTRL_SRST 0x80\r | |
| 77 | \r | |
| 78 | #define PRB_PROT_PACKET 0x01\r | |
| 79 | #define PRB_PROT_LEGACY_QUEUE 0x02\r | |
| 80 | #define PRB_PROT_NATIVE_QUEUE 0x04\r | |
| 81 | #define PRB_PROT_READ 0x08\r | |
| 82 | #define PRB_PROT_WRITE 0x10\r | |
| 83 | #define PRB_PROT_TRANSPARENT 0x20\r | |
| 84 | \r | |
| 85 | #define SGE_XCF (1 << 28)\r | |
| 86 | #define SGE_DRD (1 << 29)\r | |
| 87 | #define SGE_LNK (1 << 30)\r | |
| 88 | #define SGE_TRM 0x80000000\r | |
| 89 | \r | |
| 90 | typedef struct _SATA_SI3132_SGE {\r | |
| 91 | UINT32 DataAddressLow;\r | |
| 92 | UINT32 DataAddressHigh;\r | |
| 93 | UINT32 DataCount;\r | |
| 94 | UINT32 Attributes;\r | |
| 95 | } SATA_SI3132_SGE;\r | |
| 96 | \r | |
| 97 | typedef struct _SATA_SI3132_FIS {\r | |
| 98 | UINT8 FisType;\r | |
| 99 | UINT8 Control;\r | |
| 100 | UINT8 Command;\r | |
| 101 | UINT8 Features;\r | |
| 102 | UINT8 Fis[5 * 4];\r | |
| 103 | } SATA_SI3132_FIS;\r | |
| 104 | \r | |
| 105 | typedef struct _SATA_SI3132_PRB {\r | |
| 106 | UINT16 Control;\r | |
| 107 | UINT16 ProtocolOverride;\r | |
| 108 | UINT32 RecTransCount;\r | |
| 109 | SATA_SI3132_FIS Fis;\r | |
| 110 | SATA_SI3132_SGE Sge[2];\r | |
| 111 | } SATA_SI3132_PRB;\r | |
| 112 | \r | |
| 113 | typedef struct _SATA_SI3132_DEVICE {\r | |
| 114 | LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)\r | |
| 115 | UINTN Index;\r | |
| 116 | struct _SATA_SI3132_PORT *Port; //Parent Port\r | |
| 117 | UINT32 BlockSize;\r | |
| 118 | } SATA_SI3132_DEVICE;\r | |
| 119 | \r | |
| 120 | typedef struct _SATA_SI3132_PORT {\r | |
| 121 | UINTN Index;\r | |
| 122 | UINTN RegBase;\r | |
| 123 | struct _SATA_SI3132_INSTANCE *Instance;\r | |
| 124 | \r | |
| 125 | //TODO: Support Port multiplier\r | |
| 126 | LIST_ENTRY Devices;\r | |
| 127 | \r | |
| 128 | SATA_SI3132_PRB* HostPRB;\r | |
| 129 | EFI_PHYSICAL_ADDRESS PhysAddrHostPRB;\r | |
| 130 | VOID* PciAllocMappingPRB;\r | |
| 131 | } SATA_SI3132_PORT;\r | |
| 132 | \r | |
| 133 | typedef struct _SATA_SI3132_INSTANCE {\r | |
| 134 | UINTN Signature;\r | |
| 135 | \r | |
| 136 | SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT];\r | |
| 137 | \r | |
| 138 | EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol;\r | |
| 139 | \r | |
| 140 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
| 141 | } SATA_SI3132_INSTANCE;\r | |
| 142 | \r | |
| 143 | #define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2')\r | |
| 144 | #define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE)\r | |
| 145 | \r | |
| 146 | #define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value)\r | |
| 147 | #define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); }\r | |
| 148 | \r | |
| 149 | #define SATA_PORT_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value)\r | |
| 150 | #define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); }\r | |
| 151 | \r | |
| 152 | #define SATA_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n"))\r | |
| 153 | \r | |
| 154 | extern EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName;\r | |
| 155 | extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2;\r | |
| 156 | \r | |
| 157 | /*\r | |
| 158 | * Component Name Protocol Functions\r | |
| 159 | */\r | |
| 160 | EFI_STATUS\r | |
| 161 | EFIAPI\r | |
| 162 | SataSiI3132ComponentNameGetDriverName (\r | |
| 163 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r | |
| 164 | IN CHAR8 *Language,\r | |
| 165 | OUT CHAR16 **DriverName\r | |
| 166 | );\r | |
| 167 | \r | |
| 168 | EFI_STATUS\r | |
| 169 | EFIAPI\r | |
| 170 | SataSiI3132ComponentNameGetControllerName (\r | |
| 171 | IN EFI_COMPONENT_NAME_PROTOCOL *This,\r | |
| 172 | IN EFI_HANDLE ControllerHandle,\r | |
| 173 | IN EFI_HANDLE ChildHandle OPTIONAL,\r | |
| 174 | IN CHAR8 *Language,\r | |
| 175 | OUT CHAR16 **ControllerName\r | |
| 176 | );\r | |
| 177 | \r | |
| 178 | EFI_STATUS SiI3132HwResetPort (SATA_SI3132_PORT *Port);\r | |
| 179 | \r | |
| 180 | /*\r | |
| 181 | * Driver Binding Protocol Functions\r | |
| 182 | */\r | |
| 183 | EFI_STATUS\r | |
| 184 | EFIAPI\r | |
| 185 | SataSiI3132DriverBindingSupported (\r | |
| 186 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
| 187 | IN EFI_HANDLE Controller,\r | |
| 188 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
| 189 | );\r | |
| 190 | \r | |
| 191 | EFI_STATUS\r | |
| 192 | EFIAPI\r | |
| 193 | SataSiI3132DriverBindingStart (\r | |
| 194 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
| 195 | IN EFI_HANDLE Controller,\r | |
| 196 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
| 197 | );\r | |
| 198 | \r | |
| 199 | EFI_STATUS\r | |
| 200 | EFIAPI\r | |
| 201 | SataSiI3132DriverBindingStop (\r | |
| 202 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
| 203 | IN EFI_HANDLE Controller,\r | |
| 204 | IN UINTN NumberOfChildren,\r | |
| 205 | IN EFI_HANDLE *ChildHandleBuffer\r | |
| 206 | );\r | |
| 207 | \r | |
| 7609c047 LE |
208 | EFI_STATUS\r |
| 209 | EFIAPI\r | |
| 210 | SiI3132AtaPassThruCommand (\r | |
| f6342447 OM |
211 | IN SATA_SI3132_INSTANCE *pSataSiI3132Instance,\r |
| 212 | IN SATA_SI3132_PORT *pSataPort,\r | |
| 213 | IN UINT16 PortMultiplierPort,\r | |
| 214 | IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,\r | |
| 215 | IN EFI_EVENT Event OPTIONAL\r | |
| 216 | );\r | |
| 217 | \r | |
| 218 | /**\r | |
| 219 | * EFI ATA Pass Thru Protocol\r | |
| 220 | */\r | |
| 7609c047 LE |
221 | EFI_STATUS\r |
| 222 | EFIAPI\r | |
| 223 | SiI3132AtaPassThru (\r | |
| f6342447 OM |
224 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r |
| 225 | IN UINT16 Port,\r | |
| 226 | IN UINT16 PortMultiplierPort,\r | |
| 227 | IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,\r | |
| 228 | IN EFI_EVENT Event OPTIONAL\r | |
| 229 | );\r | |
| 230 | \r | |
| 7609c047 LE |
231 | EFI_STATUS\r |
| 232 | EFIAPI\r | |
| 233 | SiI3132GetNextPort (\r | |
| f6342447 OM |
234 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r |
| 235 | IN OUT UINT16 *Port\r | |
| 236 | );\r | |
| 237 | \r | |
| 7609c047 LE |
238 | EFI_STATUS\r |
| 239 | EFIAPI\r | |
| 240 | SiI3132GetNextDevice (\r | |
| f6342447 OM |
241 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r |
| 242 | IN UINT16 Port,\r | |
| 243 | IN OUT UINT16 *PortMultiplierPort\r | |
| 244 | );\r | |
| 245 | \r | |
| 7609c047 LE |
246 | EFI_STATUS\r |
| 247 | EFIAPI\r | |
| 248 | SiI3132BuildDevicePath (\r | |
| f6342447 OM |
249 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r |
| 250 | IN UINT16 Port,\r | |
| 251 | IN UINT16 PortMultiplierPort,\r | |
| 252 | IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r | |
| 253 | );\r | |
| 254 | \r | |
| 7609c047 LE |
255 | EFI_STATUS\r |
| 256 | EFIAPI\r | |
| 257 | SiI3132GetDevice (\r | |
| f6342447 OM |
258 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r |
| 259 | IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r | |
| 260 | OUT UINT16 *Port,\r | |
| 261 | OUT UINT16 *PortMultiplierPort\r | |
| 262 | );\r | |
| 263 | \r | |
| 7609c047 LE |
264 | EFI_STATUS\r |
| 265 | EFIAPI\r | |
| 266 | SiI3132ResetPort (\r | |
| f6342447 OM |
267 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r |
| 268 | IN UINT16 Port\r | |
| 269 | );\r | |
| 270 | \r | |
| 7609c047 LE |
271 | EFI_STATUS\r |
| 272 | EFIAPI\r | |
| 273 | SiI3132ResetDevice (\r | |
| f6342447 OM |
274 | IN EFI_ATA_PASS_THRU_PROTOCOL *This,\r |
| 275 | IN UINT16 Port,\r | |
| 276 | IN UINT16 PortMultiplierPort\r | |
| 277 | );\r | |
| 278 | \r | |
| 279 | #endif\r |