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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2006 - 2008, Intel Corporation <BR> \r | |
4 | Portions copyright (c) 2008-2009 Apple Inc. All rights reserved.\r | |
5 | \r | |
6 | All rights reserved. This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | \r | |
17 | #include <PiDxe.h>\r | |
18 | \r | |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/BaseMemoryLib.h>\r | |
22 | #include <Library/UefiBootServicesTableLib.h>\r | |
23 | #include <Library/UefiLib.h>\r | |
24 | #include <Library/MemoryAllocationLib.h>\r | |
25 | #include <Library/DxeServicesTableLib.h>\r | |
26 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
27 | #include <Library/PcdLib.h>\r | |
28 | \r | |
29 | #include <Protocol/Cpu.h>\r | |
30 | #include <Protocol/DebugSupport.h>\r | |
31 | \r | |
32 | \r | |
33 | \r | |
34 | /**\r | |
35 | This function registers and enables the handler specified by InterruptHandler for a processor \r | |
36 | interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r | |
37 | handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r | |
38 | The installed handler is called once for each processor interrupt or exception.\r | |
39 | \r | |
40 | @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r | |
41 | are enabled and FALSE if interrupts are disabled.\r | |
42 | @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r | |
43 | when a processor interrupt occurs. If this parameter is NULL, then the handler\r | |
44 | will be uninstalled.\r | |
45 | \r | |
46 | @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.\r | |
47 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was\r | |
48 | previously installed.\r | |
49 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r | |
50 | previously installed.\r | |
51 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.\r | |
52 | \r | |
53 | **/\r | |
54 | EFI_STATUS\r | |
55 | RegisterInterruptHandler (\r | |
56 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
57 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
58 | );\r | |
59 | \r | |
60 | \r | |
61 | EFI_STATUS\r | |
62 | InitializeExceptions (\r | |
63 | IN EFI_CPU_ARCH_PROTOCOL *Cpu\r | |
64 | );\r | |
65 | \r | |
66 | \r | |
67 | /**\r | |
68 | This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r | |
69 | \r | |
70 | @param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter\r | |
71 | must be between 0 and NumberOfTimers-1.\r | |
72 | @param TimerValue Pointer to the returned timer value.\r | |
73 | @param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment\r | |
74 | of TimerValue.\r | |
75 | \r | |
76 | @retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.\r | |
77 | @retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.\r | |
78 | @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r | |
79 | @retval EFI_UNSUPPORTED The processor does not have any readable timers.\r | |
80 | \r | |
81 | **/\r | |
82 | EFI_STATUS\r | |
83 | GetTimerValue (\r | |
84 | IN UINT32 TimerIndex,\r | |
85 | OUT UINT64 *TimerValue,\r | |
86 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
87 | );\r | |
88 | \r | |
89 | \r | |
90 | /**\r | |
91 | This function flushes the range of addresses from Start to Start+Length \r | |
92 | from the processor's data cache. If Start is not aligned to a cache line \r | |
93 | boundary, then the bytes before Start to the preceding cache line boundary \r | |
94 | are also flushed. If Start+Length is not aligned to a cache line boundary, \r | |
95 | then the bytes past Start+Length to the end of the next cache line boundary \r | |
96 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r | |
97 | supported. If the data cache is fully coherent with all DMA operations, then \r | |
98 | this function can just return EFI_SUCCESS. If the processor does not support \r | |
99 | flushing a range of the data cache, then the entire data cache can be flushed.\r | |
100 | \r | |
101 | @param Start The beginning physical address to flush from the processor's data\r | |
102 | cache.\r | |
103 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
104 | function may flush more bytes than Length specifies depending upon\r | |
105 | the granularity of the flush operation that the processor supports.\r | |
106 | @param FlushType Specifies the type of flush operation to perform.\r | |
107 | \r | |
108 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
109 | the processor's data cache.\r | |
110 | @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r | |
111 | by FlushType.\r | |
112 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
113 | from the processor's data cache.\r | |
114 | \r | |
115 | **/\r | |
116 | EFI_STATUS\r | |
117 | EFIAPI\r | |
118 | FlushCpuDataCache (\r | |
119 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
120 | IN UINT64 Length,\r | |
121 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
122 | );\r | |
123 | \r | |
124 | \r |