[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Isa / IsaSerialDxe / Serial.h

/*++\r
\r
Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.\r
This software and associated documentation (if any) is furnished\r
under a license and may only be used or copied in accordance\r
with the terms of the license. Except as permitted by such\r
license, no part of this software or documentation may be\r
reproduced, stored in a retrieval system, or transmitted in any\r
form or by any means without the express written consent of\r
Intel Corporation.\r
\r
\r
Module Name:\r
\r
  serial.h\r
\r
Abstract:\r
\r
  Include for Serial Driver\r
\r
Revision History:\r
\r
--*/\r
\r
#ifndef _SERIAL_H\r
#define _SERIAL_H\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiDxe.h>\r
#include <FrameworkPei.h>\r
//\r
// The protocols, PPI and GUID defintions for this module\r
//\r
#include <Protocol/IsaIo.h>\r
#include <Protocol/SerialIo.h>\r
#include <Protocol/DevicePath.h>\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/PcdLib.h>\r
//\r
// Driver Binding Externs\r
//\r
extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r
extern EFI_COMPONENT_NAME_PROTOCOL gIsaSerialComponentName;\r
\r
//\r
// Internal Data Structures\r
//\r
#define SERIAL_DEV_SIGNATURE    EFI_SIGNATURE_32 ('s', 'e', 'r', 'd')\r
#define SERIAL_MAX_BUFFER_SIZE  16\r
#define TIMEOUT_STALL_INTERVAL  10\r
\r
//\r
//  Name:   SERIAL_DEV_FIFO\r
//  Purpose:  To define Receive FIFO and Transmit FIFO\r
//  Context:  Used by serial data transmit and receive\r
//  Fields:\r
//      First UINT32: The index of the first data in array Data[]\r
//      Last  UINT32: The index, which you can put a new data into array Data[]\r
//      Surplus UINT32: Identify how many data you can put into array Data[]\r
//      Data[]  UINT8 : An array, which used to store data\r
//\r
typedef struct {\r
  UINT32  First;\r
  UINT32  Last;\r
  UINT32  Surplus;\r
  UINT8   Data[SERIAL_MAX_BUFFER_SIZE];\r
} SERIAL_DEV_FIFO;\r
\r
typedef enum {\r
  UART8250  = 0,\r
  UART16450 = 1,\r
  UART16550 = 2,\r
  UART16550A= 3\r
} EFI_UART_TYPE;\r
\r
//\r
//  Name:   SERIAL_DEV\r
//  Purpose:  To provide device specific information\r
//  Context:\r
//  Fields:\r
//      Signature UINTN: The identity of the serial device\r
//      SerialIo  SERIAL_IO_PROTOCOL: Serial I/O protocol interface\r
//      SerialMode  SERIAL_IO_MODE:\r
//      DevicePath  EFI_DEVICE_PATH_PROTOCOL *: Device path of the serial device\r
//      Handle      EFI_HANDLE: The handle instance attached to serial device\r
//      BaseAddress UINT16: The base address of specific serial device\r
//      Receive     SERIAL_DEV_FIFO: The FIFO used to store data,\r
//                  which is received by UART\r
//      Transmit    SERIAL_DEV_FIFO: The FIFO used to store data,\r
//                  which you want to transmit by UART\r
//      SoftwareLoopbackEnable BOOLEAN:\r
//      Type    EFI_UART_TYPE: Specify the UART type of certain serial device\r
//\r
typedef struct {\r
  UINTN                                  Signature;\r
\r
  EFI_HANDLE                             Handle;\r
  EFI_SERIAL_IO_PROTOCOL                 SerialIo;\r
  EFI_SERIAL_IO_MODE                     SerialMode;\r
  EFI_DEVICE_PATH_PROTOCOL               *DevicePath;\r
\r
  EFI_DEVICE_PATH_PROTOCOL               *ParentDevicePath;\r
  UART_DEVICE_PATH                       UartDevicePath;\r
  EFI_ISA_IO_PROTOCOL                    *IsaIo;\r
\r
  UINT16                                 BaseAddress;\r
  SERIAL_DEV_FIFO                        Receive;\r
  SERIAL_DEV_FIFO                        Transmit;\r
  BOOLEAN                                SoftwareLoopbackEnable;\r
  BOOLEAN                                HardwareFlowControl;\r
  EFI_UART_TYPE                          Type;\r
  EFI_UNICODE_STRING_TABLE               *ControllerNameTable;\r
} SERIAL_DEV;\r
\r
#include "ComponentName.h"\r
\r
#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)\r
\r
//\r
// Globale Variables\r
//\r
extern EFI_DRIVER_BINDING_PROTOCOL  gSerialControllerDriver;\r
\r
//\r
// Serial Driver Defaults\r
//\r
#define SERIAL_PORT_DEFAULT_BAUD_RATE           115200\r
#define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH  1\r
#define SERIAL_PORT_DEFAULT_TIMEOUT             1000000\r
#define SERIAL_PORT_DEFAULT_PARITY              NoParity\r
#define SERIAL_PORT_DEFAULT_DATA_BITS           8\r
#define SERIAL_PORT_DEFAULT_STOP_BITS           1\r
#define SERIAL_PORT_DEFAULT_CONTROL_MASK        0\r
\r
//\r
// (24000000/13)MHz input clock\r
//\r
#define SERIAL_PORT_INPUT_CLOCK 1843200\r
\r
//\r
// 115200 baud with rounding errors\r
//\r
#define SERIAL_PORT_MAX_BAUD_RATE           115400\r
#define SERIAL_PORT_MIN_BAUD_RATE           50\r
\r
#define SERIAL_PORT_MAX_RECEIVE_FIFO_DEPTH  16\r
#define SERIAL_PORT_MIN_TIMEOUT             1         // 1 uS\r
#define SERIAL_PORT_MAX_TIMEOUT             100000000 // 100 seconds\r
//\r
// UART Registers\r
//\r
#define SERIAL_REGISTER_THR 0 // WO   Transmit Holding Register\r
#define SERIAL_REGISTER_RBR 0 // RO   Receive Buffer Register\r
#define SERIAL_REGISTER_DLL 0 // R/W  Divisor Latch LSB\r
#define SERIAL_REGISTER_DLM 1 // R/W  Divisor Latch MSB\r
#define SERIAL_REGISTER_IER 1 // R/W  Interrupt Enable Register\r
#define SERIAL_REGISTER_IIR 2 // RO   Interrupt Identification Register\r
#define SERIAL_REGISTER_FCR 2 // WO   FIFO Cotrol Register\r
#define SERIAL_REGISTER_LCR 3 // R/W  Line Control Register\r
#define SERIAL_REGISTER_MCR 4 // R/W  Modem Control Register\r
#define SERIAL_REGISTER_LSR 5 // R/W  Line Status Register\r
#define SERIAL_REGISTER_MSR 6 // R/W  Modem Status Register\r
#define SERIAL_REGISTER_SCR 7 // R/W  Scratch Pad Register\r
#pragma pack(1)\r
//\r
//  Name:   SERIAL_PORT_IER_BITS\r
//  Purpose:  Define each bit in Interrupt Enable Register\r
//  Context:\r
//  Fields:\r
//     RAVIE  Bit0: Receiver Data Available Interrupt Enable\r
//     THEIE  Bit1: Transmistter Holding Register Empty Interrupt Enable\r
//     RIE      Bit2: Receiver Interrupt Enable\r
//     MIE      Bit3: Modem Interrupt Enable\r
//     Reserved Bit4-Bit7: Reserved\r
//\r
typedef struct {\r
  UINT8 RAVIE : 1;\r
  UINT8 THEIE : 1;\r
  UINT8 RIE : 1;\r
  UINT8 MIE : 1;\r
  UINT8 Reserved : 4;\r
} SERIAL_PORT_IER_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_IER\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_IER_BITS:  Bits of the IER\r
//      Data    UINT8: the value of the IER\r
//\r
typedef union {\r
  SERIAL_PORT_IER_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_IER;\r
\r
//\r
//  Name:   SERIAL_PORT_IIR_BITS\r
//  Purpose:  Define each bit in Interrupt Identification Register\r
//  Context:\r
//  Fields:\r
//      IPS    Bit0: Interrupt Pending Status\r
//      IIB    Bit1-Bit3: Interrupt ID Bits\r
//      Reserved Bit4-Bit5: Reserved\r
//      FIFOES   Bit6-Bit7: FIFO Mode Enable Status\r
//\r
typedef struct {\r
  UINT8 IPS : 1;\r
  UINT8 IIB : 3;\r
  UINT8 Reserved : 2;\r
  UINT8 FIFOES : 2;\r
} SERIAL_PORT_IIR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_IIR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_IIR_BITS:  Bits of the IIR\r
//      Data    UINT8: the value of the IIR\r
//\r
typedef union {\r
  SERIAL_PORT_IIR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_IIR;\r
\r
//\r
//  Name:   SERIAL_PORT_FCR_BITS\r
//  Purpose:  Define each bit in FIFO Control Register\r
//  Context:\r
//  Fields:\r
//      TRFIFOE    Bit0: Transmit and Receive FIFO Enable\r
//      RESETRF    Bit1: Reset Reciever FIFO\r
//      RESETTF    Bit2: Reset Transmistter FIFO\r
//      DMS        Bit3: DMA Mode Select\r
//      Reserved   Bit4-Bit5: Reserved\r
//      RTB        Bit6-Bit7: Receive Trigger Bits\r
//\r
typedef struct {\r
  UINT8 TRFIFOE : 1;\r
  UINT8 RESETRF : 1;\r
  UINT8 RESETTF : 1;\r
  UINT8 DMS : 1;\r
  UINT8 Reserved : 2;\r
  UINT8 RTB : 2;\r
} SERIAL_PORT_FCR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_FCR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_FCR_BITS:  Bits of the FCR\r
//      Data    UINT8: the value of the FCR\r
//\r
typedef union {\r
  SERIAL_PORT_FCR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_FCR;\r
\r
//\r
//  Name:   SERIAL_PORT_LCR_BITS\r
//  Purpose:  Define each bit in Line Control Register\r
//  Context:\r
//  Fields:\r
//      SERIALDB  Bit0-Bit1: Number of Serial Data Bits\r
//      STOPB   Bit2: Number of Stop Bits\r
//      PAREN   Bit3: Parity Enable\r
//      EVENPAR   Bit4: Even Parity Select\r
//      STICPAR   Bit5: Sticky Parity\r
//      BRCON   Bit6: Break Control\r
//      DLAB    Bit7: Divisor Latch Access Bit\r
//\r
typedef struct {\r
  UINT8 SERIALDB : 2;\r
  UINT8 STOPB : 1;\r
  UINT8 PAREN : 1;\r
  UINT8 EVENPAR : 1;\r
  UINT8 STICPAR : 1;\r
  UINT8 BRCON : 1;\r
  UINT8 DLAB : 1;\r
} SERIAL_PORT_LCR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_LCR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_LCR_BITS:  Bits of the LCR\r
//      Data    UINT8: the value of the LCR\r
//\r
typedef union {\r
  SERIAL_PORT_LCR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_LCR;\r
\r
//\r
//  Name:   SERIAL_PORT_MCR_BITS\r
//  Purpose:  Define each bit in Modem Control Register\r
//  Context:\r
//  Fields:\r
//      DTRC     Bit0: Data Terminal Ready Control\r
//      RTS      Bit1: Request To Send Control\r
//      OUT1     Bit2: Output1\r
//      OUT2     Bit3: Output2, used to disable interrupt\r
//      LME;     Bit4: Loopback Mode Enable\r
//      Reserved Bit5-Bit7: Reserved\r
//\r
typedef struct {\r
  UINT8 DTRC : 1;\r
  UINT8 RTS : 1;\r
  UINT8 OUT1 : 1;\r
  UINT8 OUT2 : 1;\r
  UINT8 LME : 1;\r
  UINT8 Reserved : 3;\r
} SERIAL_PORT_MCR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_MCR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_MCR_BITS:  Bits of the MCR\r
//      Data    UINT8: the value of the MCR\r
//\r
typedef union {\r
  SERIAL_PORT_MCR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_MCR;\r
\r
//\r
//  Name:   SERIAL_PORT_LSR_BITS\r
//  Purpose:  Define each bit in Line Status Register\r
//  Context:\r
//  Fields:\r
//      DR    Bit0: Receiver Data Ready Status\r
//      OE    Bit1: Overrun Error Status\r
//      PE    Bit2: Parity Error Status\r
//      FE    Bit3: Framing Error Status\r
//      BI    Bit4: Break Interrupt Status\r
//      THRE  Bit5: Transmistter Holding Register Status\r
//      TEMT  Bit6: Transmitter Empty Status\r
//      FIFOE Bit7: FIFO Error Status\r
//\r
typedef struct {\r
  UINT8 DR : 1;\r
  UINT8 OE : 1;\r
  UINT8 PE : 1;\r
  UINT8 FE : 1;\r
  UINT8 BI : 1;\r
  UINT8 THRE : 1;\r
  UINT8 TEMT : 1;\r
  UINT8 FIFOE : 1;\r
} SERIAL_PORT_LSR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_LSR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_LSR_BITS:  Bits of the LSR\r
//      Data    UINT8: the value of the LSR\r
//\r
typedef union {\r
  SERIAL_PORT_LSR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_LSR;\r
\r
//\r
//  Name:   SERIAL_PORT_MSR_BITS\r
//  Purpose:  Define each bit in Modem Status Register\r
//  Context:\r
//  Fields:\r
//      DeltaCTS      Bit0: Delta Clear To Send Status\r
//      DeltaDSR        Bit1: Delta Data Set Ready Status\r
//      TrailingEdgeRI  Bit2: Trailing Edge of Ring Indicator Status\r
//      DeltaDCD        Bit3: Delta Data Carrier Detect Status\r
//      CTS             Bit4: Clear To Send Status\r
//      DSR             Bit5: Data Set Ready Status\r
//      RI              Bit6: Ring Indicator Status\r
//      DCD             Bit7: Data Carrier Detect Status\r
//\r
typedef struct {\r
  UINT8 DeltaCTS : 1;\r
  UINT8 DeltaDSR : 1;\r
  UINT8 TrailingEdgeRI : 1;\r
  UINT8 DeltaDCD : 1;\r
  UINT8 CTS : 1;\r
  UINT8 DSR : 1;\r
  UINT8 RI : 1;\r
  UINT8 DCD : 1;\r
} SERIAL_PORT_MSR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_MSR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_MSR_BITS:  Bits of the MSR\r
//      Data    UINT8: the value of the MSR\r
//\r
typedef union {\r
  SERIAL_PORT_MSR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_MSR;\r
\r
#pragma pack()\r
//\r
// Define serial register I/O macros\r
//\r
#define READ_RBR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_RBR)\r
#define READ_DLL(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLL)\r
#define READ_DLM(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLM)\r
#define READ_IER(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_IER)\r
#define READ_IIR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_IIR)\r
#define READ_LCR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_LCR)\r
#define READ_MCR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_MCR)\r
#define READ_LSR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_LSR)\r
#define READ_MSR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_MSR)\r
#define READ_SCR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_SCR)\r
\r
#define WRITE_THR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_THR, D)\r
#define WRITE_DLL(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLL, D)\r
#define WRITE_DLM(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLM, D)\r
#define WRITE_IER(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_IER, D)\r
#define WRITE_FCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_FCR, D)\r
#define WRITE_LCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LCR, D)\r
#define WRITE_MCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MCR, D)\r
#define WRITE_LSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LSR, D)\r
#define WRITE_MSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MSR, D)\r
#define WRITE_SCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_SCR, D)\r
\r
//\r
// Prototypes\r
// Driver model protocol interface\r
//\r
\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverSupported (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverStart (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverStop (\r
  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,\r
  IN  EFI_HANDLE                    Controller,\r
  IN  UINTN                         NumberOfChildren,\r
  IN  EFI_HANDLE                    *ChildHandleBuffer\r
  );\r
\r
//\r
// Serial I/O Protocol Interface\r
//\r
EFI_STATUS\r
EFIAPI\r
IsaSerialReset (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialSetAttributes (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN UINT64                         BaudRate,\r
  IN UINT32                         ReceiveFifoDepth,\r
  IN UINT32                         Timeout,\r
  IN EFI_PARITY_TYPE                Parity,\r
  IN UINT8                          DataBits,\r
  IN EFI_STOP_BITS_TYPE             StopBits\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialSetControl (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN UINT32                         Control\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialGetControl (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  OUT UINT32                        *Control\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialWrite (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN OUT UINTN                      *BufferSize,\r
  IN VOID                           *Buffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialRead (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN OUT UINTN                      *BufferSize,\r
  OUT VOID                          *Buffer\r
  );\r
\r
//\r
// Internal Functions\r
//\r
BOOLEAN\r
IsaSerialPortPresent (\r
  IN SERIAL_DEV                     *SerialDevice\r
  );\r
\r
BOOLEAN\r
IsaSerialFifoFull (\r
  IN SERIAL_DEV_FIFO                *Fifo\r
  );\r
\r
BOOLEAN\r
IsaSerialFifoEmpty (\r
  IN SERIAL_DEV_FIFO                *Fifo\r
  );\r
\r
EFI_STATUS\r
IsaSerialFifoAdd (\r
  IN SERIAL_DEV_FIFO                *Fifo,\r
  IN UINT8                          Data\r
  );\r
\r
EFI_STATUS\r
IsaSerialFifoRemove (\r
  IN  SERIAL_DEV_FIFO               *Fifo,\r
  OUT UINT8                         *Data\r
  );\r
\r
EFI_STATUS\r
IsaSerialReceiveTransmit (\r
  IN SERIAL_DEV                     *SerialDevice\r
  );\r
\r
UINT8\r
IsaSerialReadPort (\r
  IN EFI_ISA_IO_PROTOCOL                    *IsaIo,\r
  IN UINT16                                 BaseAddress,\r
  IN UINT32                                 Offset\r
  );\r
\r
VOID\r
IsaSerialWritePort (\r
  IN EFI_ISA_IO_PROTOCOL                    *IsaIo,\r
  IN UINT16                                 BaseAddress,\r
  IN UINT32                                 Offset,\r
  IN UINT8                                  Data\r
  );\r
\r
#endif\r
Commit	Line	Data
637ff819	1	/*++\r
	2	\r
	3	Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.\r
	4	This software and associated documentation (if any) is furnished\r
	5	under a license and may only be used or copied in accordance\r
	6	with the terms of the license. Except as permitted by such\r
	7	license, no part of this software or documentation may be\r
	8	reproduced, stored in a retrieval system, or transmitted in any\r
	9	form or by any means without the express written consent of\r
	10	Intel Corporation.\r
	11	\r
	12	\r
	13	Module Name:\r
	14	\r
	15	serial.h\r
	16	\r
	17	Abstract:\r
	18	\r
	19	Include for Serial Driver\r
	20	\r
	21	Revision History:\r
	22	\r
	23	--*/\r
	24	\r
	25	#ifndef _SERIAL_H\r
	26	#define _SERIAL_H\r
	27	\r
	28	//\r
	29	// The package level header files this module uses\r
	30	//\r
	31	#include <PiDxe.h>\r
	32	#include <FrameworkPei.h>\r
	33	//\r
	34	// The protocols, PPI and GUID defintions for this module\r
	35	//\r
	36	#include <Protocol/IsaIo.h>\r
	37	#include <Protocol/SerialIo.h>\r
	38	#include <Protocol/DevicePath.h>\r
	39	//\r
	40	// The Library classes this module consumes\r
	41	//\r
	42	#include <Library/DebugLib.h>\r
	43	#include <Library/UefiDriverEntryPoint.h>\r
	44	#include <Library/BaseLib.h>\r
	45	#include <Library/UefiLib.h>\r
	46	#include <Library/DevicePathLib.h>\r
	47	#include <Library/BaseMemoryLib.h>\r
	48	#include <Library/MemoryAllocationLib.h>\r
	49	#include <Library/UefiBootServicesTableLib.h>\r
	50	#include <Library/ReportStatusCodeLib.h>\r
	51	#include <Library/PcdLib.h>\r
	52	//\r
	53	// Driver Binding Externs\r
	54	//\r
	55	extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r
	56	extern EFI_COMPONENT_NAME_PROTOCOL gIsaSerialComponentName;\r
	57	\r
	58	//\r
	59	// Internal Data Structures\r
	60	//\r
	61	#define SERIAL_DEV_SIGNATURE EFI_SIGNATURE_32 ('s', 'e', 'r', 'd')\r
	62	#define SERIAL_MAX_BUFFER_SIZE 16\r
	63	#define TIMEOUT_STALL_INTERVAL 10\r
	64	\r
65	//\r
66	// Name: SERIAL_DEV_FIFO\r
67	// Purpose: To define Receive FIFO and Transmit FIFO\r
68	// Context: Used by serial data transmit and receive\r
69	// Fields:\r
70	// First UINT32: The index of the first data in array Data[]\r
71	// Last UINT32: The index, which you can put a new data into array Data[]\r
72	// Surplus UINT32: Identify how many data you can put into array Data[]\r
73	// Data[] UINT8 : An array, which used to store data\r
74	//\r
75	typedef struct {\r
76	UINT32 First;\r
77	UINT32 Last;\r
78	UINT32 Surplus;\r
79	UINT8 Data[SERIAL_MAX_BUFFER_SIZE];\r
80	} SERIAL_DEV_FIFO;\r
81	\r
82	typedef enum {\r
83	UART8250 = 0,\r
84	UART16450 = 1,\r
85	UART16550 = 2,\r
86	UART16550A= 3\r
87	} EFI_UART_TYPE;\r
88	\r
89	//\r
90	// Name: SERIAL_DEV\r
91	// Purpose: To provide device specific information\r
92	// Context:\r
93	// Fields:\r
94	// Signature UINTN: The identity of the serial device\r
95	// SerialIo SERIAL_IO_PROTOCOL: Serial I/O protocol interface\r
96	// SerialMode SERIAL_IO_MODE:\r
97	// DevicePath EFI_DEVICE_PATH_PROTOCOL *: Device path of the serial device\r
98	// Handle EFI_HANDLE: The handle instance attached to serial device\r
99	// BaseAddress UINT16: The base address of specific serial device\r
100	// Receive SERIAL_DEV_FIFO: The FIFO used to store data,\r
101	// which is received by UART\r
102	// Transmit SERIAL_DEV_FIFO: The FIFO used to store data,\r
103	// which you want to transmit by UART\r
104	// SoftwareLoopbackEnable BOOLEAN:\r
105	// Type EFI_UART_TYPE: Specify the UART type of certain serial device\r
106	//\r
107	typedef struct {\r
108	UINTN Signature;\r
109	\r
110	EFI_HANDLE Handle;\r
111	EFI_SERIAL_IO_PROTOCOL SerialIo;\r
112	EFI_SERIAL_IO_MODE SerialMode;\r
113	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
114	\r
115	EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r
116	UART_DEVICE_PATH UartDevicePath;\r
117	EFI_ISA_IO_PROTOCOL *IsaIo;\r
118	\r
119	UINT16 BaseAddress;\r
120	SERIAL_DEV_FIFO Receive;\r
121	SERIAL_DEV_FIFO Transmit;\r
122	BOOLEAN SoftwareLoopbackEnable;\r
123	BOOLEAN HardwareFlowControl;\r
124	EFI_UART_TYPE Type;\r
125	EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
126	} SERIAL_DEV;\r
127	\r
128	#include "ComponentName.h"\r
129	\r
130	#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)\r
131	\r
132	//\r
133	// Globale Variables\r
134	//\r
135	extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r
136	\r
137	//\r
138	// Serial Driver Defaults\r
139	//\r
140	#define SERIAL_PORT_DEFAULT_BAUD_RATE 115200\r
141	#define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH 1\r
142	#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000\r
143	#define SERIAL_PORT_DEFAULT_PARITY NoParity\r
144	#define SERIAL_PORT_DEFAULT_DATA_BITS 8\r
145	#define SERIAL_PORT_DEFAULT_STOP_BITS 1\r
146	#define SERIAL_PORT_DEFAULT_CONTROL_MASK 0\r
147	\r
148	//\r
149	// (24000000/13)MHz input clock\r
150	//\r
151	#define SERIAL_PORT_INPUT_CLOCK 1843200\r
152	\r
153	//\r
154	// 115200 baud with rounding errors\r
155	//\r
156	#define SERIAL_PORT_MAX_BAUD_RATE 115400\r
157	#define SERIAL_PORT_MIN_BAUD_RATE 50\r
158	\r
159	#define SERIAL_PORT_MAX_RECEIVE_FIFO_DEPTH 16\r
160	#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS\r
161	#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds\r
162	//\r
163	// UART Registers\r
164	//\r
165	#define SERIAL_REGISTER_THR 0 // WO Transmit Holding Register\r
166	#define SERIAL_REGISTER_RBR 0 // RO Receive Buffer Register\r
167	#define SERIAL_REGISTER_DLL 0 // R/W Divisor Latch LSB\r
168	#define SERIAL_REGISTER_DLM 1 // R/W Divisor Latch MSB\r
169	#define SERIAL_REGISTER_IER 1 // R/W Interrupt Enable Register\r
170	#define SERIAL_REGISTER_IIR 2 // RO Interrupt Identification Register\r
171	#define SERIAL_REGISTER_FCR 2 // WO FIFO Cotrol Register\r
172	#define SERIAL_REGISTER_LCR 3 // R/W Line Control Register\r
173	#define SERIAL_REGISTER_MCR 4 // R/W Modem Control Register\r
174	#define SERIAL_REGISTER_LSR 5 // R/W Line Status Register\r
175	#define SERIAL_REGISTER_MSR 6 // R/W Modem Status Register\r
176	#define SERIAL_REGISTER_SCR 7 // R/W Scratch Pad Register\r
177	#pragma pack(1)\r
178	//\r
179	// Name: SERIAL_PORT_IER_BITS\r
180	// Purpose: Define each bit in Interrupt Enable Register\r
181	// Context:\r
182	// Fields:\r
183	// RAVIE Bit0: Receiver Data Available Interrupt Enable\r
184	// THEIE Bit1: Transmistter Holding Register Empty Interrupt Enable\r
185	// RIE Bit2: Receiver Interrupt Enable\r
186	// MIE Bit3: Modem Interrupt Enable\r
187	// Reserved Bit4-Bit7: Reserved\r
188	//\r
189	typedef struct {\r
190	UINT8 RAVIE : 1;\r
191	UINT8 THEIE : 1;\r
192	UINT8 RIE : 1;\r
193	UINT8 MIE : 1;\r
194	UINT8 Reserved : 4;\r
195	} SERIAL_PORT_IER_BITS;\r
196	\r
197	//\r
198	// Name: SERIAL_PORT_IER\r
199	// Purpose:\r
200	// Context:\r
201	// Fields:\r
202	// Bits SERIAL_PORT_IER_BITS: Bits of the IER\r
203	// Data UINT8: the value of the IER\r
204	//\r
205	typedef union {\r
206	SERIAL_PORT_IER_BITS Bits;\r
207	UINT8 Data;\r
208	} SERIAL_PORT_IER;\r
209	\r
210	//\r
211	// Name: SERIAL_PORT_IIR_BITS\r
212	// Purpose: Define each bit in Interrupt Identification Register\r
213	// Context:\r
214	// Fields:\r
215	// IPS Bit0: Interrupt Pending Status\r
216	// IIB Bit1-Bit3: Interrupt ID Bits\r
217	// Reserved Bit4-Bit5: Reserved\r
218	// FIFOES Bit6-Bit7: FIFO Mode Enable Status\r
219	//\r
220	typedef struct {\r
221	UINT8 IPS : 1;\r
222	UINT8 IIB : 3;\r
223	UINT8 Reserved : 2;\r
224	UINT8 FIFOES : 2;\r
225	} SERIAL_PORT_IIR_BITS;\r
226	\r
227	//\r
228	// Name: SERIAL_PORT_IIR\r
229	// Purpose:\r
230	// Context:\r
231	// Fields:\r
232	// Bits SERIAL_PORT_IIR_BITS: Bits of the IIR\r
233	// Data UINT8: the value of the IIR\r
234	//\r
235	typedef union {\r
236	SERIAL_PORT_IIR_BITS Bits;\r
237	UINT8 Data;\r
238	} SERIAL_PORT_IIR;\r
239	\r
240	//\r
241	// Name: SERIAL_PORT_FCR_BITS\r
242	// Purpose: Define each bit in FIFO Control Register\r
243	// Context:\r
244	// Fields:\r
245	// TRFIFOE Bit0: Transmit and Receive FIFO Enable\r
246	// RESETRF Bit1: Reset Reciever FIFO\r
247	// RESETTF Bit2: Reset Transmistter FIFO\r
248	// DMS Bit3: DMA Mode Select\r
249	// Reserved Bit4-Bit5: Reserved\r
250	// RTB Bit6-Bit7: Receive Trigger Bits\r
251	//\r
252	typedef struct {\r
253	UINT8 TRFIFOE : 1;\r
254	UINT8 RESETRF : 1;\r
255	UINT8 RESETTF : 1;\r
256	UINT8 DMS : 1;\r
257	UINT8 Reserved : 2;\r
258	UINT8 RTB : 2;\r
259	} SERIAL_PORT_FCR_BITS;\r
260	\r
261	//\r
262	// Name: SERIAL_PORT_FCR\r
263	// Purpose:\r
264	// Context:\r
265	// Fields:\r
266	// Bits SERIAL_PORT_FCR_BITS: Bits of the FCR\r
267	// Data UINT8: the value of the FCR\r
268	//\r
269	typedef union {\r
270	SERIAL_PORT_FCR_BITS Bits;\r
271	UINT8 Data;\r
272	} SERIAL_PORT_FCR;\r
273	\r
274	//\r
275	// Name: SERIAL_PORT_LCR_BITS\r
276	// Purpose: Define each bit in Line Control Register\r
277	// Context:\r
278	// Fields:\r
279	// SERIALDB Bit0-Bit1: Number of Serial Data Bits\r
280	// STOPB Bit2: Number of Stop Bits\r
281	// PAREN Bit3: Parity Enable\r
282	// EVENPAR Bit4: Even Parity Select\r
283	// STICPAR Bit5: Sticky Parity\r
284	// BRCON Bit6: Break Control\r
285	// DLAB Bit7: Divisor Latch Access Bit\r
286	//\r
287	typedef struct {\r
288	UINT8 SERIALDB : 2;\r
289	UINT8 STOPB : 1;\r
290	UINT8 PAREN : 1;\r
291	UINT8 EVENPAR : 1;\r
292	UINT8 STICPAR : 1;\r
293	UINT8 BRCON : 1;\r
294	UINT8 DLAB : 1;\r
295	} SERIAL_PORT_LCR_BITS;\r
296	\r
297	//\r
298	// Name: SERIAL_PORT_LCR\r
299	// Purpose:\r
300	// Context:\r
301	// Fields:\r
302	// Bits SERIAL_PORT_LCR_BITS: Bits of the LCR\r
303	// Data UINT8: the value of the LCR\r
304	//\r
305	typedef union {\r
306	SERIAL_PORT_LCR_BITS Bits;\r
307	UINT8 Data;\r
308	} SERIAL_PORT_LCR;\r
309	\r
310	//\r
311	// Name: SERIAL_PORT_MCR_BITS\r
312	// Purpose: Define each bit in Modem Control Register\r
313	// Context:\r
314	// Fields:\r
315	// DTRC Bit0: Data Terminal Ready Control\r
316	// RTS Bit1: Request To Send Control\r
317	// OUT1 Bit2: Output1\r
318	// OUT2 Bit3: Output2, used to disable interrupt\r
319	// LME; Bit4: Loopback Mode Enable\r
320	// Reserved Bit5-Bit7: Reserved\r
321	//\r
322	typedef struct {\r
323	UINT8 DTRC : 1;\r
324	UINT8 RTS : 1;\r
325	UINT8 OUT1 : 1;\r
326	UINT8 OUT2 : 1;\r
327	UINT8 LME : 1;\r
328	UINT8 Reserved : 3;\r
329	} SERIAL_PORT_MCR_BITS;\r
330	\r
331	//\r
332	// Name: SERIAL_PORT_MCR\r
333	// Purpose:\r
334	// Context:\r
335	// Fields:\r
336	// Bits SERIAL_PORT_MCR_BITS: Bits of the MCR\r
337	// Data UINT8: the value of the MCR\r
338	//\r
339	typedef union {\r
340	SERIAL_PORT_MCR_BITS Bits;\r
341	UINT8 Data;\r
342	} SERIAL_PORT_MCR;\r
343	\r
344	//\r
345	// Name: SERIAL_PORT_LSR_BITS\r
346	// Purpose: Define each bit in Line Status Register\r
347	// Context:\r
348	// Fields:\r
349	// DR Bit0: Receiver Data Ready Status\r
350	// OE Bit1: Overrun Error Status\r
351	// PE Bit2: Parity Error Status\r
352	// FE Bit3: Framing Error Status\r
353	// BI Bit4: Break Interrupt Status\r
354	// THRE Bit5: Transmistter Holding Register Status\r
355	// TEMT Bit6: Transmitter Empty Status\r
356	// FIFOE Bit7: FIFO Error Status\r
357	//\r
358	typedef struct {\r
359	UINT8 DR : 1;\r
360	UINT8 OE : 1;\r
361	UINT8 PE : 1;\r
362	UINT8 FE : 1;\r
363	UINT8 BI : 1;\r
364	UINT8 THRE : 1;\r
365	UINT8 TEMT : 1;\r
366	UINT8 FIFOE : 1;\r
367	} SERIAL_PORT_LSR_BITS;\r
368	\r
369	//\r
370	// Name: SERIAL_PORT_LSR\r
371	// Purpose:\r
372	// Context:\r
373	// Fields:\r
374	// Bits SERIAL_PORT_LSR_BITS: Bits of the LSR\r
375	// Data UINT8: the value of the LSR\r
376	//\r
377	typedef union {\r
378	SERIAL_PORT_LSR_BITS Bits;\r
379	UINT8 Data;\r
380	} SERIAL_PORT_LSR;\r
381	\r
382	//\r
383	// Name: SERIAL_PORT_MSR_BITS\r
384	// Purpose: Define each bit in Modem Status Register\r
385	// Context:\r
386	// Fields:\r
387	// DeltaCTS Bit0: Delta Clear To Send Status\r
388	// DeltaDSR Bit1: Delta Data Set Ready Status\r
389	// TrailingEdgeRI Bit2: Trailing Edge of Ring Indicator Status\r
390	// DeltaDCD Bit3: Delta Data Carrier Detect Status\r
391	// CTS Bit4: Clear To Send Status\r
392	// DSR Bit5: Data Set Ready Status\r
393	// RI Bit6: Ring Indicator Status\r
394	// DCD Bit7: Data Carrier Detect Status\r
395	//\r
396	typedef struct {\r
397	UINT8 DeltaCTS : 1;\r
398	UINT8 DeltaDSR : 1;\r
399	UINT8 TrailingEdgeRI : 1;\r
400	UINT8 DeltaDCD : 1;\r
401	UINT8 CTS : 1;\r
402	UINT8 DSR : 1;\r
403	UINT8 RI : 1;\r
404	UINT8 DCD : 1;\r
405	} SERIAL_PORT_MSR_BITS;\r
406	\r
407	//\r
408	// Name: SERIAL_PORT_MSR\r
409	// Purpose:\r
410	// Context:\r
411	// Fields:\r
412	// Bits SERIAL_PORT_MSR_BITS: Bits of the MSR\r
413	// Data UINT8: the value of the MSR\r
414	//\r
415	typedef union {\r
416	SERIAL_PORT_MSR_BITS Bits;\r
417	UINT8 Data;\r
418	} SERIAL_PORT_MSR;\r
419	\r
420	#pragma pack()\r
421	//\r
422	// Define serial register I/O macros\r
423	//\r
424	#define READ_RBR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_RBR)\r
425	#define READ_DLL(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLL)\r
426	#define READ_DLM(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLM)\r
427	#define READ_IER(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IER)\r
428	#define READ_IIR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IIR)\r
429	#define READ_LCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LCR)\r
430	#define READ_MCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MCR)\r
431	#define READ_LSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LSR)\r
432	#define READ_MSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MSR)\r
433	#define READ_SCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_SCR)\r
434	\r
435	#define WRITE_THR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_THR, D)\r
436	#define WRITE_DLL(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLL, D)\r
437	#define WRITE_DLM(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLM, D)\r
438	#define WRITE_IER(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_IER, D)\r
439	#define WRITE_FCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_FCR, D)\r
440	#define WRITE_LCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LCR, D)\r
441	#define WRITE_MCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MCR, D)\r
442	#define WRITE_LSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LSR, D)\r
443	#define WRITE_MSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MSR, D)\r
444	#define WRITE_SCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_SCR, D)\r
445	\r
446	//\r
447	// Prototypes\r
448	// Driver model protocol interface\r
449	//\r
450	\r
451	EFI_STATUS\r
452	EFIAPI\r
453	SerialControllerDriverSupported (\r
454	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
455	IN EFI_HANDLE Controller,\r
456	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
457	);\r
458	\r
459	EFI_STATUS\r
460	EFIAPI\r
461	SerialControllerDriverStart (\r
462	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
463	IN EFI_HANDLE Controller,\r
464	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
465	);\r
466	\r
467	EFI_STATUS\r
468	EFIAPI\r
469	SerialControllerDriverStop (\r
470	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
471	IN EFI_HANDLE Controller,\r
472	IN UINTN NumberOfChildren,\r
473	IN EFI_HANDLE *ChildHandleBuffer\r
474	);\r
475	\r
476	//\r
477	// Serial I/O Protocol Interface\r
478	//\r
479	EFI_STATUS\r
480	EFIAPI\r
481	IsaSerialReset (\r
482	IN EFI_SERIAL_IO_PROTOCOL *This\r
483	);\r
484	\r
485	EFI_STATUS\r
486	EFIAPI\r
487	IsaSerialSetAttributes (\r
488	IN EFI_SERIAL_IO_PROTOCOL *This,\r
489	IN UINT64 BaudRate,\r
490	IN UINT32 ReceiveFifoDepth,\r
491	IN UINT32 Timeout,\r
492	IN EFI_PARITY_TYPE Parity,\r
493	IN UINT8 DataBits,\r
494	IN EFI_STOP_BITS_TYPE StopBits\r
495	);\r
496	\r
497	EFI_STATUS\r
498	EFIAPI\r
499	IsaSerialSetControl (\r
500	IN EFI_SERIAL_IO_PROTOCOL *This,\r
501	IN UINT32 Control\r
502	);\r
503	\r
504	EFI_STATUS\r
505	EFIAPI\r
506	IsaSerialGetControl (\r
507	IN EFI_SERIAL_IO_PROTOCOL *This,\r
508	OUT UINT32 *Control\r
509	);\r
510	\r
511	EFI_STATUS\r
512	EFIAPI\r
513	IsaSerialWrite (\r
514	IN EFI_SERIAL_IO_PROTOCOL *This,\r
515	IN OUT UINTN *BufferSize,\r
516	IN VOID *Buffer\r
517	);\r
518	\r
519	EFI_STATUS\r
520	EFIAPI\r
521	IsaSerialRead (\r
522	IN EFI_SERIAL_IO_PROTOCOL *This,\r
523	IN OUT UINTN *BufferSize,\r
524	OUT VOID *Buffer\r
525	);\r
526	\r
527	//\r
528	// Internal Functions\r
529	//\r
530	BOOLEAN\r
531	IsaSerialPortPresent (\r
532	IN SERIAL_DEV *SerialDevice\r
533	);\r
534	\r
535	BOOLEAN\r
536	IsaSerialFifoFull (\r
537	IN SERIAL_DEV_FIFO *Fifo\r
538	);\r
539	\r
540	BOOLEAN\r
541	IsaSerialFifoEmpty (\r
542	IN SERIAL_DEV_FIFO *Fifo\r
543	);\r
544	\r
545	EFI_STATUS\r
546	IsaSerialFifoAdd (\r
547	IN SERIAL_DEV_FIFO *Fifo,\r
548	IN UINT8 Data\r
549	);\r
550	\r
551	EFI_STATUS\r
552	IsaSerialFifoRemove (\r
553	IN SERIAL_DEV_FIFO *Fifo,\r
554	OUT UINT8 *Data\r
555	);\r
556	\r
557	EFI_STATUS\r
558	IsaSerialReceiveTransmit (\r
559	IN SERIAL_DEV *SerialDevice\r
560	);\r
561	\r
562	UINT8\r
563	IsaSerialReadPort (\r
564	IN EFI_ISA_IO_PROTOCOL *IsaIo,\r
565	IN UINT16 BaseAddress,\r
566	IN UINT32 Offset\r
567	);\r
568	\r
569	VOID\r
570	IsaSerialWritePort (\r
571	IN EFI_ISA_IO_PROTOCOL *IsaIo,\r
572	IN UINT16 BaseAddress,\r
573	IN UINT32 Offset,\r
574	IN UINT8 Data\r
575	);\r
576	\r
577	#endif\r