[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Isa / IsaSerialDxe / Serial.h

/**@file\r
  Include for Serial Driver\r
  \r
Copyright (c) 2006 - 2007, Intel Corporation.<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _SERIAL_H\r
#define _SERIAL_H\r
\r
\r
#include <PiDxe.h>\r
#include <FrameworkPei.h>\r
\r
#include <Protocol/IsaIo.h>\r
#include <Protocol/SerialIo.h>\r
#include <Protocol/DevicePath.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/PcdLib.h>\r
//\r
// Driver Binding Externs\r
//\r
extern EFI_DRIVER_BINDING_PROTOCOL  gSerialControllerDriver;\r
extern EFI_COMPONENT_NAME_PROTOCOL  gIsaSerialComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL gIsaSerialComponentName2;\r
\r
//\r
// Internal Data Structures\r
//\r
#define SERIAL_DEV_SIGNATURE    SIGNATURE_32 ('s', 'e', 'r', 'd')\r
#define SERIAL_MAX_BUFFER_SIZE  16\r
#define TIMEOUT_STALL_INTERVAL  10\r
\r
//\r
//  Name:   SERIAL_DEV_FIFO\r
//  Purpose:  To define Receive FIFO and Transmit FIFO\r
//  Context:  Used by serial data transmit and receive\r
//  Fields:\r
//      First UINT32: The index of the first data in array Data[]\r
//      Last  UINT32: The index, which you can put a new data into array Data[]\r
//      Surplus UINT32: Identify how many data you can put into array Data[]\r
//      Data[]  UINT8 : An array, which used to store data\r
//\r
typedef struct {\r
  UINT32  First;\r
  UINT32  Last;\r
  UINT32  Surplus;\r
  UINT8   Data[SERIAL_MAX_BUFFER_SIZE];\r
} SERIAL_DEV_FIFO;\r
\r
typedef enum {\r
  UART8250  = 0,\r
  UART16450 = 1,\r
  UART16550 = 2,\r
  UART16550A= 3\r
} EFI_UART_TYPE;\r
\r
//\r
//  Name:   SERIAL_DEV\r
//  Purpose:  To provide device specific information\r
//  Context:\r
//  Fields:\r
//      Signature UINTN: The identity of the serial device\r
//      SerialIo  SERIAL_IO_PROTOCOL: Serial I/O protocol interface\r
//      SerialMode  SERIAL_IO_MODE:\r
//      DevicePath  EFI_DEVICE_PATH_PROTOCOL *: Device path of the serial device\r
//      Handle      EFI_HANDLE: The handle instance attached to serial device\r
//      BaseAddress UINT16: The base address of specific serial device\r
//      Receive     SERIAL_DEV_FIFO: The FIFO used to store data,\r
//                  which is received by UART\r
//      Transmit    SERIAL_DEV_FIFO: The FIFO used to store data,\r
//                  which you want to transmit by UART\r
//      SoftwareLoopbackEnable BOOLEAN:\r
//      Type    EFI_UART_TYPE: Specify the UART type of certain serial device\r
//\r
typedef struct {\r
  UINTN                                  Signature;\r
\r
  EFI_HANDLE                             Handle;\r
  EFI_SERIAL_IO_PROTOCOL                 SerialIo;\r
  EFI_SERIAL_IO_MODE                     SerialMode;\r
  EFI_DEVICE_PATH_PROTOCOL               *DevicePath;\r
\r
  EFI_DEVICE_PATH_PROTOCOL               *ParentDevicePath;\r
  UART_DEVICE_PATH                       UartDevicePath;\r
  EFI_ISA_IO_PROTOCOL                    *IsaIo;\r
\r
  UINT16                                 BaseAddress;\r
  SERIAL_DEV_FIFO                        Receive;\r
  SERIAL_DEV_FIFO                        Transmit;\r
  BOOLEAN                                SoftwareLoopbackEnable;\r
  BOOLEAN                                HardwareFlowControl;\r
  EFI_UART_TYPE                          Type;\r
  EFI_UNICODE_STRING_TABLE               *ControllerNameTable;\r
} SERIAL_DEV;\r
\r
#include "ComponentName.h"\r
\r
#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)\r
\r
//\r
// Globale Variables\r
//\r
extern EFI_DRIVER_BINDING_PROTOCOL   gSerialControllerDriver;\r
\r
//\r
// Serial Driver Defaults\r
//\r
#define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH  1\r
#define SERIAL_PORT_DEFAULT_TIMEOUT             1000000\r
\r
/*\r
#define SERIAL_PORT_DEFAULT_BAUD_RATE           115200\r
#define SERIAL_PORT_DEFAULT_PARITY              NoParity\r
#define SERIAL_PORT_DEFAULT_DATA_BITS           8\r
#define SERIAL_PORT_DEFAULT_STOP_BITS           1\r
*/\r
#define SERIAL_PORT_DEFAULT_CONTROL_MASK        0\r
\r
\r
//\r
// (24000000/13)MHz input clock\r
//\r
#define SERIAL_PORT_INPUT_CLOCK 1843200\r
\r
//\r
// 115200 baud with rounding errors\r
//\r
#define SERIAL_PORT_MAX_BAUD_RATE           115400\r
#define SERIAL_PORT_MIN_BAUD_RATE           50\r
\r
#define SERIAL_PORT_MAX_RECEIVE_FIFO_DEPTH  16\r
#define SERIAL_PORT_MIN_TIMEOUT             1         // 1 uS\r
#define SERIAL_PORT_MAX_TIMEOUT             100000000 // 100 seconds\r
//\r
// UART Registers\r
//\r
#define SERIAL_REGISTER_THR 0 // WO   Transmit Holding Register\r
#define SERIAL_REGISTER_RBR 0 // RO   Receive Buffer Register\r
#define SERIAL_REGISTER_DLL 0 // R/W  Divisor Latch LSB\r
#define SERIAL_REGISTER_DLM 1 // R/W  Divisor Latch MSB\r
#define SERIAL_REGISTER_IER 1 // R/W  Interrupt Enable Register\r
#define SERIAL_REGISTER_IIR 2 // RO   Interrupt Identification Register\r
#define SERIAL_REGISTER_FCR 2 // WO   FIFO Cotrol Register\r
#define SERIAL_REGISTER_LCR 3 // R/W  Line Control Register\r
#define SERIAL_REGISTER_MCR 4 // R/W  Modem Control Register\r
#define SERIAL_REGISTER_LSR 5 // R/W  Line Status Register\r
#define SERIAL_REGISTER_MSR 6 // R/W  Modem Status Register\r
#define SERIAL_REGISTER_SCR 7 // R/W  Scratch Pad Register\r
#pragma pack(1)\r
//\r
//  Name:   SERIAL_PORT_IER_BITS\r
//  Purpose:  Define each bit in Interrupt Enable Register\r
//  Context:\r
//  Fields:\r
//     RAVIE  Bit0: Receiver Data Available Interrupt Enable\r
//     THEIE  Bit1: Transmistter Holding Register Empty Interrupt Enable\r
//     RIE      Bit2: Receiver Interrupt Enable\r
//     MIE      Bit3: Modem Interrupt Enable\r
//     Reserved Bit4-Bit7: Reserved\r
//\r
typedef struct {\r
  UINT8 RAVIE : 1;\r
  UINT8 THEIE : 1;\r
  UINT8 RIE : 1;\r
  UINT8 MIE : 1;\r
  UINT8 Reserved : 4;\r
} SERIAL_PORT_IER_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_IER\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_IER_BITS:  Bits of the IER\r
//      Data    UINT8: the value of the IER\r
//\r
typedef union {\r
  SERIAL_PORT_IER_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_IER;\r
\r
//\r
//  Name:   SERIAL_PORT_IIR_BITS\r
//  Purpose:  Define each bit in Interrupt Identification Register\r
//  Context:\r
//  Fields:\r
//      IPS    Bit0: Interrupt Pending Status\r
//      IIB    Bit1-Bit3: Interrupt ID Bits\r
//      Reserved Bit4-Bit5: Reserved\r
//      FIFOES   Bit6-Bit7: FIFO Mode Enable Status\r
//\r
typedef struct {\r
  UINT8 IPS : 1;\r
  UINT8 IIB : 3;\r
  UINT8 Reserved : 2;\r
  UINT8 FIFOES : 2;\r
} SERIAL_PORT_IIR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_IIR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_IIR_BITS:  Bits of the IIR\r
//      Data    UINT8: the value of the IIR\r
//\r
typedef union {\r
  SERIAL_PORT_IIR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_IIR;\r
\r
//\r
//  Name:   SERIAL_PORT_FCR_BITS\r
//  Purpose:  Define each bit in FIFO Control Register\r
//  Context:\r
//  Fields:\r
//      TRFIFOE    Bit0: Transmit and Receive FIFO Enable\r
//      RESETRF    Bit1: Reset Reciever FIFO\r
//      RESETTF    Bit2: Reset Transmistter FIFO\r
//      DMS        Bit3: DMA Mode Select\r
//      Reserved   Bit4-Bit5: Reserved\r
//      RTB        Bit6-Bit7: Receive Trigger Bits\r
//\r
typedef struct {\r
  UINT8 TRFIFOE : 1;\r
  UINT8 RESETRF : 1;\r
  UINT8 RESETTF : 1;\r
  UINT8 DMS : 1;\r
  UINT8 Reserved : 2;\r
  UINT8 RTB : 2;\r
} SERIAL_PORT_FCR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_FCR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_FCR_BITS:  Bits of the FCR\r
//      Data    UINT8: the value of the FCR\r
//\r
typedef union {\r
  SERIAL_PORT_FCR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_FCR;\r
\r
//\r
//  Name:   SERIAL_PORT_LCR_BITS\r
//  Purpose:  Define each bit in Line Control Register\r
//  Context:\r
//  Fields:\r
//      SERIALDB  Bit0-Bit1: Number of Serial Data Bits\r
//      STOPB   Bit2: Number of Stop Bits\r
//      PAREN   Bit3: Parity Enable\r
//      EVENPAR   Bit4: Even Parity Select\r
//      STICPAR   Bit5: Sticky Parity\r
//      BRCON   Bit6: Break Control\r
//      DLAB    Bit7: Divisor Latch Access Bit\r
//\r
typedef struct {\r
  UINT8 SERIALDB : 2;\r
  UINT8 STOPB : 1;\r
  UINT8 PAREN : 1;\r
  UINT8 EVENPAR : 1;\r
  UINT8 STICPAR : 1;\r
  UINT8 BRCON : 1;\r
  UINT8 DLAB : 1;\r
} SERIAL_PORT_LCR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_LCR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_LCR_BITS:  Bits of the LCR\r
//      Data    UINT8: the value of the LCR\r
//\r
typedef union {\r
  SERIAL_PORT_LCR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_LCR;\r
\r
//\r
//  Name:   SERIAL_PORT_MCR_BITS\r
//  Purpose:  Define each bit in Modem Control Register\r
//  Context:\r
//  Fields:\r
//      DTRC     Bit0: Data Terminal Ready Control\r
//      RTS      Bit1: Request To Send Control\r
//      OUT1     Bit2: Output1\r
//      OUT2     Bit3: Output2, used to disable interrupt\r
//      LME;     Bit4: Loopback Mode Enable\r
//      Reserved Bit5-Bit7: Reserved\r
//\r
typedef struct {\r
  UINT8 DTRC : 1;\r
  UINT8 RTS : 1;\r
  UINT8 OUT1 : 1;\r
  UINT8 OUT2 : 1;\r
  UINT8 LME : 1;\r
  UINT8 Reserved : 3;\r
} SERIAL_PORT_MCR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_MCR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_MCR_BITS:  Bits of the MCR\r
//      Data    UINT8: the value of the MCR\r
//\r
typedef union {\r
  SERIAL_PORT_MCR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_MCR;\r
\r
//\r
//  Name:   SERIAL_PORT_LSR_BITS\r
//  Purpose:  Define each bit in Line Status Register\r
//  Context:\r
//  Fields:\r
//      DR    Bit0: Receiver Data Ready Status\r
//      OE    Bit1: Overrun Error Status\r
//      PE    Bit2: Parity Error Status\r
//      FE    Bit3: Framing Error Status\r
//      BI    Bit4: Break Interrupt Status\r
//      THRE  Bit5: Transmistter Holding Register Status\r
//      TEMT  Bit6: Transmitter Empty Status\r
//      FIFOE Bit7: FIFO Error Status\r
//\r
typedef struct {\r
  UINT8 DR : 1;\r
  UINT8 OE : 1;\r
  UINT8 PE : 1;\r
  UINT8 FE : 1;\r
  UINT8 BI : 1;\r
  UINT8 THRE : 1;\r
  UINT8 TEMT : 1;\r
  UINT8 FIFOE : 1;\r
} SERIAL_PORT_LSR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_LSR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_LSR_BITS:  Bits of the LSR\r
//      Data    UINT8: the value of the LSR\r
//\r
typedef union {\r
  SERIAL_PORT_LSR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_LSR;\r
\r
//\r
//  Name:   SERIAL_PORT_MSR_BITS\r
//  Purpose:  Define each bit in Modem Status Register\r
//  Context:\r
//  Fields:\r
//      DeltaCTS      Bit0: Delta Clear To Send Status\r
//      DeltaDSR        Bit1: Delta Data Set Ready Status\r
//      TrailingEdgeRI  Bit2: Trailing Edge of Ring Indicator Status\r
//      DeltaDCD        Bit3: Delta Data Carrier Detect Status\r
//      CTS             Bit4: Clear To Send Status\r
//      DSR             Bit5: Data Set Ready Status\r
//      RI              Bit6: Ring Indicator Status\r
//      DCD             Bit7: Data Carrier Detect Status\r
//\r
typedef struct {\r
  UINT8 DeltaCTS : 1;\r
  UINT8 DeltaDSR : 1;\r
  UINT8 TrailingEdgeRI : 1;\r
  UINT8 DeltaDCD : 1;\r
  UINT8 CTS : 1;\r
  UINT8 DSR : 1;\r
  UINT8 RI : 1;\r
  UINT8 DCD : 1;\r
} SERIAL_PORT_MSR_BITS;\r
\r
//\r
//  Name:   SERIAL_PORT_MSR\r
//  Purpose:\r
//  Context:\r
//  Fields:\r
//      Bits    SERIAL_PORT_MSR_BITS:  Bits of the MSR\r
//      Data    UINT8: the value of the MSR\r
//\r
typedef union {\r
  SERIAL_PORT_MSR_BITS  Bits;\r
  UINT8                 Data;\r
} SERIAL_PORT_MSR;\r
\r
#pragma pack()\r
//\r
// Define serial register I/O macros\r
//\r
#define READ_RBR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_RBR)\r
#define READ_DLL(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLL)\r
#define READ_DLM(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLM)\r
#define READ_IER(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_IER)\r
#define READ_IIR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_IIR)\r
#define READ_LCR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_LCR)\r
#define READ_MCR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_MCR)\r
#define READ_LSR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_LSR)\r
#define READ_MSR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_MSR)\r
#define READ_SCR(IO, B)     IsaSerialReadPort (IO, B, SERIAL_REGISTER_SCR)\r
\r
#define WRITE_THR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_THR, D)\r
#define WRITE_DLL(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLL, D)\r
#define WRITE_DLM(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLM, D)\r
#define WRITE_IER(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_IER, D)\r
#define WRITE_FCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_FCR, D)\r
#define WRITE_LCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LCR, D)\r
#define WRITE_MCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MCR, D)\r
#define WRITE_LSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LSR, D)\r
#define WRITE_MSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MSR, D)\r
#define WRITE_SCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_SCR, D)\r
\r
//\r
// Prototypes\r
// Driver model protocol interface\r
//\r
\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverSupported (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverStart (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverStop (\r
  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,\r
  IN  EFI_HANDLE                    Controller,\r
  IN  UINTN                         NumberOfChildren,\r
  IN  EFI_HANDLE                    *ChildHandleBuffer\r
  );\r
\r
//\r
// Serial I/O Protocol Interface\r
//\r
EFI_STATUS\r
EFIAPI\r
IsaSerialReset (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialSetAttributes (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN UINT64                         BaudRate,\r
  IN UINT32                         ReceiveFifoDepth,\r
  IN UINT32                         Timeout,\r
  IN EFI_PARITY_TYPE                Parity,\r
  IN UINT8                          DataBits,\r
  IN EFI_STOP_BITS_TYPE             StopBits\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialSetControl (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN UINT32                         Control\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialGetControl (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  OUT UINT32                        *Control\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialWrite (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN OUT UINTN                      *BufferSize,\r
  IN VOID                           *Buffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
IsaSerialRead (\r
  IN EFI_SERIAL_IO_PROTOCOL         *This,\r
  IN OUT UINTN                      *BufferSize,\r
  OUT VOID                          *Buffer\r
  );\r
\r
//\r
// Internal Functions\r
//\r
BOOLEAN\r
IsaSerialPortPresent (\r
  IN SERIAL_DEV                     *SerialDevice\r
  );\r
\r
BOOLEAN\r
IsaSerialFifoFull (\r
  IN SERIAL_DEV_FIFO                *Fifo\r
  );\r
\r
BOOLEAN\r
IsaSerialFifoEmpty (\r
  IN SERIAL_DEV_FIFO                *Fifo\r
  );\r
\r
EFI_STATUS\r
IsaSerialFifoAdd (\r
  IN SERIAL_DEV_FIFO                *Fifo,\r
  IN UINT8                          Data\r
  );\r
\r
EFI_STATUS\r
IsaSerialFifoRemove (\r
  IN  SERIAL_DEV_FIFO               *Fifo,\r
  OUT UINT8                         *Data\r
  );\r
\r
EFI_STATUS\r
IsaSerialReceiveTransmit (\r
  IN SERIAL_DEV                     *SerialDevice\r
  );\r
\r
UINT8\r
IsaSerialReadPort (\r
  IN EFI_ISA_IO_PROTOCOL                    *IsaIo,\r
  IN UINT16                                 BaseAddress,\r
  IN UINT32                                 Offset\r
  );\r
\r
VOID\r
IsaSerialWritePort (\r
  IN EFI_ISA_IO_PROTOCOL                    *IsaIo,\r
  IN UINT16                                 BaseAddress,\r
  IN UINT32                                 Offset,\r
  IN UINT8                                  Data\r
  );\r
\r
#endif\r
Commit	Line	Data
f8cd287b	1	/**@file\r
637ff819	2	Include for Serial Driver\r
f8cd287b	3	\r
	4	Copyright (c) 2006 - 2007, Intel Corporation.<BR>\r
	5	All rights reserved. This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
637ff819	9	\r
f8cd287b	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
f8cd287b	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
637ff819	12	\r
f8cd287b	13	**/\r
637ff819	14	\r
	15	#ifndef _SERIAL_H\r
	16	#define _SERIAL_H\r
	17	\r
ed7748fe	18	\r
637ff819	19	#include <PiDxe.h>\r
637ff819	20	#include <FrameworkPei.h>\r
ed7748fe	21	\r
637ff819	22	#include <Protocol/IsaIo.h>\r
	23	#include <Protocol/SerialIo.h>\r
	24	#include <Protocol/DevicePath.h>\r
ed7748fe	25	\r
637ff819	26	#include <Library/DebugLib.h>\r
	27	#include <Library/UefiDriverEntryPoint.h>\r
	28	#include <Library/BaseLib.h>\r
	29	#include <Library/UefiLib.h>\r
	30	#include <Library/DevicePathLib.h>\r
	31	#include <Library/BaseMemoryLib.h>\r
	32	#include <Library/MemoryAllocationLib.h>\r
	33	#include <Library/UefiBootServicesTableLib.h>\r
	34	#include <Library/ReportStatusCodeLib.h>\r
	35	#include <Library/PcdLib.h>\r
	36	//\r
	37	// Driver Binding Externs\r
	38	//\r
f3d08ccf	39	extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r
	40	extern EFI_COMPONENT_NAME_PROTOCOL gIsaSerialComponentName;\r
	41	extern EFI_COMPONENT_NAME2_PROTOCOL gIsaSerialComponentName2;\r
637ff819	42	\r
	43	//\r
	44	// Internal Data Structures\r
	45	//\r
f02bd376	46	#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')\r
637ff819	47	#define SERIAL_MAX_BUFFER_SIZE 16\r
	48	#define TIMEOUT_STALL_INTERVAL 10\r
	49	\r
	50	//\r
	51	// Name: SERIAL_DEV_FIFO\r
	52	// Purpose: To define Receive FIFO and Transmit FIFO\r
	53	// Context: Used by serial data transmit and receive\r
	54	// Fields:\r
	55	// First UINT32: The index of the first data in array Data[]\r
	56	// Last UINT32: The index, which you can put a new data into array Data[]\r
	57	// Surplus UINT32: Identify how many data you can put into array Data[]\r
	58	// Data[] UINT8 : An array, which used to store data\r
	59	//\r
	60	typedef struct {\r
	61	UINT32 First;\r
	62	UINT32 Last;\r
	63	UINT32 Surplus;\r
	64	UINT8 Data[SERIAL_MAX_BUFFER_SIZE];\r
	65	} SERIAL_DEV_FIFO;\r
	66	\r
	67	typedef enum {\r
	68	UART8250 = 0,\r
	69	UART16450 = 1,\r
	70	UART16550 = 2,\r
	71	UART16550A= 3\r
	72	} EFI_UART_TYPE;\r
	73	\r
	74	//\r
	75	// Name: SERIAL_DEV\r
	76	// Purpose: To provide device specific information\r
	77	// Context:\r
	78	// Fields:\r
	79	// Signature UINTN: The identity of the serial device\r
	80	// SerialIo SERIAL_IO_PROTOCOL: Serial I/O protocol interface\r
	81	// SerialMode SERIAL_IO_MODE:\r
	82	// DevicePath EFI_DEVICE_PATH_PROTOCOL *: Device path of the serial device\r
	83	// Handle EFI_HANDLE: The handle instance attached to serial device\r
	84	// BaseAddress UINT16: The base address of specific serial device\r
	85	// Receive SERIAL_DEV_FIFO: The FIFO used to store data,\r
	86	// which is received by UART\r
	87	// Transmit SERIAL_DEV_FIFO: The FIFO used to store data,\r
	88	// which you want to transmit by UART\r
	89	// SoftwareLoopbackEnable BOOLEAN:\r
	90	// Type EFI_UART_TYPE: Specify the UART type of certain serial device\r
	91	//\r
	92	typedef struct {\r
	93	UINTN Signature;\r
	94	\r
	95	EFI_HANDLE Handle;\r
	96	EFI_SERIAL_IO_PROTOCOL SerialIo;\r
	97	EFI_SERIAL_IO_MODE SerialMode;\r
	98	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	99	\r
	100	EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r
	101	UART_DEVICE_PATH UartDevicePath;\r
	102	EFI_ISA_IO_PROTOCOL *IsaIo;\r
	103	\r
	104	UINT16 BaseAddress;\r
	105	SERIAL_DEV_FIFO Receive;\r
	106	SERIAL_DEV_FIFO Transmit;\r
	107	BOOLEAN SoftwareLoopbackEnable;\r
	108	BOOLEAN HardwareFlowControl;\r
	109	EFI_UART_TYPE Type;\r
	110	EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
111	} SERIAL_DEV;\r
112	\r
113	#include "ComponentName.h"\r
114	\r
115	#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)\r
116	\r
117	//\r
118	// Globale Variables\r
119	//\r
f3d08ccf	120	extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r
637ff819	121	\r
	122	//\r
	123	// Serial Driver Defaults\r
	124	//\r
637ff819	125	#define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH 1\r
637ff819	126	#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000\r
6b88ceec A	127	\r
	128	/*\r
	129	#define SERIAL_PORT_DEFAULT_BAUD_RATE 115200\r
637ff819	130	#define SERIAL_PORT_DEFAULT_PARITY NoParity\r
	131	#define SERIAL_PORT_DEFAULT_DATA_BITS 8\r
	132	#define SERIAL_PORT_DEFAULT_STOP_BITS 1\r
6b88ceec	133	*/\r
637ff819	134	#define SERIAL_PORT_DEFAULT_CONTROL_MASK 0\r
637ff819	135	\r
6b88ceec	136	\r
637ff819	137	//\r
	138	// (24000000/13)MHz input clock\r
	139	//\r
	140	#define SERIAL_PORT_INPUT_CLOCK 1843200\r
	141	\r
	142	//\r
	143	// 115200 baud with rounding errors\r
	144	//\r
	145	#define SERIAL_PORT_MAX_BAUD_RATE 115400\r
	146	#define SERIAL_PORT_MIN_BAUD_RATE 50\r
	147	\r
	148	#define SERIAL_PORT_MAX_RECEIVE_FIFO_DEPTH 16\r
	149	#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS\r
	150	#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds\r
	151	//\r
	152	// UART Registers\r
	153	//\r
	154	#define SERIAL_REGISTER_THR 0 // WO Transmit Holding Register\r
	155	#define SERIAL_REGISTER_RBR 0 // RO Receive Buffer Register\r
	156	#define SERIAL_REGISTER_DLL 0 // R/W Divisor Latch LSB\r
	157	#define SERIAL_REGISTER_DLM 1 // R/W Divisor Latch MSB\r
	158	#define SERIAL_REGISTER_IER 1 // R/W Interrupt Enable Register\r
	159	#define SERIAL_REGISTER_IIR 2 // RO Interrupt Identification Register\r
	160	#define SERIAL_REGISTER_FCR 2 // WO FIFO Cotrol Register\r
	161	#define SERIAL_REGISTER_LCR 3 // R/W Line Control Register\r
	162	#define SERIAL_REGISTER_MCR 4 // R/W Modem Control Register\r
	163	#define SERIAL_REGISTER_LSR 5 // R/W Line Status Register\r
	164	#define SERIAL_REGISTER_MSR 6 // R/W Modem Status Register\r
	165	#define SERIAL_REGISTER_SCR 7 // R/W Scratch Pad Register\r
	166	#pragma pack(1)\r
	167	//\r
	168	// Name: SERIAL_PORT_IER_BITS\r
	169	// Purpose: Define each bit in Interrupt Enable Register\r
	170	// Context:\r
	171	// Fields:\r
	172	// RAVIE Bit0: Receiver Data Available Interrupt Enable\r
	173	// THEIE Bit1: Transmistter Holding Register Empty Interrupt Enable\r
	174	// RIE Bit2: Receiver Interrupt Enable\r
	175	// MIE Bit3: Modem Interrupt Enable\r
	176	// Reserved Bit4-Bit7: Reserved\r
	177	//\r
	178	typedef struct {\r
	179	UINT8 RAVIE : 1;\r
	180	UINT8 THEIE : 1;\r
	181	UINT8 RIE : 1;\r
	182	UINT8 MIE : 1;\r
	183	UINT8 Reserved : 4;\r
	184	} SERIAL_PORT_IER_BITS;\r
	185	\r
	186	//\r
	187	// Name: SERIAL_PORT_IER\r
	188	// Purpose:\r
	189	// Context:\r
	190	// Fields:\r
	191	// Bits SERIAL_PORT_IER_BITS: Bits of the IER\r
	192	// Data UINT8: the value of the IER\r
	193	//\r
	194	typedef union {\r
	195	SERIAL_PORT_IER_BITS Bits;\r
	196	UINT8 Data;\r
	197	} SERIAL_PORT_IER;\r
	198	\r
	199	//\r
	200	// Name: SERIAL_PORT_IIR_BITS\r
201	// Purpose: Define each bit in Interrupt Identification Register\r
202	// Context:\r
203	// Fields:\r
204	// IPS Bit0: Interrupt Pending Status\r
205	// IIB Bit1-Bit3: Interrupt ID Bits\r
206	// Reserved Bit4-Bit5: Reserved\r
207	// FIFOES Bit6-Bit7: FIFO Mode Enable Status\r
208	//\r
209	typedef struct {\r
210	UINT8 IPS : 1;\r
211	UINT8 IIB : 3;\r
212	UINT8 Reserved : 2;\r
213	UINT8 FIFOES : 2;\r
214	} SERIAL_PORT_IIR_BITS;\r
215	\r
216	//\r
217	// Name: SERIAL_PORT_IIR\r
218	// Purpose:\r
219	// Context:\r
220	// Fields:\r
221	// Bits SERIAL_PORT_IIR_BITS: Bits of the IIR\r
222	// Data UINT8: the value of the IIR\r
223	//\r
224	typedef union {\r
225	SERIAL_PORT_IIR_BITS Bits;\r
226	UINT8 Data;\r
227	} SERIAL_PORT_IIR;\r
228	\r
229	//\r
230	// Name: SERIAL_PORT_FCR_BITS\r
231	// Purpose: Define each bit in FIFO Control Register\r
232	// Context:\r
233	// Fields:\r
234	// TRFIFOE Bit0: Transmit and Receive FIFO Enable\r
235	// RESETRF Bit1: Reset Reciever FIFO\r
236	// RESETTF Bit2: Reset Transmistter FIFO\r
237	// DMS Bit3: DMA Mode Select\r
238	// Reserved Bit4-Bit5: Reserved\r
239	// RTB Bit6-Bit7: Receive Trigger Bits\r
240	//\r
241	typedef struct {\r
242	UINT8 TRFIFOE : 1;\r
243	UINT8 RESETRF : 1;\r
244	UINT8 RESETTF : 1;\r
245	UINT8 DMS : 1;\r
246	UINT8 Reserved : 2;\r
247	UINT8 RTB : 2;\r
248	} SERIAL_PORT_FCR_BITS;\r
249	\r
250	//\r
251	// Name: SERIAL_PORT_FCR\r
252	// Purpose:\r
253	// Context:\r
254	// Fields:\r
255	// Bits SERIAL_PORT_FCR_BITS: Bits of the FCR\r
256	// Data UINT8: the value of the FCR\r
257	//\r
258	typedef union {\r
259	SERIAL_PORT_FCR_BITS Bits;\r
260	UINT8 Data;\r
261	} SERIAL_PORT_FCR;\r
262	\r
263	//\r
264	// Name: SERIAL_PORT_LCR_BITS\r
265	// Purpose: Define each bit in Line Control Register\r
266	// Context:\r
267	// Fields:\r
268	// SERIALDB Bit0-Bit1: Number of Serial Data Bits\r
269	// STOPB Bit2: Number of Stop Bits\r
270	// PAREN Bit3: Parity Enable\r
271	// EVENPAR Bit4: Even Parity Select\r
272	// STICPAR Bit5: Sticky Parity\r
273	// BRCON Bit6: Break Control\r
274	// DLAB Bit7: Divisor Latch Access Bit\r
275	//\r
276	typedef struct {\r
277	UINT8 SERIALDB : 2;\r
278	UINT8 STOPB : 1;\r
279	UINT8 PAREN : 1;\r
280	UINT8 EVENPAR : 1;\r
281	UINT8 STICPAR : 1;\r
282	UINT8 BRCON : 1;\r
283	UINT8 DLAB : 1;\r
284	} SERIAL_PORT_LCR_BITS;\r
285	\r
286	//\r
287	// Name: SERIAL_PORT_LCR\r
288	// Purpose:\r
289	// Context:\r
290	// Fields:\r
291	// Bits SERIAL_PORT_LCR_BITS: Bits of the LCR\r
292	// Data UINT8: the value of the LCR\r
293	//\r
294	typedef union {\r
295	SERIAL_PORT_LCR_BITS Bits;\r
296	UINT8 Data;\r
297	} SERIAL_PORT_LCR;\r
298	\r
299	//\r
300	// Name: SERIAL_PORT_MCR_BITS\r
301	// Purpose: Define each bit in Modem Control Register\r
302	// Context:\r
303	// Fields:\r
304	// DTRC Bit0: Data Terminal Ready Control\r
305	// RTS Bit1: Request To Send Control\r
306	// OUT1 Bit2: Output1\r
307	// OUT2 Bit3: Output2, used to disable interrupt\r
308	// LME; Bit4: Loopback Mode Enable\r
309	// Reserved Bit5-Bit7: Reserved\r
310	//\r
311	typedef struct {\r
312	UINT8 DTRC : 1;\r
313	UINT8 RTS : 1;\r
314	UINT8 OUT1 : 1;\r
315	UINT8 OUT2 : 1;\r
316	UINT8 LME : 1;\r
317	UINT8 Reserved : 3;\r
318	} SERIAL_PORT_MCR_BITS;\r
319	\r
320	//\r
321	// Name: SERIAL_PORT_MCR\r
322	// Purpose:\r
323	// Context:\r
324	// Fields:\r
325	// Bits SERIAL_PORT_MCR_BITS: Bits of the MCR\r
326	// Data UINT8: the value of the MCR\r
327	//\r
328	typedef union {\r
329	SERIAL_PORT_MCR_BITS Bits;\r
330	UINT8 Data;\r
331	} SERIAL_PORT_MCR;\r
332	\r
333	//\r
334	// Name: SERIAL_PORT_LSR_BITS\r
335	// Purpose: Define each bit in Line Status Register\r
336	// Context:\r
337	// Fields:\r
338	// DR Bit0: Receiver Data Ready Status\r
339	// OE Bit1: Overrun Error Status\r
340	// PE Bit2: Parity Error Status\r
341	// FE Bit3: Framing Error Status\r
342	// BI Bit4: Break Interrupt Status\r
343	// THRE Bit5: Transmistter Holding Register Status\r
344	// TEMT Bit6: Transmitter Empty Status\r
345	// FIFOE Bit7: FIFO Error Status\r
346	//\r
347	typedef struct {\r
348	UINT8 DR : 1;\r
349	UINT8 OE : 1;\r
350	UINT8 PE : 1;\r
351	UINT8 FE : 1;\r
352	UINT8 BI : 1;\r
353	UINT8 THRE : 1;\r
354	UINT8 TEMT : 1;\r
355	UINT8 FIFOE : 1;\r
356	} SERIAL_PORT_LSR_BITS;\r
357	\r
358	//\r
359	// Name: SERIAL_PORT_LSR\r
360	// Purpose:\r
361	// Context:\r
362	// Fields:\r
363	// Bits SERIAL_PORT_LSR_BITS: Bits of the LSR\r
364	// Data UINT8: the value of the LSR\r
365	//\r
366	typedef union {\r
367	SERIAL_PORT_LSR_BITS Bits;\r
368	UINT8 Data;\r
369	} SERIAL_PORT_LSR;\r
370	\r
371	//\r
372	// Name: SERIAL_PORT_MSR_BITS\r
373	// Purpose: Define each bit in Modem Status Register\r
374	// Context:\r
375	// Fields:\r
376	// DeltaCTS Bit0: Delta Clear To Send Status\r
377	// DeltaDSR Bit1: Delta Data Set Ready Status\r
378	// TrailingEdgeRI Bit2: Trailing Edge of Ring Indicator Status\r
379	// DeltaDCD Bit3: Delta Data Carrier Detect Status\r
380	// CTS Bit4: Clear To Send Status\r
381	// DSR Bit5: Data Set Ready Status\r
382	// RI Bit6: Ring Indicator Status\r
383	// DCD Bit7: Data Carrier Detect Status\r
384	//\r
385	typedef struct {\r
386	UINT8 DeltaCTS : 1;\r
387	UINT8 DeltaDSR : 1;\r
388	UINT8 TrailingEdgeRI : 1;\r
389	UINT8 DeltaDCD : 1;\r
390	UINT8 CTS : 1;\r
391	UINT8 DSR : 1;\r
392	UINT8 RI : 1;\r
393	UINT8 DCD : 1;\r
394	} SERIAL_PORT_MSR_BITS;\r
395	\r
396	//\r
397	// Name: SERIAL_PORT_MSR\r
398	// Purpose:\r
399	// Context:\r
400	// Fields:\r
401	// Bits SERIAL_PORT_MSR_BITS: Bits of the MSR\r
402	// Data UINT8: the value of the MSR\r
403	//\r
404	typedef union {\r
405	SERIAL_PORT_MSR_BITS Bits;\r
406	UINT8 Data;\r
407	} SERIAL_PORT_MSR;\r
408	\r
409	#pragma pack()\r
410	//\r
411	// Define serial register I/O macros\r
412	//\r
413	#define READ_RBR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_RBR)\r
414	#define READ_DLL(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLL)\r
415	#define READ_DLM(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLM)\r
416	#define READ_IER(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IER)\r
417	#define READ_IIR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IIR)\r
418	#define READ_LCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LCR)\r
419	#define READ_MCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MCR)\r
420	#define READ_LSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LSR)\r
421	#define READ_MSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MSR)\r
422	#define READ_SCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_SCR)\r
423	\r
424	#define WRITE_THR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_THR, D)\r
425	#define WRITE_DLL(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLL, D)\r
426	#define WRITE_DLM(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLM, D)\r
427	#define WRITE_IER(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_IER, D)\r
428	#define WRITE_FCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_FCR, D)\r
429	#define WRITE_LCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LCR, D)\r
430	#define WRITE_MCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MCR, D)\r
431	#define WRITE_LSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LSR, D)\r
432	#define WRITE_MSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MSR, D)\r
433	#define WRITE_SCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_SCR, D)\r
434	\r
435	//\r
436	// Prototypes\r
437	// Driver model protocol interface\r
438	//\r
439	\r
440	EFI_STATUS\r
441	EFIAPI\r
442	SerialControllerDriverSupported (\r
443	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
444	IN EFI_HANDLE Controller,\r
445	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
446	);\r
447	\r
448	EFI_STATUS\r
449	EFIAPI\r
450	SerialControllerDriverStart (\r
451	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
452	IN EFI_HANDLE Controller,\r
453	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
454	);\r
455	\r
456	EFI_STATUS\r
457	EFIAPI\r
458	SerialControllerDriverStop (\r
459	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
460	IN EFI_HANDLE Controller,\r
461	IN UINTN NumberOfChildren,\r
462	IN EFI_HANDLE *ChildHandleBuffer\r
463	);\r
464	\r
465	//\r
466	// Serial I/O Protocol Interface\r
467	//\r
468	EFI_STATUS\r
469	EFIAPI\r
470	IsaSerialReset (\r
471	IN EFI_SERIAL_IO_PROTOCOL *This\r
472	);\r
473	\r
474	EFI_STATUS\r
475	EFIAPI\r
476	IsaSerialSetAttributes (\r
477	IN EFI_SERIAL_IO_PROTOCOL *This,\r
478	IN UINT64 BaudRate,\r
479	IN UINT32 ReceiveFifoDepth,\r
480	IN UINT32 Timeout,\r
481	IN EFI_PARITY_TYPE Parity,\r
482	IN UINT8 DataBits,\r
483	IN EFI_STOP_BITS_TYPE StopBits\r
484	);\r
485	\r
486	EFI_STATUS\r
487	EFIAPI\r
488	IsaSerialSetControl (\r
489	IN EFI_SERIAL_IO_PROTOCOL *This,\r
490	IN UINT32 Control\r
491	);\r
492	\r
493	EFI_STATUS\r
494	EFIAPI\r
495	IsaSerialGetControl (\r
496	IN EFI_SERIAL_IO_PROTOCOL *This,\r
497	OUT UINT32 *Control\r
498	);\r
499	\r
500	EFI_STATUS\r
501	EFIAPI\r
502	IsaSerialWrite (\r
503	IN EFI_SERIAL_IO_PROTOCOL *This,\r
504	IN OUT UINTN *BufferSize,\r
505	IN VOID *Buffer\r
506	);\r
507	\r
508	EFI_STATUS\r
509	EFIAPI\r
510	IsaSerialRead (\r
511	IN EFI_SERIAL_IO_PROTOCOL *This,\r
512	IN OUT UINTN *BufferSize,\r
513	OUT VOID *Buffer\r
514	);\r
515	\r
516	//\r
517	// Internal Functions\r
518	//\r
519	BOOLEAN\r
520	IsaSerialPortPresent (\r
521	IN SERIAL_DEV *SerialDevice\r
522	);\r
523	\r
524	BOOLEAN\r
525	IsaSerialFifoFull (\r
526	IN SERIAL_DEV_FIFO *Fifo\r
527	);\r
528	\r
529	BOOLEAN\r
530	IsaSerialFifoEmpty (\r
531	IN SERIAL_DEV_FIFO *Fifo\r
532	);\r
533	\r
534	EFI_STATUS\r
535	IsaSerialFifoAdd (\r
536	IN SERIAL_DEV_FIFO *Fifo,\r
537	IN UINT8 Data\r
538	);\r
539	\r
540	EFI_STATUS\r
541	IsaSerialFifoRemove (\r
542	IN SERIAL_DEV_FIFO *Fifo,\r
543	OUT UINT8 *Data\r
544	);\r
545	\r
546	EFI_STATUS\r
547	IsaSerialReceiveTransmit (\r
548	IN SERIAL_DEV *SerialDevice\r
549	);\r
550	\r
551	UINT8\r
552	IsaSerialReadPort (\r
553	IN EFI_ISA_IO_PROTOCOL *IsaIo,\r
554	IN UINT16 BaseAddress,\r
555	IN UINT32 Offset\r
556	);\r
557	\r
558	VOID\r
559	IsaSerialWritePort (\r
560	IN EFI_ISA_IO_PROTOCOL *IsaIo,\r
561	IN UINT16 BaseAddress,\r
562	IN UINT32 Offset,\r
563	IN UINT8 Data\r
564	);\r
565	\r
566	#endif\r