[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciBus.h

/** @file\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#ifndef _EFI_PCI_BUS_H_\r
#define _EFI_PCI_BUS_H_\r
\r
\r
#include <FrameworkDxe.h>\r
\r
\r
#include <Protocol/LoadedImage.h>\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciIo.h>\r
#include <Protocol/LoadFile2.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/PciHotPlugRequest.h>\r
#include <Protocol/DevicePath.h>\r
#include <Protocol/PciPlatform.h>\r
#include <Protocol/PciHotPlugInit.h>\r
#include <Protocol/Decompress.h>\r
#include <Protocol/BusSpecificDriverOverride.h>\r
#include <Protocol/UgaIo.h>\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciIncompatibleDeviceSupportLib.h>\r
#include <Library/PeCoffLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/PeImage.h>\r
#include <IndustryStandard/Acpi.h>\r
#include "ComponentName.h"\r
\r
\r
//\r
// Global Variables\r
//\r
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;\r
extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;\r
\r
//\r
// Driver Produced Protocol Prototypes\r
//\r
\r
#define VGABASE1  0x3B0\r
#define VGALIMIT1 0x3BB\r
\r
#define VGABASE2  0x3C0\r
#define VGALIMIT2 0x3DF\r
\r
#define ISABASE   0x100\r
#define ISALIMIT  0x3FF\r
\r
typedef enum {\r
  PciBarTypeUnknown = 0,\r
  PciBarTypeIo16,\r
  PciBarTypeIo32,\r
  PciBarTypeMem32,\r
  PciBarTypePMem32,\r
  PciBarTypeMem64,\r
  PciBarTypePMem64,\r
  PciBarTypeIo,\r
  PciBarTypeMem,\r
  PciBarTypeMaxType\r
} PCI_BAR_TYPE;\r
\r
typedef struct {\r
  UINT64        BaseAddress;\r
  UINT64        Length;\r
  UINT64        Alignment;\r
  PCI_BAR_TYPE  BarType;\r
  BOOLEAN       Prefetchable;\r
  UINT8         MemType;\r
  UINT8         Offset;\r
} PCI_BAR;\r
\r
#define PPB_BAR_0                             0\r
#define PPB_BAR_1                             1\r
#define PPB_IO_RANGE                          2\r
#define PPB_MEM32_RANGE                       3\r
#define PPB_PMEM32_RANGE                      4\r
#define PPB_PMEM64_RANGE                      5\r
#define PPB_MEM64_RANGE                       0xFF\r
\r
#define P2C_BAR_0                             0\r
#define P2C_MEM_1                             1\r
#define P2C_MEM_2                             2\r
#define P2C_IO_1                              3\r
#define P2C_IO_2                              4\r
\r
#define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')\r
\r
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001\r
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002\r
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004\r
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008\r
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020\r
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040\r
\r
#define PCI_MAX_HOST_BRIDGE_NUM               0x0010\r
\r
//\r
// Define option for attribute\r
//\r
#define EFI_SET_SUPPORTS    0\r
#define EFI_SET_ATTRIBUTES  1\r
\r
typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;\r
\r
struct _PCI_IO_DEVICE {\r
  UINT32                                    Signature;\r
  EFI_HANDLE                                Handle;\r
  EFI_PCI_IO_PROTOCOL                       PciIo;\r
  LIST_ENTRY                                Link;\r
\r
  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;\r
  EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;\r
\r
  //\r
  // PCI configuration space header type\r
  //\r
  PCI_TYPE00                                Pci;\r
\r
  //\r
  // Bus number, Device number, Function number\r
  //\r
  UINT8                                     BusNumber;\r
  UINT8                                     DeviceNumber;\r
  UINT8                                     FunctionNumber;\r
\r
  //\r
  // BAR for this PCI Device\r
  //\r
  PCI_BAR                                   PciBar[PCI_MAX_BAR];\r
\r
  //\r
  // The bridge device this pci device is subject to\r
  //\r
  PCI_IO_DEVICE                             *Parent;\r
\r
  //\r
  // A linked list for children Pci Device if it is bridge device\r
  //\r
  LIST_ENTRY                                ChildList;\r
\r
  //\r
  // TURE if the PCI bus driver creates the handle for this PCI device\r
  //\r
  BOOLEAN                                   Registered;\r
\r
  //\r
  // TRUE if the PCI bus driver successfully allocates the resource required by\r
  // this PCI device\r
  //\r
  BOOLEAN                                   Allocated;\r
\r
  //\r
  // The attribute this PCI device currently set\r
  //\r
  UINT64                                    Attributes;\r
\r
  //\r
  // The attributes this PCI device actually supports\r
  //\r
  UINT64                                    Supports;\r
\r
  //\r
  // The resource decode the bridge supports\r
  //\r
  UINT32                                    Decodes;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomSize;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomBase;\r
\r
  //\r
  // TRUE if all OpROM (in device or in platform specific position) have been processed\r
  //\r
  BOOLEAN                                   AllOpRomProcessed;\r
\r
  //\r
  // TRUE if there is any EFI driver in the OptionRom\r
  //\r
  BOOLEAN                                   BusOverride;\r
\r
  //\r
  //  A list tracking reserved resource on a bridge device\r
  //\r
  LIST_ENTRY                                ReservedResourceList;\r
\r
  //\r
  // A list tracking image handle of platform specific overriding driver\r
  //\r
  LIST_ENTRY                                OptionRomDriverList;\r
\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;\r
  EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;\r
\r
  BOOLEAN                                   IsPciExp;\r
\r
};\r
\r
\r
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LINK(a) \\r
  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
\r
//\r
// Global Variables\r
//\r
extern LIST_ENTRY                                   gPciDevicePool;\r
extern BOOLEAN                                      gFullEnumeration;\r
extern UINTN                                        gPciHostBridgeNumber;\r
extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
extern UINT64                                       gAllOne;\r
extern UINT64                                       gAllZero;\r
\r
extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;\r
\r
#include "PciIo.h"\r
#include "PciCommand.h"\r
#include "PciDeviceSupport.h"\r
#include "PciEnumerator.h"\r
#include "PciEnumeratorSupport.h"\r
#include "PciDriverOverride.h"\r
#include "PciRomTable.h"\r
#include "PciOptionRomSupport.h"\r
#include "PciPowerManagement.h"\r
#include "PciHotPlugSupport.h"\r
#include "PciLib.h"\r
\r
//\r
// PCI Bus Support Function Prototypes\r
//\r
/**\r
  Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
  than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
\r
  @param  This                Protocol instance pointer.\r
  @param  ControllerHandle    Handle of device to test.\r
  @param  RemainingDevicePath Optional parameter use to pick a specific child.\r
                              device to start.\r
\r
  @retval EFI_SUCCESS         This driver supports this device.\r
  @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
  @retval other               This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingSupported (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Start this driver on ControllerHandle and enumerate Pci bus and start\r
  all device under PCI bus.\r
\r
  @param  This                 Protocol instance pointer.\r
  @param  ControllerHandle     Handle of device to bind driver to.\r
  @param  RemainingDevicePath  Optional parameter use to pick a specific child.\r
                               device to start.\r
\r
  @retval EFI_SUCCESS          This driver is added to ControllerHandle.\r
  @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.\r
  @retval other                This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStart (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Stop this driver on ControllerHandle. Support stoping any child handles\r
  created by this driver.\r
\r
  @param  This              Protocol instance pointer.\r
  @param  ControllerHandle  Handle of device to stop driver on.\r
  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
                            children is zero stop the entire bus driver.\r
  @param  ChildHandleBuffer List of Child Handles to Stop.\r
\r
  @retval EFI_SUCCESS       This driver is removed ControllerHandle.\r
  @retval other             This driver was not removed from this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStop (\r
  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,\r
  IN  EFI_HANDLE                    Controller,\r
  IN  UINTN                         NumberOfChildren,\r
  IN  EFI_HANDLE                    *ChildHandleBuffer\r
  );\r
\r
#define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
\r
#endif\r
Commit	Line	Data
eeefcb9d	1	/** @file\r
ead42efc	2	\r
c72216a6	3	Copyright (c) 2006 - 2009, Intel Corporation\r
ea5632e5	4	All rights reserved. This program and the accompanying materials\r
	5	are licensed and made available under the terms and conditions of the BSD License\r
	6	which accompanies this distribution. The full text of the license may be found at\r
	7	http://opensource.org/licenses/bsd-license.php\r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
ead42efc	11	\r
3db51098	12	**/\r
ead42efc	13	\r
ead42efc	14	\r
eeefcb9d	15	#ifndef _EFI_PCI_BUS_H_\r
eeefcb9d	16	#define _EFI_PCI_BUS_H_\r
ead42efc	17	\r
ed7748fe	18	\r
694b922c	19	#include <FrameworkDxe.h>\r
694b922c	20	\r
ed7748fe	21	\r
ead42efc	22	#include <Protocol/LoadedImage.h>\r
	23	#include <Protocol/PciHostBridgeResourceAllocation.h>\r
	24	#include <Protocol/PciIo.h>\r
8e6b0dcb	25	#include <Protocol/LoadFile2.h>\r
ead42efc	26	#include <Protocol/PciRootBridgeIo.h>\r
	27	#include <Protocol/PciHotPlugRequest.h>\r
	28	#include <Protocol/DevicePath.h>\r
	29	#include <Protocol/PciPlatform.h>\r
	30	#include <Protocol/PciHotPlugInit.h>\r
	31	#include <Protocol/Decompress.h>\r
ead42efc	32	#include <Protocol/BusSpecificDriverOverride.h>\r
ead42efc	33	#include <Protocol/UgaIo.h>\r
ea5632e5	34	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
ed7748fe	35	\r
ead42efc	36	#include <Library/DebugLib.h>\r
	37	#include <Library/UefiDriverEntryPoint.h>\r
	38	#include <Library/BaseLib.h>\r
	39	#include <Library/UefiLib.h>\r
	40	#include <Library/BaseMemoryLib.h>\r
	41	#include <Library/ReportStatusCodeLib.h>\r
	42	#include <Library/MemoryAllocationLib.h>\r
	43	#include <Library/UefiBootServicesTableLib.h>\r
	44	#include <Library/DevicePathLib.h>\r
	45	#include <Library/PcdLib.h>\r
	46	#include <Library/PciIncompatibleDeviceSupportLib.h>\r
2fb718b0	47	#include <Library/PeCoffLib.h>\r
ead42efc	48	\r
bc14bdb3	49	#include <IndustryStandard/Pci.h>\r
b1ef4015	50	#include <IndustryStandard/PeImage.h>\r
ead42efc	51	#include <IndustryStandard/Acpi.h>\r
	52	#include "ComponentName.h"\r
	53	\r
9f6531d1	54	\r
	55	//\r
	56	// Global Variables\r
	57	//\r
	58	extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
	59	extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
	60	extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
	61	extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
	62	\r
ead42efc	63	//\r
	64	// Driver Produced Protocol Prototypes\r
	65	//\r
	66	\r
	67	#define VGABASE1 0x3B0\r
	68	#define VGALIMIT1 0x3BB\r
	69	\r
	70	#define VGABASE2 0x3C0\r
	71	#define VGALIMIT2 0x3DF\r
	72	\r
	73	#define ISABASE 0x100\r
	74	#define ISALIMIT 0x3FF\r
	75	\r
	76	typedef enum {\r
	77	PciBarTypeUnknown = 0,\r
	78	PciBarTypeIo16,\r
	79	PciBarTypeIo32,\r
	80	PciBarTypeMem32,\r
	81	PciBarTypePMem32,\r
	82	PciBarTypeMem64,\r
	83	PciBarTypePMem64,\r
	84	PciBarTypeIo,\r
	85	PciBarTypeMem,\r
	86	PciBarTypeMaxType\r
	87	} PCI_BAR_TYPE;\r
	88	\r
	89	typedef struct {\r
	90	UINT64 BaseAddress;\r
	91	UINT64 Length;\r
	92	UINT64 Alignment;\r
	93	PCI_BAR_TYPE BarType;\r
	94	BOOLEAN Prefetchable;\r
	95	UINT8 MemType;\r
	96	UINT8 Offset;\r
	97	} PCI_BAR;\r
	98	\r
	99	#define PPB_BAR_0 0\r
	100	#define PPB_BAR_1 1\r
	101	#define PPB_IO_RANGE 2\r
	102	#define PPB_MEM32_RANGE 3\r
	103	#define PPB_PMEM32_RANGE 4\r
	104	#define PPB_PMEM64_RANGE 5\r
	105	#define PPB_MEM64_RANGE 0xFF\r
	106	\r
	107	#define P2C_BAR_0 0\r
	108	#define P2C_MEM_1 1\r
	109	#define P2C_MEM_2 2\r
	110	#define P2C_IO_1 3\r
	111	#define P2C_IO_2 4\r
	112	\r
f02bd376	113	#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
ead42efc	114	\r
	115	#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
	116	#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
	117	#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
	118	#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
	119	#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
	120	#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
	121	#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
	122	\r
	123	#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
ead42efc	124	\r
	125	//\r
	126	// Define option for attribute\r
	127	//\r
	128	#define EFI_SET_SUPPORTS 0\r
	129	#define EFI_SET_ATTRIBUTES 1\r
	130	\r
c72216a6	131	typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
	132	\r
	133	struct _PCI_IO_DEVICE {\r
ead42efc	134	UINT32 Signature;\r
	135	EFI_HANDLE Handle;\r
	136	EFI_PCI_IO_PROTOCOL PciIo;\r
	137	LIST_ENTRY Link;\r
	138	\r
	139	EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
	140	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	141	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
8e6b0dcb	142	EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
ead42efc	143	\r
	144	//\r
	145	// PCI configuration space header type\r
	146	//\r
	147	PCI_TYPE00 Pci;\r
	148	\r
	149	//\r
	150	// Bus number, Device number, Function number\r
	151	//\r
	152	UINT8 BusNumber;\r
	153	UINT8 DeviceNumber;\r
	154	UINT8 FunctionNumber;\r
	155	\r
	156	//\r
	157	// BAR for this PCI Device\r
	158	//\r
	159	PCI_BAR PciBar[PCI_MAX_BAR];\r
	160	\r
	161	//\r
	162	// The bridge device this pci device is subject to\r
	163	//\r
c72216a6	164	PCI_IO_DEVICE *Parent;\r
ead42efc	165	\r
	166	//\r
	167	// A linked list for children Pci Device if it is bridge device\r
	168	//\r
	169	LIST_ENTRY ChildList;\r
	170	\r
	171	//\r
	172	// TURE if the PCI bus driver creates the handle for this PCI device\r
	173	//\r
	174	BOOLEAN Registered;\r
	175	\r
	176	//\r
	177	// TRUE if the PCI bus driver successfully allocates the resource required by\r
	178	// this PCI device\r
	179	//\r
	180	BOOLEAN Allocated;\r
	181	\r
	182	//\r
	183	// The attribute this PCI device currently set\r
	184	//\r
	185	UINT64 Attributes;\r
	186	\r
	187	//\r
	188	// The attributes this PCI device actually supports\r
	189	//\r
	190	UINT64 Supports;\r
	191	\r
	192	//\r
	193	// The resource decode the bridge supports\r
	194	//\r
	195	UINT32 Decodes;\r
	196	\r
	197	//\r
	198	// The OptionRom Size\r
	199	//\r
	200	UINT64 RomSize;\r
	201	\r
	202	//\r
	203	// The OptionRom Size\r
	204	//\r
	205	UINT64 RomBase;\r
	206	\r
	207	//\r
	208	// TRUE if all OpROM (in device or in platform specific position) have been processed\r
	209	//\r
	210	BOOLEAN AllOpRomProcessed;\r
	211	\r
	212	//\r
	213	// TRUE if there is any EFI driver in the OptionRom\r
	214	//\r
	215	BOOLEAN BusOverride;\r
	216	\r
	217	//\r
	218	// A list tracking reserved resource on a bridge device\r
	219	//\r
	220	LIST_ENTRY ReservedResourceList;\r
	221	\r
	222	//\r
	223	// A list tracking image handle of platform specific overriding driver\r
	224	//\r
	225	LIST_ENTRY OptionRomDriverList;\r
	226	\r
	227	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
	228	EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
229	\r
230	BOOLEAN IsPciExp;\r
231	\r
c72216a6	232	};\r
ead42efc	233	\r
	234	\r
	235	#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
	236	CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
	237	\r
	238	#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
	239	CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
	240	\r
	241	#define PCI_IO_DEVICE_FROM_LINK(a) \\r
	242	CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
	243	\r
8e6b0dcb	244	#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
	245	CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
	246	\r
ead42efc	247	//\r
	248	// Global Variables\r
	249	//\r
ead42efc	250	extern LIST_ENTRY gPciDevicePool;\r
	251	extern BOOLEAN gFullEnumeration;\r
	252	extern UINTN gPciHostBridgeNumber;\r
	253	extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
	254	extern UINT64 gAllOne;\r
	255	extern UINT64 gAllZero;\r
	256	\r
	257	extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
	258	\r
	259	#include "PciIo.h"\r
	260	#include "PciCommand.h"\r
	261	#include "PciDeviceSupport.h"\r
	262	#include "PciEnumerator.h"\r
	263	#include "PciEnumeratorSupport.h"\r
	264	#include "PciDriverOverride.h"\r
	265	#include "PciRomTable.h"\r
	266	#include "PciOptionRomSupport.h"\r
	267	#include "PciPowerManagement.h"\r
	268	#include "PciHotPlugSupport.h"\r
	269	#include "PciLib.h"\r
	270	\r
	271	//\r
	272	// PCI Bus Support Function Prototypes\r
	273	//\r
eeefcb9d	274	/**\r
	275	Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
	276	than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
	277	\r
	278	@param This Protocol instance pointer.\r
	279	@param ControllerHandle Handle of device to test.\r
	280	@param RemainingDevicePath Optional parameter use to pick a specific child.\r
	281	device to start.\r
	282	\r
	283	@retval EFI_SUCCESS This driver supports this device.\r
	284	@retval EFI_ALREADY_STARTED This driver is already running on this device.\r
	285	@retval other This driver does not support this device.\r
	286	\r
	287	**/\r
ead42efc	288	EFI_STATUS\r
	289	EFIAPI\r
	290	PciBusDriverBindingSupported (\r
	291	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	292	IN EFI_HANDLE Controller,\r
	293	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	294	);\r
	295	\r
eeefcb9d	296	/**\r
	297	Start this driver on ControllerHandle and enumerate Pci bus and start\r
	298	all device under PCI bus.\r
	299	\r
	300	@param This Protocol instance pointer.\r
	301	@param ControllerHandle Handle of device to bind driver to.\r
	302	@param RemainingDevicePath Optional parameter use to pick a specific child.\r
	303	device to start.\r
	304	\r
	305	@retval EFI_SUCCESS This driver is added to ControllerHandle.\r
	306	@retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r
	307	@retval other This driver does not support this device.\r
	308	\r
	309	**/\r
ead42efc	310	EFI_STATUS\r
	311	EFIAPI\r
	312	PciBusDriverBindingStart (\r
	313	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	314	IN EFI_HANDLE Controller,\r
	315	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	316	);\r
	317	\r
eeefcb9d	318	/**\r
	319	Stop this driver on ControllerHandle. Support stoping any child handles\r
	320	created by this driver.\r
	321	\r
	322	@param This Protocol instance pointer.\r
	323	@param ControllerHandle Handle of device to stop driver on.\r
	324	@param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r
	325	children is zero stop the entire bus driver.\r
	326	@param ChildHandleBuffer List of Child Handles to Stop.\r
	327	\r
	328	@retval EFI_SUCCESS This driver is removed ControllerHandle.\r
	329	@retval other This driver was not removed from this device.\r
	330	\r
	331	**/\r
ead42efc	332	EFI_STATUS\r
	333	EFIAPI\r
	334	PciBusDriverBindingStop (\r
	335	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	336	IN EFI_HANDLE Controller,\r
	337	IN UINTN NumberOfChildren,\r
	338	IN EFI_HANDLE *ChildHandleBuffer\r
	339	);\r
	340	\r
1833218d	341	#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
1833218d	342	\r
ead42efc	343	#endif\r