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1 | /**@file\r |
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2 | \r |
| 3 | Copyright (c) 2006, Intel Corporation \r |
| 4 | All rights reserved. This program and the accompanying materials \r |
| 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r |
| 7 | http://opensource.org/licenses/bsd-license.php \r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | \r |
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12 | **/\r |
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13 | \r |
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14 | \r |
| 15 | #ifndef _EFI_PCI_COMMAND_H\r |
| 16 | #define _EFI_PCI_COMMAND_H\r |
| 17 | \r |
| 18 | //\r |
| 19 | // The PCI Command register bits owned by PCI Bus driver.\r |
| 20 | //\r |
| 21 | // They should be cleared at the beginning. The other registers\r |
| 22 | // are owned by chipset, we should not touch them.\r |
| 23 | //\r |
| 24 | #define EFI_PCI_COMMAND_BITS_OWNED ( \\r |
| 25 | EFI_PCI_COMMAND_IO_SPACE | \\r |
| 26 | EFI_PCI_COMMAND_MEMORY_SPACE | \\r |
| 27 | EFI_PCI_COMMAND_BUS_MASTER | \\r |
| 28 | EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \\r |
| 29 | EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \\r |
| 30 | EFI_PCI_COMMAND_FAST_BACK_TO_BACK \\r |
| 31 | )\r |
| 32 | \r |
| 33 | //\r |
| 34 | // The PCI Bridge Control register bits owned by PCI Bus driver.\r |
| 35 | // \r |
| 36 | // They should be cleared at the beginning. The other registers\r |
| 37 | // are owned by chipset, we should not touch them.\r |
| 38 | //\r |
| 39 | #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \\r |
| 40 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r |
| 41 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r |
| 42 | EFI_PCI_BRIDGE_CONTROL_VGA_16 | \\r |
| 43 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r |
| 44 | )\r |
| 45 | \r |
| 46 | //\r |
| 47 | // The PCCard Bridge Control register bits owned by PCI Bus driver.\r |
| 48 | // \r |
| 49 | // They should be cleared at the beginning. The other registers\r |
| 50 | // are owned by chipset, we should not touch them.\r |
| 51 | //\r |
| 52 | #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \\r |
| 53 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r |
| 54 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r |
| 55 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r |
| 56 | )\r |
| 57 | \r |
| 58 | \r |
| 59 | #define EFI_GET_REGISTER 1\r |
| 60 | #define EFI_SET_REGISTER 2\r |
| 61 | #define EFI_ENABLE_REGISTER 3\r |
| 62 | #define EFI_DISABLE_REGISTER 4\r |
| 63 | \r |
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64 | /**\r |
| 65 | Operate the PCI register via PciIo function interface.\r |
| 66 | \r |
| 67 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r |
| 68 | @param Command Operator command\r |
| 69 | @param Offset The address within the PCI configuration space for the PCI controller.\r |
| 70 | @param Operation Type of Operation\r |
| 71 | @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER\r |
| 72 | \r |
| 73 | @return status of PciIo operation\r |
| 74 | **/\r |
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75 | EFI_STATUS\r |
| 76 | PciOperateRegister (\r |
| 77 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 78 | IN UINT16 Command,\r |
| 79 | IN UINT8 Offset,\r |
| 80 | IN UINT8 Operation,\r |
| 81 | OUT UINT16 *PtrCommand\r |
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82 | );\r |
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83 | \r |
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84 | /**\r |
| 85 | check the cpability of this device supports\r |
| 86 | \r |
| 87 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r |
| 88 | \r |
| 89 | @retval TRUE Support\r |
| 90 | @retval FALSE Not support\r |
| 91 | **/\r |
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92 | BOOLEAN\r |
| 93 | PciCapabilitySupport (\r |
| 94 | IN PCI_IO_DEVICE *PciIoDevice\r |
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95 | );\r |
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96 | \r |
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97 | /**\r |
| 98 | Locate cap reg.\r |
| 99 | \r |
| 100 | @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r |
| 101 | @param CapId - The cap ID.\r |
| 102 | @param Offset - A pointer to the offset.\r |
| 103 | @param NextRegBlock - A pointer to the next block.\r |
| 104 | \r |
| 105 | @retval EFI_UNSUPPORTED Pci device does not support\r |
| 106 | @retval EFI_NOT_FOUND Pci device support but can not find register block.\r |
| 107 | @retval EFI_SUCCESS Success to locate capability register block\r |
| 108 | **/\r |
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109 | EFI_STATUS\r |
| 110 | LocateCapabilityRegBlock (\r |
| 111 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 112 | IN UINT8 CapId,\r |
| 113 | IN OUT UINT8 *Offset,\r |
| 114 | OUT UINT8 *NextRegBlock OPTIONAL\r |
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115 | );\r |
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116 | \r |
| 117 | \r |
| 118 | #define PciReadCommandRegister(a,b) \\r |
| 119 | PciOperateRegister (a,0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r |
| 120 | \r |
| 121 | #define PciSetCommandRegister(a,b) \\r |
| 122 | PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r |
| 123 | \r |
| 124 | #define PciEnableCommandRegister(a,b) \\r |
| 125 | PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r |
| 126 | \r |
| 127 | #define PciDisableCommandRegister(a,b) \\r |
| 128 | PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r |
| 129 | \r |
| 130 | #define PciReadBridgeControlRegister(a,b) \\r |
| 131 | PciOperateRegister (a,0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r |
| 132 | \r |
| 133 | #define PciSetBridgeControlRegister(a,b) \\r |
| 134 | PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r |
| 135 | \r |
| 136 | #define PciEnableBridgeControlRegister(a,b) \\r |
| 137 | PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r |
| 138 | \r |
| 139 | #define PciDisableBridgeControlRegister(a,b) \\r |
| 140 | PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r |
| 141 | \r |
| 142 | #endif\r |
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