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[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciEnumerator.c
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97404058 1/** @file\r
ead42efc 2\r
c07ed17d 3Copyright (c) 2006 - 2008, Intel Corporation \r
3db51098 4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
ead42efc 11\r
3db51098 12**/\r
ead42efc 13\r
ead42efc 14\r
03417d8d 15#include "PciBus.h"\r
ead42efc 16#include "PciEnumerator.h"\r
ead42efc 17#include "PciOptionRomSupport.h"\r
18\r
bcd70414 19/**\r
ead42efc 20 This routine is used to enumerate entire pci bus system\r
97404058 21 in a given platform.\r
ead42efc 22\r
97404058 23 @param Controller Parent controller handle.\r
a3b8e257 24 \r
97404058 25 @return Status of enumerating.\r
bcd70414 26**/\r
a3b8e257 27EFI_STATUS\r
28PciEnumerator (\r
29 IN EFI_HANDLE Controller\r
30 )\r
ead42efc 31{\r
32\r
33 EFI_HANDLE HostBridgeHandle;\r
34 EFI_STATUS Status;\r
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
37\r
38 //\r
39 // If PCI bus has already done the full enumeration, never do it again\r
40 //\r
41 if (!gFullEnumeration) {\r
42 return PciEnumeratorLight (Controller);\r
43 }\r
44\r
ead42efc 45 //\r
46 // Get the rootbridge Io protocol to find the host bridge handle\r
47 //\r
48 Status = gBS->OpenProtocol (\r
49 Controller,\r
50 &gEfiPciRootBridgeIoProtocolGuid,\r
51 (VOID **) &PciRootBridgeIo,\r
52 gPciBusDriverBinding.DriverBindingHandle,\r
53 Controller,\r
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
55 );\r
56\r
57 if (EFI_ERROR (Status)) {\r
58 return Status;\r
59 }\r
60\r
61 //\r
62 // Get the host bridge handle\r
63 //\r
64 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
65\r
66 //\r
67 // Get the pci host bridge resource allocation protocol\r
68 //\r
69 Status = gBS->OpenProtocol (\r
70 HostBridgeHandle,\r
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
72 (VOID **) &PciResAlloc,\r
73 gPciBusDriverBinding.DriverBindingHandle,\r
74 Controller,\r
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
76 );\r
77\r
78 if (EFI_ERROR (Status)) {\r
79 return Status;\r
80 }\r
81\r
82 //\r
83 // Notify the pci bus enumeration is about to begin\r
84 //\r
85 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);\r
86\r
87 //\r
88 // Start the bus allocation phase\r
89 //\r
90 Status = PciHostBridgeEnumerator (PciResAlloc);\r
91\r
92 if (EFI_ERROR (Status)) {\r
93 return Status;\r
94 }\r
95\r
96 //\r
97 // Submit the resource request\r
98 //\r
99 Status = PciHostBridgeResourceAllocator (PciResAlloc);\r
100\r
101 if (EFI_ERROR (Status)) {\r
102 return Status;\r
103 }\r
104\r
105 //\r
106 // Process P2C\r
107 //\r
108 Status = PciHostBridgeP2CProcess (PciResAlloc);\r
109\r
110 if (EFI_ERROR (Status)) {\r
111 return Status;\r
112 }\r
113\r
114 //\r
115 // Process attributes for devices on this host bridge\r
116 //\r
117 Status = PciHostBridgeDeviceAttribute (PciResAlloc);\r
118 if (EFI_ERROR (Status)) {\r
119 return Status;\r
120 }\r
121\r
122 gFullEnumeration = FALSE;\r
123\r
124 return EFI_SUCCESS;\r
125}\r
126\r
a3b8e257 127/**\r
128 Enumerate PCI root bridge\r
129 \r
97404058 130 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
131 @param RootBridgeDev Instance of root bridge device.\r
a3b8e257 132 \r
97404058 133 @retval EFI_SUCCESS Success to enumerate root bridge.\r
134 @retval Others Fail to enumerate root bridge.\r
a3b8e257 135 \r
136**/\r
ead42efc 137EFI_STATUS\r
138PciRootBridgeEnumerator (\r
139 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
140 IN PCI_IO_DEVICE *RootBridgeDev\r
141 )\r
ead42efc 142{\r
143 EFI_STATUS Status;\r
5326528b 144 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
ead42efc 145 UINT8 SubBusNumber;\r
146 UINT8 StartBusNumber;\r
147 UINT8 PaddedBusRange;\r
148 EFI_HANDLE RootBridgeHandle;\r
149\r
150 SubBusNumber = 0;\r
151 StartBusNumber = 0;\r
152 PaddedBusRange = 0;\r
153\r
154 //\r
155 // Get the root bridge handle\r
156 //\r
157 RootBridgeHandle = RootBridgeDev->Handle;\r
158\r
159 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
160 EFI_PROGRESS_CODE,\r
161 EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_BUS_ENUM,\r
162 RootBridgeDev->DevicePath\r
163 );\r
164\r
165 //\r
166 // Get the Bus information\r
167 //\r
168 Status = PciResAlloc->StartBusEnumeration (\r
169 PciResAlloc,\r
170 RootBridgeHandle,\r
5326528b 171 (VOID **) &Configuration\r
ead42efc 172 );\r
173\r
174 if (EFI_ERROR (Status)) {\r
175 return Status;\r
176 }\r
177\r
178 //\r
179 // Get the bus number to start with\r
180 //\r
5326528b 181 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
182 PaddedBusRange = (UINT8) (Configuration->AddrRangeMax);\r
ead42efc 183\r
184 //\r
185 // Initialize the subordinate bus number\r
186 //\r
187 SubBusNumber = StartBusNumber;\r
188\r
ff62de37 189 //\r
190 // Reset all assigned PCI bus number\r
191 //\r
192 ResetAllPpbBusNumber (\r
193 RootBridgeDev, \r
194 StartBusNumber\r
195 );\r
196\r
ead42efc 197 //\r
198 // Assign bus number\r
199 //\r
200 Status = PciScanBus (\r
201 RootBridgeDev,\r
5326528b 202 (UINT8) (Configuration->AddrRangeMin),\r
ead42efc 203 &SubBusNumber,\r
204 &PaddedBusRange\r
205 );\r
206\r
207 if (EFI_ERROR (Status)) {\r
208 return Status;\r
209 }\r
210\r
211\r
212 //\r
213 // Assign max bus number scanned\r
214 //\r
5326528b 215 Configuration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;\r
ead42efc 216\r
217 //\r
218 // Set bus number\r
219 //\r
220 Status = PciResAlloc->SetBusNumbers (\r
221 PciResAlloc,\r
222 RootBridgeHandle,\r
5326528b 223 Configuration\r
ead42efc 224 );\r
4beb4afe 225 \r
5326528b 226 gBS->FreePool (Configuration);\r
4beb4afe 227 \r
ead42efc 228 if (EFI_ERROR (Status)) {\r
229 return Status;\r
230 }\r
231\r
232 return EFI_SUCCESS;\r
233}\r
234\r
a3b8e257 235/**\r
236 This routine is used to process option rom on a certain root bridge\r
237 \r
238 @param Bridge Given parent's root bridge\r
239 @param RomBase Base address of ROM driver loaded from\r
240 @param MaxLength Max rom size\r
241 \r
242 @retval EFI_SUCCESS Success to process option rom image.\r
243**/\r
ead42efc 244EFI_STATUS\r
245ProcessOptionRom (\r
246 IN PCI_IO_DEVICE *Bridge,\r
247 IN UINT64 RomBase,\r
248 IN UINT64 MaxLength\r
249 )\r
ead42efc 250{\r
251 LIST_ENTRY *CurrentLink;\r
252 PCI_IO_DEVICE *Temp;\r
ead42efc 253\r
254 //\r
255 // Go through bridges to reach all devices\r
256 //\r
257 CurrentLink = Bridge->ChildList.ForwardLink;\r
97404058 258 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
ead42efc 259 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
260 if (!IsListEmpty (&Temp->ChildList)) {\r
261\r
262 //\r
263 // Go further to process the option rom under this bridge\r
264 //\r
eb9a9a5e 265 ProcessOptionRom (Temp, RomBase, MaxLength);\r
ead42efc 266 }\r
267\r
268 if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {\r
269\r
270 //\r
271 // Load and process the option rom\r
272 //\r
eb9a9a5e 273 LoadOpRomImage (Temp, RomBase);\r
ead42efc 274 }\r
275\r
276 CurrentLink = CurrentLink->ForwardLink;\r
277 }\r
278\r
279 return EFI_SUCCESS;\r
280}\r
281\r
a3b8e257 282/**\r
283 This routine is used to assign bus number to the given PCI bus system\r
284 \r
97404058 285 @param Bridge Parent root bridge instance.\r
286 @param StartBusNumber Number of beginning.\r
287 @param SubBusNumber the number of sub bus.\r
a3b8e257 288 \r
97404058 289 @retval EFI_SUCCESS Success to assign bus number.\r
a3b8e257 290**/\r
ead42efc 291EFI_STATUS\r
292PciAssignBusNumber (\r
293 IN PCI_IO_DEVICE *Bridge,\r
294 IN UINT8 StartBusNumber,\r
295 OUT UINT8 *SubBusNumber\r
296 )\r
ead42efc 297{\r
298 EFI_STATUS Status;\r
299 PCI_TYPE00 Pci;\r
300 UINT8 Device;\r
301 UINT8 Func;\r
302 UINT64 Address;\r
303 UINTN SecondBus;\r
304 UINT16 Register;\r
305 UINT8 Register8;\r
306 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
307\r
308 PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
309\r
310 SecondBus = 0;\r
311 Register = 0;\r
312\r
313 *SubBusNumber = StartBusNumber;\r
314\r
315 //\r
316 // First check to see whether the parent is ppb\r
317 //\r
318 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
319 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
320\r
321 //\r
322 // Check to see whether a pci device is present\r
323 //\r
324\r
325 Status = PciDevicePresent (\r
326 PciRootBridgeIo,\r
327 &Pci,\r
328 StartBusNumber,\r
329 Device,\r
330 Func\r
331 );\r
332\r
333 if (!EFI_ERROR (Status) &&\r
334 (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {\r
335\r
336 //\r
337 // Reserved one bus for cardbus bridge\r
338 //\r
339 SecondBus = ++(*SubBusNumber);\r
340\r
341 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
342\r
343 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
344\r
345 Status = PciRootBridgeIoWrite (\r
346 PciRootBridgeIo,\r
347 &Pci,\r
348 EfiPciWidthUint16,\r
349 Address,\r
350 1,\r
351 &Register\r
352 );\r
353\r
354 //\r
355 // Initialize SubBusNumber to SecondBus\r
356 //\r
357 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
358 Status = PciRootBridgeIoWrite (\r
359 PciRootBridgeIo,\r
360 &Pci,\r
361 EfiPciWidthUint8,\r
362 Address,\r
363 1,\r
364 SubBusNumber\r
365 );\r
366 //\r
367 // If it is PPB, resursively search down this bridge\r
368 //\r
369 if (IS_PCI_BRIDGE (&Pci)) {\r
370\r
371 Register8 = 0xFF;\r
372 Status = PciRootBridgeIoWrite (\r
373 PciRootBridgeIo,\r
374 &Pci,\r
375 EfiPciWidthUint8,\r
376 Address,\r
377 1,\r
378 &Register8\r
379 );\r
380\r
381 Status = PciAssignBusNumber (\r
382 Bridge,\r
383 (UINT8) (SecondBus),\r
384 SubBusNumber\r
385 );\r
386\r
387 if (EFI_ERROR (Status)) {\r
388 return EFI_DEVICE_ERROR;\r
389 }\r
390 }\r
391\r
392 //\r
393 // Set the current maximum bus number under the PPB\r
394 //\r
395\r
396 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
397\r
398 Status = PciRootBridgeIoWrite (\r
399 PciRootBridgeIo,\r
400 &Pci,\r
401 EfiPciWidthUint8,\r
402 Address,\r
403 1,\r
404 SubBusNumber\r
405 );\r
406\r
407 }\r
408\r
409 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
410\r
411 //\r
412 // Skip sub functions, this is not a multi function device\r
413 //\r
414\r
415 Func = PCI_MAX_FUNC;\r
416 }\r
417 }\r
418 }\r
419\r
420 return EFI_SUCCESS;\r
421}\r
422\r
bcd70414 423/**\r
ead42efc 424 This routine is used to determine the root bridge attribute by interfacing\r
425 the host bridge resource allocation protocol.\r
426\r
a3b8e257 427 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
428 @param RootBridgeDev Root bridge instance\r
429 \r
430 @retval EFI_SUCCESS Success to get root bridge's attribute\r
431 @retval Others Fail to get attribute\r
bcd70414 432**/\r
a3b8e257 433EFI_STATUS\r
434DetermineRootBridgeAttributes (\r
435 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
436 IN PCI_IO_DEVICE *RootBridgeDev\r
437 )\r
ead42efc 438{\r
439 UINT64 Attributes;\r
440 EFI_STATUS Status;\r
441 EFI_HANDLE RootBridgeHandle;\r
442\r
443 Attributes = 0;\r
444 RootBridgeHandle = RootBridgeDev->Handle;\r
445\r
446 //\r
447 // Get root bridge attribute by calling into pci host bridge resource allocation protocol\r
448 //\r
449 Status = PciResAlloc->GetAllocAttributes (\r
450 PciResAlloc,\r
451 RootBridgeHandle,\r
452 &Attributes\r
453 );\r
454\r
455 if (EFI_ERROR (Status)) {\r
456 return Status;\r
457 }\r
458\r
459 //\r
460 // Here is the point where PCI bus driver calls HOST bridge allocation protocol\r
461 // Currently we hardcoded for ea815\r
462 //\r
463\r
97404058 464 if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
ead42efc 465 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;\r
466 }\r
467\r
97404058 468 if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {\r
ead42efc 469 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;\r
470 }\r
471\r
472 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;\r
473 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;\r
474 RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;\r
475\r
476 return EFI_SUCCESS;\r
477}\r
478\r
a3b8e257 479/**\r
480 Get Max Option Rom size on this bridge\r
481 \r
97404058 482 @param Bridge Bridge device instance.\r
483 @return Max size of option rom.\r
a3b8e257 484**/\r
ead42efc 485UINT64\r
486GetMaxOptionRomSize (\r
487 IN PCI_IO_DEVICE *Bridge\r
488 )\r
ead42efc 489{\r
490 LIST_ENTRY *CurrentLink;\r
491 PCI_IO_DEVICE *Temp;\r
492 UINT64 MaxOptionRomSize;\r
493 UINT64 TempOptionRomSize;\r
494\r
495 MaxOptionRomSize = 0;\r
496\r
497 //\r
498 // Go through bridges to reach all devices\r
499 //\r
500 CurrentLink = Bridge->ChildList.ForwardLink;\r
97404058 501 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
ead42efc 502 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
503 if (!IsListEmpty (&Temp->ChildList)) {\r
504\r
505 //\r
506 // Get max option rom size under this bridge\r
507 //\r
508 TempOptionRomSize = GetMaxOptionRomSize (Temp);\r
509\r
510 //\r
511 // Compare with the option rom size of the bridge\r
512 // Get the larger one\r
513 //\r
514 if (Temp->RomSize > TempOptionRomSize) {\r
515 TempOptionRomSize = Temp->RomSize;\r
516 }\r
517\r
518 } else {\r
519\r
520 //\r
521 // For devices get the rom size directly\r
522 //\r
523 TempOptionRomSize = Temp->RomSize;\r
524 }\r
525\r
526 //\r
527 // Get the largest rom size on this bridge\r
528 //\r
529 if (TempOptionRomSize > MaxOptionRomSize) {\r
530 MaxOptionRomSize = TempOptionRomSize;\r
531 }\r
532\r
533 CurrentLink = CurrentLink->ForwardLink;\r
534 }\r
535\r
536 return MaxOptionRomSize;\r
537}\r
538\r
a3b8e257 539/**\r
540 Process attributes of devices on this host bridge\r
541 \r
97404058 542 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
a3b8e257 543 \r
97404058 544 @retval EFI_NOT_FOUND Can not find the specific root bridge device.\r
545 @retval EFI_SUCCESS Success Process attribute.\r
546 @retval Others Can not determine the root bridge device's attribute.\r
a3b8e257 547**/\r
ead42efc 548EFI_STATUS\r
549PciHostBridgeDeviceAttribute (\r
550 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
551 )\r
ead42efc 552{\r
553 EFI_HANDLE RootBridgeHandle;\r
554 PCI_IO_DEVICE *RootBridgeDev;\r
555 EFI_STATUS Status;\r
556\r
557 RootBridgeHandle = NULL;\r
558\r
559 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
560\r
561 //\r
562 // Get RootBridg Device by handle\r
563 //\r
564 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
565\r
566 if (RootBridgeDev == NULL) {\r
567 return EFI_NOT_FOUND;\r
568 }\r
569\r
570 //\r
571 // Set the attributes for devcies behind the Root Bridge\r
572 //\r
573 Status = DetermineDeviceAttribute (RootBridgeDev);\r
574 if (EFI_ERROR (Status)) {\r
575 return Status;\r
576 }\r
577\r
578 }\r
579\r
580 return EFI_SUCCESS;\r
581}\r
582\r
a3b8e257 583/**\r
584 Get resource allocation status from the ACPI pointer\r
585\r
586 @param AcpiConfig Point to Acpi configuration table\r
587 @param IoResStatus Return the status of I/O resource\r
588 @param Mem32ResStatus Return the status of 32-bit Memory resource\r
589 @param PMem32ResStatus Return the status of 32-bit PMemory resource\r
590 @param Mem64ResStatus Return the status of 64-bit Memory resource\r
591 @param PMem64ResStatus Return the status of 64-bit PMemory resource\r
592 \r
593 @retval EFI_SUCCESS Success to get resource allocation status from ACPI configuration table.\r
594**/\r
ead42efc 595EFI_STATUS\r
596GetResourceAllocationStatus (\r
597 VOID *AcpiConfig,\r
598 OUT UINT64 *IoResStatus,\r
599 OUT UINT64 *Mem32ResStatus,\r
600 OUT UINT64 *PMem32ResStatus,\r
601 OUT UINT64 *Mem64ResStatus,\r
602 OUT UINT64 *PMem64ResStatus\r
603 )\r
ead42efc 604{\r
605\r
606 UINT8 *Temp;\r
607 UINT64 ResStatus;\r
5326528b 608 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
ead42efc 609\r
610 Temp = (UINT8 *) AcpiConfig;\r
611\r
612 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
613\r
5326528b 614 ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
615 ResStatus = ACPIAddressDesc->AddrTranslationOffset;\r
ead42efc 616\r
5326528b 617 switch (ACPIAddressDesc->ResType) {\r
ead42efc 618 case 0:\r
5326528b 619 if (ACPIAddressDesc->AddrSpaceGranularity == 32) {\r
620 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
ead42efc 621 //\r
622 // Pmem32\r
623 //\r
624 *PMem32ResStatus = ResStatus;\r
625 } else {\r
626 //\r
627 // Mem32\r
628 //\r
629 *Mem32ResStatus = ResStatus;\r
630 }\r
631 }\r
632\r
5326528b 633 if (ACPIAddressDesc->AddrSpaceGranularity == 64) {\r
634 if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
ead42efc 635 //\r
636 // PMem64\r
637 //\r
638 *PMem64ResStatus = ResStatus;\r
639 } else {\r
640 //\r
641 // Mem64\r
642 //\r
643 *Mem64ResStatus = ResStatus;\r
644 }\r
645 }\r
646\r
647 break;\r
648\r
649 case 1:\r
650 //\r
651 // Io\r
652 //\r
653 *IoResStatus = ResStatus;\r
654 break;\r
655\r
656 default:\r
657 break;\r
658 }\r
659\r
660 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
661 }\r
662\r
663 return EFI_SUCCESS;\r
664}\r
665\r
a3b8e257 666/**\r
667 Remove a PCI device from device pool and mark its bar\r
668 \r
97404058 669 @param PciDevice Instance of Pci device.\r
a3b8e257 670 \r
97404058 671 @retval EFI_SUCCESS Success Operation.\r
672 @retval EFI_ABORTED Pci device is a root bridge.\r
a3b8e257 673**/\r
ead42efc 674EFI_STATUS\r
675RejectPciDevice (\r
676 IN PCI_IO_DEVICE *PciDevice\r
677 )\r
ead42efc 678{\r
679 PCI_IO_DEVICE *Bridge;\r
680 PCI_IO_DEVICE *Temp;\r
681 LIST_ENTRY *CurrentLink;\r
682\r
683 //\r
684 // Remove the padding resource from a bridge\r
685 //\r
686 if ( IS_PCI_BRIDGE(&PciDevice->Pci) && \\r
97404058 687 PciDevice->ResourcePaddingDescriptors != NULL ) {\r
ead42efc 688 gBS->FreePool (PciDevice->ResourcePaddingDescriptors);\r
689 PciDevice->ResourcePaddingDescriptors = NULL;\r
690 return EFI_SUCCESS;\r
691 }\r
692\r
693 //\r
694 // Skip RB and PPB\r
695 //\r
97404058 696 if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {\r
ead42efc 697 return EFI_ABORTED;\r
698 }\r
699\r
700 if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {\r
701 //\r
702 // Get the root bridge device\r
703 //\r
704 Bridge = PciDevice;\r
97404058 705 while (Bridge->Parent != NULL) {\r
ead42efc 706 Bridge = Bridge->Parent;\r
707 }\r
708\r
709 RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);\r
710\r
711 //\r
712 // Mark its bar\r
713 //\r
714 InitializeP2C (PciDevice);\r
715 }\r
716\r
717 //\r
718 // Remove the device\r
719 //\r
720 Bridge = PciDevice->Parent;\r
721 CurrentLink = Bridge->ChildList.ForwardLink;\r
97404058 722 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
ead42efc 723 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
724 if (Temp == PciDevice) {\r
725 InitializePciDevice (Temp);\r
726 RemoveEntryList (CurrentLink);\r
727 FreePciDevice (Temp);\r
728 return EFI_SUCCESS;\r
729 }\r
730\r
731 CurrentLink = CurrentLink->ForwardLink;\r
732 }\r
733\r
734 return EFI_ABORTED;\r
735}\r
736\r
a3b8e257 737/**\r
97404058 738 Determine whethter a PCI device can be rejected.\r
a3b8e257 739 \r
97404058 740 @param PciResNode Pointer to Pci resource node instance.\r
a3b8e257 741 \r
97404058 742 @return whethter a PCI device can be rejected.\r
a3b8e257 743**/\r
ead42efc 744BOOLEAN\r
745IsRejectiveDevice (\r
746 IN PCI_RESOURCE_NODE *PciResNode\r
747 )\r
ead42efc 748{\r
749 PCI_IO_DEVICE *Temp;\r
750\r
751 Temp = PciResNode->PciDev;\r
752\r
753 //\r
754 // Ensure the device is present\r
755 //\r
97404058 756 if (Temp == NULL) {\r
ead42efc 757 return FALSE;\r
758 }\r
759\r
760 //\r
761 // PPB and RB should go ahead\r
762 //\r
97404058 763 if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {\r
ead42efc 764 return TRUE;\r
765 }\r
766\r
767 //\r
768 // Skip device on Bus0\r
769 //\r
97404058 770 if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {\r
ead42efc 771 return FALSE;\r
772 }\r
773\r
774 //\r
775 // Skip VGA\r
776 //\r
777 if (IS_PCI_VGA (&Temp->Pci)) {\r
778 return FALSE;\r
779 }\r
780\r
781 return TRUE;\r
782}\r
783\r
a3b8e257 784/**\r
785 Compare two resource node and get the larger resource consumer\r
786 \r
787 @param PciResNode1 resource node 1 want to be compared\r
788 @param PciResNode2 resource node 2 want to be compared\r
789 \r
790 @return Larger resource consumer.\r
791**/\r
ead42efc 792PCI_RESOURCE_NODE *\r
793GetLargerConsumerDevice (\r
794 IN PCI_RESOURCE_NODE *PciResNode1,\r
795 IN PCI_RESOURCE_NODE *PciResNode2\r
796 )\r
ead42efc 797{\r
97404058 798 if (PciResNode2 == NULL) {\r
ead42efc 799 return PciResNode1;\r
800 }\r
801\r
97404058 802 if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \\r
ead42efc 803 && (PciResNode2->ResourceUsage != PciResUsagePadding) )\r
804 {\r
805 return PciResNode1;\r
806 }\r
807\r
97404058 808 if (PciResNode1 == NULL) {\r
ead42efc 809 return PciResNode2;\r
810 }\r
811\r
812 if ((PciResNode1->Length) > (PciResNode2->Length)) {\r
813 return PciResNode1;\r
814 }\r
815\r
816 return PciResNode2;\r
817\r
818}\r
819\r
a3b8e257 820\r
821/**\r
97404058 822 Get the max resource consumer in the host resource pool.\r
a3b8e257 823 \r
97404058 824 @param ResPool Pointer to resource pool node.\r
a3b8e257 825 \r
97404058 826 @return the max resource consumer in the host resource pool.\r
a3b8e257 827**/\r
ead42efc 828PCI_RESOURCE_NODE *\r
829GetMaxResourceConsumerDevice (\r
830 IN PCI_RESOURCE_NODE *ResPool\r
831 )\r
ead42efc 832{\r
833 PCI_RESOURCE_NODE *Temp;\r
834 LIST_ENTRY *CurrentLink;\r
835 PCI_RESOURCE_NODE *PciResNode;\r
836 PCI_RESOURCE_NODE *PPBResNode;\r
837\r
838 PciResNode = NULL;\r
839\r
840 CurrentLink = ResPool->ChildList.ForwardLink;\r
97404058 841 while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {\r
ead42efc 842\r
843 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
844\r
845 if (!IsRejectiveDevice (Temp)) {\r
846 CurrentLink = CurrentLink->ForwardLink;\r
847 continue;\r
848 }\r
849\r
97404058 850 if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \\r
ead42efc 851 && (Temp->ResourceUsage != PciResUsagePadding))\r
852 {\r
853 PPBResNode = GetMaxResourceConsumerDevice (Temp);\r
854 PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);\r
855 } else {\r
856 PciResNode = GetLargerConsumerDevice (PciResNode, Temp);\r
857 }\r
858\r
859 CurrentLink = CurrentLink->ForwardLink;\r
860 }\r
861\r
862 return PciResNode;\r
863}\r
864\r
a3b8e257 865/**\r
866 Adjust host bridge allocation so as to reduce resource requirement\r
867 \r
97404058 868 @param IoPool Pointer to instance of I/O resource Node.\r
869 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r
870 @param PMem32Pool Pointer to instance of 32-bit Pmemory resource node.\r
871 @param Mem64Pool Pointer to instance of 64-bit memory resource node.\r
872 @param PMem64Pool Pointer to instance of 64-bit Pmemory resource node.\r
873 @param IoResStatus Status of I/O resource Node.\r
874 @param Mem32ResStatus Status of 32-bit memory resource Node.\r
875 @param PMem32ResStatus Status of 32-bit Pmemory resource node.\r
876 @param Mem64ResStatus Status of 64-bit memory resource node.\r
877 @param PMem64ResStatus Status of 64-bit Pmemory resource node.\r
a3b8e257 878**/\r
ead42efc 879EFI_STATUS\r
880PciHostBridgeAdjustAllocation (\r
881 IN PCI_RESOURCE_NODE *IoPool,\r
882 IN PCI_RESOURCE_NODE *Mem32Pool,\r
883 IN PCI_RESOURCE_NODE *PMem32Pool,\r
884 IN PCI_RESOURCE_NODE *Mem64Pool,\r
885 IN PCI_RESOURCE_NODE *PMem64Pool,\r
886 IN UINT64 IoResStatus,\r
887 IN UINT64 Mem32ResStatus,\r
888 IN UINT64 PMem32ResStatus,\r
889 IN UINT64 Mem64ResStatus,\r
890 IN UINT64 PMem64ResStatus\r
891 )\r
ead42efc 892{\r
893 BOOLEAN AllocationAjusted;\r
894 PCI_RESOURCE_NODE *PciResNode;\r
895 PCI_RESOURCE_NODE *ResPool[5];\r
896 PCI_IO_DEVICE *RemovedPciDev[5];\r
897 UINT64 ResStatus[5];\r
898 UINTN RemovedPciDevNum;\r
899 UINTN DevIndex;\r
900 UINTN ResType;\r
901 EFI_STATUS Status;\r
1d6d9e7e 902 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
ead42efc 903\r
904 PciResNode = NULL;\r
905 ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));\r
906 RemovedPciDevNum = 0;\r
907\r
908 ResPool[0] = IoPool;\r
909 ResPool[1] = Mem32Pool;\r
910 ResPool[2] = PMem32Pool;\r
911 ResPool[3] = Mem64Pool;\r
912 ResPool[4] = PMem64Pool;\r
913\r
914 ResStatus[0] = IoResStatus;\r
915 ResStatus[1] = Mem32ResStatus;\r
916 ResStatus[2] = PMem32ResStatus;\r
917 ResStatus[3] = Mem64ResStatus;\r
918 ResStatus[4] = PMem64ResStatus;\r
919\r
920 AllocationAjusted = FALSE;\r
921\r
922 for (ResType = 0; ResType < 5; ResType++) {\r
923\r
924 if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {\r
925 continue;\r
926 }\r
927\r
7508355e 928 if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {\r
ead42efc 929 //\r
930 // Hostbridge hasn't this resource type\r
931 //\r
932 return EFI_ABORTED;\r
933 }\r
934\r
935 //\r
936 // Hostbridge hasn't enough resource\r
937 //\r
938 PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);\r
97404058 939 if (PciResNode == NULL) {\r
ead42efc 940 continue;\r
941 }\r
942\r
943 //\r
944 // Check if the device has been removed before\r
945 //\r
946 for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {\r
947 if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {\r
a1d887b7 948 break;\r
ead42efc 949 }\r
950 }\r
a1d887b7 951\r
952 if (DevIndex != RemovedPciDevNum) {\r
953 continue;\r
954 }\r
ead42efc 955\r
956 //\r
957 // Remove the device if it isn't in the array\r
958 //\r
959 Status = RejectPciDevice (PciResNode->PciDev);\r
960 if (Status == EFI_SUCCESS) {\r
961\r
962 //\r
963 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
964 //\r
965 //\r
966 // Have no way to get ReqRes, AllocRes & Bar here\r
967 //\r
968 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
969 AllocFailExtendedData.DevicePathSize = sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
970 AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;\r
971 AllocFailExtendedData.Bar = PciResNode->Bar;\r
972\r
973 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
974 EFI_PROGRESS_CODE,\r
975 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
976 (VOID *) &AllocFailExtendedData,\r
977 sizeof (AllocFailExtendedData)\r
978 );\r
979\r
980 //\r
981 // Add it to the array and indicate at least a device has been rejected\r
982 //\r
983 RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;\r
984 AllocationAjusted = TRUE;\r
985 }\r
986 }\r
987 //\r
988 // End for\r
989 //\r
990\r
991 if (AllocationAjusted) {\r
992 return EFI_SUCCESS;\r
993 } else {\r
994 return EFI_ABORTED;\r
995 }\r
996}\r
997\r
a3b8e257 998/**\r
999 Summary requests for all resource type, and contruct ACPI resource\r
1000 requestor instance.\r
1001 \r
1002 @param Bridge detecting bridge\r
1003 @param IoNode Pointer to instance of I/O resource Node\r
1004 @param Mem32Node Pointer to instance of 32-bit memory resource Node\r
1005 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node\r
1006 @param Mem64Node Pointer to instance of 64-bit memory resource node\r
1007 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r
1008 @param pConfig outof buffer holding new constructed APCI resource requestor\r
1009**/\r
ead42efc 1010EFI_STATUS\r
1011ConstructAcpiResourceRequestor (\r
1012 IN PCI_IO_DEVICE *Bridge,\r
1013 IN PCI_RESOURCE_NODE *IoNode,\r
1014 IN PCI_RESOURCE_NODE *Mem32Node,\r
1015 IN PCI_RESOURCE_NODE *PMem32Node,\r
1016 IN PCI_RESOURCE_NODE *Mem64Node,\r
1017 IN PCI_RESOURCE_NODE *PMem64Node,\r
1018 OUT VOID **pConfig\r
1019 )\r
ead42efc 1020{\r
1021 UINT8 NumConfig;\r
1022 UINT8 Aperture;\r
1023 UINT8 *Configuration;\r
1024 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1025 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
1026\r
1027 NumConfig = 0;\r
1028 Aperture = 0;\r
1029\r
1030 *pConfig = NULL;\r
1031\r
1032 //\r
1033 // if there is io request, add to the io aperture\r
1034 //\r
1035 if (ResourceRequestExisted (IoNode)) {\r
1036 NumConfig++;\r
1037 Aperture |= 0x01;\r
1038 }\r
1039\r
1040 //\r
1041 // if there is mem32 request, add to the mem32 aperture\r
1042 //\r
1043 if (ResourceRequestExisted (Mem32Node)) {\r
1044 NumConfig++;\r
1045 Aperture |= 0x02;\r
1046 }\r
1047\r
1048 //\r
1049 // if there is pmem32 request, add to the pmem32 aperture\r
1050 //\r
1051 if (ResourceRequestExisted (PMem32Node)) {\r
1052 NumConfig++;\r
1053 Aperture |= 0x04;\r
1054 }\r
1055\r
1056 //\r
1057 // if there is mem64 request, add to the mem64 aperture\r
1058 //\r
1059 if (ResourceRequestExisted (Mem64Node)) {\r
1060 NumConfig++;\r
1061 Aperture |= 0x08;\r
1062 }\r
1063\r
1064 //\r
1065 // if there is pmem64 request, add to the pmem64 aperture\r
1066 //\r
1067 if (ResourceRequestExisted (PMem64Node)) {\r
1068 NumConfig++;\r
1069 Aperture |= 0x10;\r
1070 }\r
1071\r
1072 if (NumConfig != 0) {\r
1073\r
1074 //\r
1075 // If there is at least one type of resource request,\r
1076 // allocate a acpi resource node\r
1077 //\r
1078 Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1079 if (Configuration == NULL) {\r
1080 return EFI_OUT_OF_RESOURCES;\r
1081 }\r
1082\r
1083 ZeroMem (\r
1084 Configuration,\r
1085 sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
1086 );\r
1087\r
1088 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
1089\r
1090 //\r
1091 // Deal with io aperture\r
1092 //\r
97404058 1093 if ((Aperture & 0x01) != 0) {\r
ead42efc 1094 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1095 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
1096 //\r
1097 // Io\r
1098 //\r
1099 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
1100 //\r
1101 // non ISA range\r
1102 //\r
1103 Ptr->SpecificFlag = 1;\r
1104 Ptr->AddrLen = IoNode->Length;\r
1105 Ptr->AddrRangeMax = IoNode->Alignment;\r
1106\r
1107 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
1108 }\r
1109 //\r
1110 // Deal with mem32 aperture\r
1111 //\r
97404058 1112 if ((Aperture & 0x02) != 0) {\r
ead42efc 1113 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1114 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
1115 //\r
1116 // Mem\r
1117 //\r
1118 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1119 //\r
1120 // Nonprefechable\r
1121 //\r
1122 Ptr->SpecificFlag = 0;\r
1123 //\r
1124 // 32 bit\r
1125 //\r
1126 Ptr->AddrSpaceGranularity = 32;\r
1127 Ptr->AddrLen = Mem32Node->Length;\r
1128 Ptr->AddrRangeMax = Mem32Node->Alignment;\r
1129\r
1130 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
1131 }\r
1132\r
1133 //\r
1134 // Deal with Pmem32 aperture\r
1135 //\r
97404058 1136 if ((Aperture & 0x04) != 0) {\r
ead42efc 1137 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1138 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
1139 //\r
1140 // Mem\r
1141 //\r
1142 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1143 //\r
1144 // prefechable\r
1145 //\r
1146 Ptr->SpecificFlag = 0x6;\r
1147 //\r
1148 // 32 bit\r
1149 //\r
1150 Ptr->AddrSpaceGranularity = 32;\r
1151 Ptr->AddrLen = PMem32Node->Length;\r
1152 Ptr->AddrRangeMax = PMem32Node->Alignment;\r
1153\r
1154 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
1155 }\r
1156 //\r
1157 // Deal with mem64 aperture\r
1158 //\r
97404058 1159 if ((Aperture & 0x08) != 0) {\r
ead42efc 1160 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1161 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
1162 //\r
1163 // Mem\r
1164 //\r
1165 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1166 //\r
1167 // nonprefechable\r
1168 //\r
1169 Ptr->SpecificFlag = 0;\r
1170 //\r
1171 // 64 bit\r
1172 //\r
1173 Ptr->AddrSpaceGranularity = 64;\r
1174 Ptr->AddrLen = Mem64Node->Length;\r
1175 Ptr->AddrRangeMax = Mem64Node->Alignment;\r
1176\r
1177 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
1178 }\r
1179 //\r
1180 // Deal with Pmem64 aperture\r
1181 //\r
97404058 1182 if ((Aperture & 0x10) != 0) {\r
ead42efc 1183 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1184 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
1185 //\r
1186 // Mem\r
1187 //\r
1188 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1189 //\r
1190 // prefechable\r
1191 //\r
1192 Ptr->SpecificFlag = 0x06;\r
1193 //\r
1194 // 64 bit\r
1195 //\r
1196 Ptr->AddrSpaceGranularity = 64;\r
1197 Ptr->AddrLen = PMem64Node->Length;\r
1198 Ptr->AddrRangeMax = PMem64Node->Alignment;\r
1199\r
c07ed17d 1200 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
ead42efc 1201 }\r
1202\r
1203 //\r
1204 // put the checksum\r
1205 //\r
1206 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);\r
1207\r
1208 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1209 PtrEnd->Checksum = 0;\r
1210\r
1211 } else {\r
1212\r
1213 //\r
1214 // If there is no resource request\r
1215 //\r
1216 Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1217 if (Configuration == NULL) {\r
1218 return EFI_OUT_OF_RESOURCES;\r
1219 }\r
1220\r
1221 ZeroMem (Configuration, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1222\r
1223 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);\r
1224 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1225\r
1226 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Configuration + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
1227 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1228 PtrEnd->Checksum = 0;\r
1229 }\r
1230\r
1231 *pConfig = Configuration;\r
1232\r
1233 return EFI_SUCCESS;\r
1234}\r
1235\r
a3b8e257 1236/**\r
1237 Get resource base from a acpi configuration descriptor.\r
1238 \r
1239 @param pConfig an acpi configuration descriptor.\r
97404058 1240 @param IoBase output of I/O resource base address.\r
1241 @param Mem32Base output of 32-bit memory base address.\r
1242 @param PMem32Base output of 32-bit pmemory base address.\r
1243 @param Mem64Base output of 64-bit memory base address.\r
1244 @param PMem64Base output of 64-bit pmemory base address.\r
a3b8e257 1245 \r
97404058 1246 @return EFI_SUCCESS Success operation.\r
a3b8e257 1247**/\r
ead42efc 1248EFI_STATUS\r
1249GetResourceBase (\r
1250 IN VOID *pConfig,\r
1251 OUT UINT64 *IoBase,\r
1252 OUT UINT64 *Mem32Base,\r
1253 OUT UINT64 *PMem32Base,\r
1254 OUT UINT64 *Mem64Base,\r
1255 OUT UINT64 *PMem64Base\r
1256 )\r
ead42efc 1257{\r
1258 UINT8 *Temp;\r
1259 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1260 UINT64 ResStatus;\r
1261\r
1262 *IoBase = 0xFFFFFFFFFFFFFFFFULL;\r
1263 *Mem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1264 *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;\r
1265 *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1266 *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;\r
1267\r
1268 Temp = (UINT8 *) pConfig;\r
1269\r
1270 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
1271\r
1272 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
1273 ResStatus = Ptr->AddrTranslationOffset;\r
1274\r
1275 if (ResStatus == EFI_RESOURCE_SATISFIED) {\r
1276\r
1277 switch (Ptr->ResType) {\r
1278\r
1279 //\r
1280 // Memory type aperture\r
1281 //\r
1282 case 0:\r
1283\r
1284 //\r
1285 // Check to see the granularity\r
1286 //\r
1287 if (Ptr->AddrSpaceGranularity == 32) {\r
5326528b 1288 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
ead42efc 1289 *PMem32Base = Ptr->AddrRangeMin;\r
1290 } else {\r
1291 *Mem32Base = Ptr->AddrRangeMin;\r
1292 }\r
1293 }\r
1294\r
1295 if (Ptr->AddrSpaceGranularity == 64) {\r
5326528b 1296 if ((Ptr->SpecificFlag & 0x06) != 0) {\r
ead42efc 1297 *PMem64Base = Ptr->AddrRangeMin;\r
1298 } else {\r
1299 *Mem64Base = Ptr->AddrRangeMin;\r
1300 }\r
1301 }\r
1302 break;\r
1303\r
1304 case 1:\r
1305\r
1306 //\r
1307 // Io type aperture\r
1308 //\r
1309 *IoBase = Ptr->AddrRangeMin;\r
1310 break;\r
1311\r
1312 default:\r
1313 break;\r
1314\r
1315 }\r
1316 //\r
1317 // End switch\r
1318 //\r
1319 }\r
1320 //\r
1321 // End for\r
1322 //\r
1323 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
1324 }\r
1325\r
1326 return EFI_SUCCESS;\r
1327}\r
1328\r
a3b8e257 1329/**\r
1330 Enumerate pci bridge, allocate resource and determine attribute\r
1331 for devices on this bridge\r
1332 \r
97404058 1333 @param BridgeDev Pointer to instance of bridge device.\r
a3b8e257 1334 \r
97404058 1335 @retval EFI_SUCCESS Success operation.\r
1336 @retval Others Fail to enumerate.\r
a3b8e257 1337**/\r
ead42efc 1338EFI_STATUS\r
1339PciBridgeEnumerator (\r
1340 IN PCI_IO_DEVICE *BridgeDev\r
1341 )\r
ead42efc 1342{\r
1343 UINT8 SubBusNumber;\r
1344 UINT8 StartBusNumber;\r
1345 EFI_PCI_IO_PROTOCOL *PciIo;\r
1346 EFI_STATUS Status;\r
1347\r
1348 SubBusNumber = 0;\r
1349 StartBusNumber = 0;\r
1350 PciIo = &(BridgeDev->PciIo);\r
1351 Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
1352\r
1353 if (EFI_ERROR (Status)) {\r
1354 return Status;\r
1355 }\r
1356\r
1357 Status = PciAssignBusNumber (\r
1358 BridgeDev,\r
1359 StartBusNumber,\r
1360 &SubBusNumber\r
1361 );\r
1362\r
1363 if (EFI_ERROR (Status)) {\r
1364 return Status;\r
1365 }\r
1366\r
1367 Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);\r
1368\r
1369 if (EFI_ERROR (Status)) {\r
1370 return Status;\r
1371 }\r
1372\r
1373 Status = PciBridgeResourceAllocator (BridgeDev);\r
1374\r
1375 if (EFI_ERROR (Status)) {\r
1376 return Status;\r
1377 }\r
1378\r
1379 Status = DetermineDeviceAttribute (BridgeDev);\r
1380\r
1381 if (EFI_ERROR (Status)) {\r
1382 return Status;\r
1383 }\r
1384\r
1385 return EFI_SUCCESS;\r
1386\r
1387}\r
1388\r
a3b8e257 1389/**\r
1390 Allocate all kinds of resource for bridge\r
1391 \r
97404058 1392 @param Bridge Pointer to bridge instance.\r
a3b8e257 1393 \r
1394 @retval EFI_SUCCESS Success operation.\r
97404058 1395 @retval Others Fail to allocate resource for bridge.\r
a3b8e257 1396**/\r
ead42efc 1397EFI_STATUS\r
1398PciBridgeResourceAllocator (\r
1399 IN PCI_IO_DEVICE *Bridge\r
1400 )\r
ead42efc 1401{\r
1402 PCI_RESOURCE_NODE *IoBridge;\r
1403 PCI_RESOURCE_NODE *Mem32Bridge;\r
1404 PCI_RESOURCE_NODE *PMem32Bridge;\r
1405 PCI_RESOURCE_NODE *Mem64Bridge;\r
1406 PCI_RESOURCE_NODE *PMem64Bridge;\r
1407 UINT64 IoBase;\r
1408 UINT64 Mem32Base;\r
1409 UINT64 PMem32Base;\r
1410 UINT64 Mem64Base;\r
1411 UINT64 PMem64Base;\r
1412 EFI_STATUS Status;\r
1413\r
1414 IoBridge = CreateResourceNode (\r
1415 Bridge,\r
1416 0,\r
1417 0xFFF,\r
1418 0,\r
1419 PciBarTypeIo16,\r
1420 PciResUsageTypical\r
1421 );\r
1422\r
1423 Mem32Bridge = CreateResourceNode (\r
1424 Bridge,\r
1425 0,\r
1426 0xFFFFF,\r
1427 0,\r
1428 PciBarTypeMem32,\r
1429 PciResUsageTypical\r
1430 );\r
1431\r
1432 PMem32Bridge = CreateResourceNode (\r
1433 Bridge,\r
1434 0,\r
1435 0xFFFFF,\r
1436 0,\r
1437 PciBarTypePMem32,\r
1438 PciResUsageTypical\r
1439 );\r
1440\r
1441 Mem64Bridge = CreateResourceNode (\r
1442 Bridge,\r
1443 0,\r
1444 0xFFFFF,\r
1445 0,\r
1446 PciBarTypeMem64,\r
1447 PciResUsageTypical\r
1448 );\r
1449\r
1450 PMem64Bridge = CreateResourceNode (\r
1451 Bridge,\r
1452 0,\r
1453 0xFFFFF,\r
1454 0,\r
1455 PciBarTypePMem64,\r
1456 PciResUsageTypical\r
1457 );\r
1458\r
1459 //\r
1460 // Create resourcemap by going through all the devices subject to this root bridge\r
1461 //\r
1462 Status = CreateResourceMap (\r
1463 Bridge,\r
1464 IoBridge,\r
1465 Mem32Bridge,\r
1466 PMem32Bridge,\r
1467 Mem64Bridge,\r
1468 PMem64Bridge\r
1469 );\r
1470\r
1471 if (EFI_ERROR (Status)) {\r
1472 return Status;\r
1473 }\r
1474\r
1475 Status = GetResourceBaseFromBridge (\r
1476 Bridge,\r
1477 &IoBase,\r
1478 &Mem32Base,\r
1479 &PMem32Base,\r
1480 &Mem64Base,\r
1481 &PMem64Base\r
1482 );\r
1483\r
1484 if (EFI_ERROR (Status)) {\r
1485 return Status;\r
1486 }\r
1487\r
1488 //\r
1489 // Program IO resources\r
1490 //\r
1491 ProgramResource (\r
1492 IoBase,\r
1493 IoBridge\r
1494 );\r
1495\r
1496 //\r
1497 // Program Mem32 resources\r
1498 //\r
1499 ProgramResource (\r
1500 Mem32Base,\r
1501 Mem32Bridge\r
1502 );\r
1503\r
1504 //\r
1505 // Program PMem32 resources\r
1506 //\r
1507 ProgramResource (\r
1508 PMem32Base,\r
1509 PMem32Bridge\r
1510 );\r
1511\r
1512 //\r
1513 // Program Mem64 resources\r
1514 //\r
1515 ProgramResource (\r
1516 Mem64Base,\r
1517 Mem64Bridge\r
1518 );\r
1519\r
1520 //\r
1521 // Program PMem64 resources\r
1522 //\r
1523 ProgramResource (\r
1524 PMem64Base,\r
1525 PMem64Bridge\r
1526 );\r
1527\r
1528 DestroyResourceTree (IoBridge);\r
1529 DestroyResourceTree (Mem32Bridge);\r
1530 DestroyResourceTree (PMem32Bridge);\r
1531 DestroyResourceTree (PMem64Bridge);\r
1532 DestroyResourceTree (Mem64Bridge);\r
1533\r
1534 gBS->FreePool (IoBridge);\r
1535 gBS->FreePool (Mem32Bridge);\r
1536 gBS->FreePool (PMem32Bridge);\r
1537 gBS->FreePool (PMem64Bridge);\r
1538 gBS->FreePool (Mem64Bridge);\r
1539\r
1540 return EFI_SUCCESS;\r
1541}\r
1542\r
a3b8e257 1543/**\r
1544 Get resource base address for a pci bridge device\r
1545 \r
97404058 1546 @param Bridge Given Pci driver instance.\r
1547 @param IoBase output for base address of I/O type resource.\r
1548 @param Mem32Base output for base address of 32-bit memory type resource.\r
1549 @param PMem32Base output for base address of 32-bit Pmemory type resource.\r
1550 @param Mem64Base output for base address of 64-bit memory type resource.\r
1551 @param PMem64Base output for base address of 64-bit Pmemory type resource.\r
a3b8e257 1552 \r
97404058 1553 @retval EFI_SUCCESS Succes to get resource base address.\r
a3b8e257 1554**/\r
ead42efc 1555EFI_STATUS\r
1556GetResourceBaseFromBridge (\r
1557 IN PCI_IO_DEVICE *Bridge,\r
1558 OUT UINT64 *IoBase,\r
1559 OUT UINT64 *Mem32Base,\r
1560 OUT UINT64 *PMem32Base,\r
1561 OUT UINT64 *Mem64Base,\r
1562 OUT UINT64 *PMem64Base\r
1563 )\r
ead42efc 1564{\r
1565 if (!Bridge->Allocated) {\r
1566 return EFI_OUT_OF_RESOURCES;\r
1567 }\r
1568\r
1569 *IoBase = gAllOne;\r
1570 *Mem32Base = gAllOne;\r
1571 *PMem32Base = gAllOne;\r
1572 *Mem64Base = gAllOne;\r
1573 *PMem64Base = gAllOne;\r
1574\r
1575 if (IS_PCI_BRIDGE (&Bridge->Pci)) {\r
1576\r
97404058 1577 if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {\r
ead42efc 1578 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;\r
1579 }\r
1580\r
97404058 1581 if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {\r
ead42efc 1582 *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;\r
1583 }\r
1584\r
97404058 1585 if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {\r
ead42efc 1586 *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;\r
1587 }\r
1588\r
97404058 1589 if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {\r
ead42efc 1590 *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;\r
1591 } else {\r
1592 *PMem64Base = gAllOne;\r
1593 }\r
1594\r
1595 }\r
1596\r
1597 if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {\r
97404058 1598 if (Bridge->PciBar[P2C_IO_1].Length > 0) {\r
ead42efc 1599 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;\r
1600 } else {\r
97404058 1601 if (Bridge->PciBar[P2C_IO_2].Length > 0) {\r
ead42efc 1602 *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;\r
1603 }\r
1604 }\r
1605\r
97404058 1606 if (Bridge->PciBar[P2C_MEM_1].Length > 0) {\r
ead42efc 1607 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {\r
1608 *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1609 }\r
1610\r
1611 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {\r
1612 *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;\r
1613 }\r
1614 }\r
1615\r
97404058 1616 if (Bridge->PciBar[P2C_MEM_2].Length > 0) {\r
ead42efc 1617 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {\r
1618 *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1619 }\r
1620\r
1621 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {\r
1622 *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;\r
1623 }\r
1624 }\r
1625 }\r
1626\r
1627 return EFI_SUCCESS;\r
1628}\r
1629\r
a3b8e257 1630/**\r
1631 These are the notifications from the PCI bus driver that it is about to enter a certain \r
1632 phase of the PCI enumeration process.\r
1633\r
1634 This member function can be used to notify the host bridge driver to perform specific actions,\r
1635 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
1636 Eight notification points are defined at this time. See belows:\r
1637 EfiPciHostBridgeBeginEnumeration - Resets the host bridge PCI apertures and internal data\r
1638 structures. The PCI enumerator should issue this notification\r
1639 before starting a fresh enumeration process. Enumeration cannot\r
1640 be restarted after sending any other notification such as\r
1641 EfiPciHostBridgeBeginBusAllocation.\r
1642 EfiPciHostBridgeBeginBusAllocation - The bus allocation phase is about to begin. No specific action is\r
1643 required here. This notification can be used to perform any\r
1644 chipset-specific programming.\r
1645 EfiPciHostBridgeEndBusAllocation - The bus allocation and bus programming phase is complete. No\r
1646 specific action is required here. This notification can be used to\r
1647 perform any chipset-specific programming.\r
1648 EfiPciHostBridgeBeginResourceAllocation - The resource allocation phase is about to begin. No specific\r
1649 action is required here. This notification can be used to perform\r
1650 any chipset-specific programming.\r
1651 EfiPciHostBridgeAllocateResources - Allocates resources per previously submitted requests for all the PCI\r
1652 root bridges. These resource settings are returned on the next call to\r
1653 GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
1654 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible for gathering I/O and memory requests for\r
1655 all the PCI root bridges and submitting these requests using\r
1656 SubmitResources(). This function pads the resource amount\r
1657 to suit the root bridge hardware, takes care of dependencies between\r
1658 the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
1659 with the allocation request. In the case of padding, the allocated range\r
1660 could be bigger than what was requested.\r
1661 EfiPciHostBridgeSetResources - Programs the host bridge hardware to decode previously allocated\r
1662 resources (proposed resources) for all the PCI root bridges. After the\r
1663 hardware is programmed, reassigning resources will not be supported.\r
1664 The bus settings are not affected.\r
1665 EfiPciHostBridgeFreeResources - Deallocates resources that were previously allocated for all the PCI\r
1666 root bridges and resets the I/O and memory apertures to their initial\r
1667 state. The bus settings are not affected. If the request to allocate\r
1668 resources fails, the PCI enumerator can use this notification to\r
1669 deallocate previous resources, adjust the requests, and retry\r
1670 allocation.\r
1671 EfiPciHostBridgeEndResourceAllocation- The resource allocation phase is completed. No specific action is\r
1672 required here. This notification can be used to perform any chipsetspecific\r
1673 programming.\r
1674 \r
97404058 1675 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
a3b8e257 1676 @param[in] Phase The phase during enumeration\r
1677 \r
1678 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
1679 is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
1680 SubmitResources() has not been called for one or more\r
1681 PCI root bridges before this call\r
1682 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
1683 for a Phase of EfiPciHostBridgeSetResources.\r
1684 @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
1685 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1686 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
1687 previously submitted resource requests cannot be fulfilled or\r
1688 were only partially fulfilled.\r
1689 @retval EFI_SUCCESS The notification was accepted without any errors.\r
1690\r
1691**/\r
ead42efc 1692EFI_STATUS\r
1693NotifyPhase (\r
1694 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r
1695 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
1696 )\r
ead42efc 1697{\r
1698 EFI_HANDLE HostBridgeHandle;\r
1699 EFI_HANDLE RootBridgeHandle;\r
1700 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
1701 EFI_STATUS Status;\r
1702\r
1703 HostBridgeHandle = NULL;\r
1704 RootBridgeHandle = NULL;\r
1705 if (gPciPlatformProtocol != NULL) {\r
1706 //\r
1707 // Get Host Bridge Handle.\r
1708 //\r
1709 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);\r
1710\r
1711 //\r
1712 // Get the rootbridge Io protocol to find the host bridge handle\r
1713 //\r
1714 Status = gBS->HandleProtocol (\r
1715 RootBridgeHandle,\r
1716 &gEfiPciRootBridgeIoProtocolGuid,\r
1717 (VOID **) &PciRootBridgeIo\r
1718 );\r
1719\r
1720 if (EFI_ERROR (Status)) {\r
1721 return EFI_NOT_FOUND;\r
1722 }\r
1723\r
1724 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
1725\r
1726 //\r
1727 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1728 //\r
1729 gPciPlatformProtocol->PhaseNotify (\r
1730 gPciPlatformProtocol,\r
1731 HostBridgeHandle,\r
1732 Phase,\r
1733 ChipsetEntry\r
1734 );\r
1735 }\r
1736\r
1737 Status = PciResAlloc->NotifyPhase (\r
1738 PciResAlloc,\r
1739 Phase\r
1740 );\r
1741\r
1742 if (gPciPlatformProtocol != NULL) {\r
1743 //\r
1744 // Call PlatformPci::PhaseNotify() if the protocol is present.\r
1745 //\r
1746 gPciPlatformProtocol->PhaseNotify (\r
1747 gPciPlatformProtocol,\r
1748 HostBridgeHandle,\r
1749 Phase,\r
1750 ChipsetExit\r
1751 );\r
1752\r
1753 }\r
1754\r
1755 return EFI_SUCCESS;\r
1756}\r
1757\r
a3b8e257 1758/**\r
1759 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
1760 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
1761 PCI controllers before enumeration.\r
1762\r
1763 This function is called during the PCI enumeration process. No specific action is expected from this\r
1764 member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
1765 enumeration.\r
1766\r
eeefcb9d 1767 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
1768 @param Bus The bus number of the pci device. \r
1769 @param Device The device number of the pci device. \r
1770 @param Func The function number of the pci device. \r
a3b8e257 1771 @param Phase The phase of the PCI device enumeration. \r
1772 \r
1773 @retval EFI_SUCCESS The requested parameters were returned.\r
1774 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
1775 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
1776 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
1777 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
1778 not enumerate this device, including its child devices if it is a PCI-to-PCI\r
1779 bridge.\r
1780\r
1781**/\r
ead42efc 1782EFI_STATUS\r
1783PreprocessController (\r
1784 IN PCI_IO_DEVICE *Bridge,\r
1785 IN UINT8 Bus,\r
1786 IN UINT8 Device,\r
1787 IN UINT8 Func,\r
1788 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
1789 )\r
ead42efc 1790{\r
1791 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;\r
1792 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
1793 EFI_HANDLE RootBridgeHandle;\r
1794 EFI_HANDLE HostBridgeHandle;\r
1795 EFI_STATUS Status;\r
1796\r
1797 //\r
1798 // Get the host bridge handle\r
1799 //\r
1800 HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;\r
1801\r
1802 //\r
1803 // Get the pci host bridge resource allocation protocol\r
1804 //\r
1805 Status = gBS->OpenProtocol (\r
1806 HostBridgeHandle,\r
1807 &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
1808 (VOID **) &PciResAlloc,\r
1809 NULL,\r
1810 NULL,\r
1811 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
1812 );\r
1813\r
1814 if (EFI_ERROR (Status)) {\r
1815 return EFI_UNSUPPORTED;\r
1816 }\r
1817\r
1818 //\r
1819 // Get Root Brige Handle\r
1820 //\r
97404058 1821 while (Bridge->Parent != NULL) {\r
ead42efc 1822 Bridge = Bridge->Parent;\r
1823 }\r
1824\r
1825 RootBridgeHandle = Bridge->Handle;\r
1826\r
1827 RootBridgePciAddress.Register = 0;\r
1828 RootBridgePciAddress.Function = Func;\r
1829 RootBridgePciAddress.Device = Device;\r
1830 RootBridgePciAddress.Bus = Bus;\r
1831 RootBridgePciAddress.ExtendedRegister = 0;\r
1832\r
1833 if (gPciPlatformProtocol != NULL) {\r
1834 //\r
1835 // Call PlatformPci::PrepController() if the protocol is present.\r
1836 //\r
1837 gPciPlatformProtocol->PlatformPrepController (\r
1838 gPciPlatformProtocol,\r
1839 HostBridgeHandle,\r
1840 RootBridgeHandle,\r
1841 RootBridgePciAddress,\r
1842 Phase,\r
1843 ChipsetEntry\r
1844 );\r
1845 }\r
1846\r
1847 Status = PciResAlloc->PreprocessController (\r
1848 PciResAlloc,\r
1849 RootBridgeHandle,\r
1850 RootBridgePciAddress,\r
1851 Phase\r
1852 );\r
1853\r
1854 if (gPciPlatformProtocol != NULL) {\r
1855 //\r
1856 // Call PlatformPci::PrepController() if the protocol is present.\r
1857 //\r
1858 gPciPlatformProtocol->PlatformPrepController (\r
1859 gPciPlatformProtocol,\r
1860 HostBridgeHandle,\r
1861 RootBridgeHandle,\r
1862 RootBridgePciAddress,\r
1863 Phase,\r
1864 ChipsetExit\r
1865 );\r
1866 }\r
1867\r
1868 return EFI_SUCCESS;\r
1869}\r
1870\r
a3b8e257 1871/**\r
1872 Hot plug request notify.\r
1873 \r
1874 @param This - A pointer to the hot plug request protocol.\r
1875 @param Operation - The operation.\r
1876 @param Controller - A pointer to the controller.\r
eeefcb9d 1877 @param RemainingDevicePath - A pointer to the device path.\r
a3b8e257 1878 @param NumberOfChildren - A the number of child handle in the ChildHandleBuffer.\r
1879 @param ChildHandleBuffer - A pointer to the array contain the child handle.\r
1880 \r
97404058 1881 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r
1882 @retval EFI_SUCCESS Success operating.\r
a3b8e257 1883**/\r
ead42efc 1884EFI_STATUS\r
1885EFIAPI\r
1886PciHotPlugRequestNotify (\r
1887 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,\r
1888 IN EFI_PCI_HOTPLUG_OPERATION Operation,\r
1889 IN EFI_HANDLE Controller,\r
1890 IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,\r
1891 IN OUT UINT8 *NumberOfChildren,\r
1892 IN OUT EFI_HANDLE * ChildHandleBuffer\r
1893 )\r
ead42efc 1894{\r
1895 PCI_IO_DEVICE *Bridge;\r
1896 PCI_IO_DEVICE *Temp;\r
1897 EFI_PCI_IO_PROTOCOL *PciIo;\r
1898 UINTN Index;\r
1899 EFI_HANDLE RootBridgeHandle;\r
1900 EFI_STATUS Status;\r
1901\r
1902 Status = gBS->OpenProtocol (\r
1903 Controller,\r
1904 &gEfiPciIoProtocolGuid,\r
1905 (VOID **) &PciIo,\r
1906 gPciBusDriverBinding.DriverBindingHandle,\r
1907 Controller,\r
1908 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
1909 );\r
1910\r
1911 if (EFI_ERROR (Status)) {\r
1912 return EFI_NOT_FOUND;\r
1913 }\r
1914\r
1915 Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
1916\r
1917 //\r
1918 // Get root bridge handle\r
1919 //\r
1920 Temp = Bridge;\r
97404058 1921 while (Temp->Parent != NULL) {\r
ead42efc 1922 Temp = Temp->Parent;\r
1923 }\r
1924\r
1925 RootBridgeHandle = Temp->Handle;\r
1926\r
1927 if (Operation == EfiPciHotPlugRequestAdd) {\r
1928\r
1929 if (NumberOfChildren != NULL) {\r
1930 *NumberOfChildren = 0;\r
1931 }\r
1932\r
1933 if (IsListEmpty (&Bridge->ChildList)) {\r
1934\r
1935 Status = PciBridgeEnumerator (Bridge);\r
1936\r
1937 if (EFI_ERROR (Status)) {\r
1938 return Status;\r
1939 }\r
1940 }\r
1941\r
1942 Status = StartPciDevicesOnBridge (\r
1943 RootBridgeHandle,\r
1944 Bridge,\r
1945 RemainingDevicePath,\r
1946 NumberOfChildren,\r
1947 ChildHandleBuffer\r
1948 );\r
1949\r
1950 return EFI_SUCCESS;\r
1951 }\r
1952\r
1953 if (Operation == EfiPciHotplugRequestRemove) {\r
1954\r
1955 if (*NumberOfChildren == 0) {\r
1956 //\r
1957 // Remove all devices on the bridge\r
1958 //\r
1959 Status = RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);\r
1960 return Status;\r
1961\r
1962 }\r
1963\r
1964 for (Index = 0; Index < *NumberOfChildren; Index++) {\r
1965 //\r
1966 // De register all the pci device\r
1967 //\r
1968 Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);\r
1969\r
1970 if (EFI_ERROR (Status)) {\r
1971 return Status;\r
1972 }\r
1973\r
1974 }\r
1975 //\r
1976 // End for\r
1977 //\r
1978 return EFI_SUCCESS;\r
1979 }\r
1980\r
1981 return EFI_SUCCESS;\r
1982}\r
1983\r
a3b8e257 1984/**\r
1985 Search hostbridge according to given handle\r
1986 \r
eeefcb9d 1987 @param RootBridgeHandle - Host bridge handle.\r
1988\r
1989 @return TRUE Found.\r
1990 @return FALSE Not found.\r
a3b8e257 1991**/\r
ead42efc 1992BOOLEAN\r
1993SearchHostBridgeHandle (\r
1994 IN EFI_HANDLE RootBridgeHandle\r
1995 )\r
ead42efc 1996{\r
1997 EFI_HANDLE HostBridgeHandle;\r
1998 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
1999 UINTN Index;\r
2000 EFI_STATUS Status;\r
2001\r
2002 //\r
2003 // Get the rootbridge Io protocol to find the host bridge handle\r
2004 //\r
2005 Status = gBS->OpenProtocol (\r
2006 RootBridgeHandle,\r
2007 &gEfiPciRootBridgeIoProtocolGuid,\r
2008 (VOID **) &PciRootBridgeIo,\r
2009 gPciBusDriverBinding.DriverBindingHandle,\r
2010 RootBridgeHandle,\r
2011 EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
2012 );\r
2013\r
2014 if (EFI_ERROR (Status)) {\r
2015 return FALSE;\r
2016 }\r
2017\r
2018 HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
2019 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2020 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2021 return TRUE;\r
2022 }\r
2023 }\r
2024\r
2025 return FALSE;\r
2026}\r
2027\r
a3b8e257 2028/**\r
2029 Add host bridge handle to global variable for enumating.\r
2030 \r
97404058 2031 @param HostBridgeHandle host bridge handle.\r
a3b8e257 2032**/\r
ead42efc 2033EFI_STATUS\r
2034AddHostBridgeEnumerator (\r
2035 IN EFI_HANDLE HostBridgeHandle\r
2036 )\r
ead42efc 2037{\r
2038 UINTN Index;\r
2039\r
97404058 2040 if (HostBridgeHandle == NULL) {\r
ead42efc 2041 return EFI_ABORTED;\r
2042 }\r
2043\r
2044 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {\r
2045 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {\r
2046 return EFI_ABORTED;\r
2047 }\r
2048 }\r
2049\r
2050 if (Index < PCI_MAX_HOST_BRIDGE_NUM) {\r
2051 gPciHostBrigeHandles[Index] = HostBridgeHandle;\r
2052 gPciHostBridgeNumber++;\r
2053 }\r
2054\r
2055 return EFI_SUCCESS;\r
2056}\r
a3b8e257 2057\r
EFI Development Kit II mirror for PVE