| 97404058 |
1 | /** @file\r |
| ead42efc |
2 | \r |
| 3 | Copyright (c) 2006, Intel Corporation \r |
| 4 | All rights reserved. This program and the accompanying materials \r |
| 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r |
| 7 | http://opensource.org/licenses/bsd-license.php \r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | \r |
| 3db51098 |
12 | **/\r |
| ead42efc |
13 | \r |
| ead42efc |
14 | \r |
| eeefcb9d |
15 | #ifndef _EFI_PCI_IO_PROTOCOL_H_\r |
| 16 | #define _EFI_PCI_IO_PROTOCOL_H_\r |
| ead42efc |
17 | \r |
| 57076f45 |
18 | /**\r |
| eeefcb9d |
19 | Initializes a PCI I/O Instance.\r |
| 57076f45 |
20 | \r |
| eeefcb9d |
21 | @param PciIoDevice Pci device instance.\r |
| 57076f45 |
22 | \r |
| 57076f45 |
23 | **/\r |
| 8e6b0dcb |
24 | VOID\r |
| ead42efc |
25 | InitializePciIoInstance (\r |
| 26 | PCI_IO_DEVICE *PciIoDevice\r |
| ed66e1bc |
27 | );\r |
| ead42efc |
28 | \r |
| 57076f45 |
29 | /**\r |
| 30 | Verifies access to a PCI Base Address Register (BAR)\r |
| 31 | \r |
| 32 | @param PciIoDevice Pci device instance\r |
| 33 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 34 | base address for the memory or I/O operation to perform. \r |
| 35 | @param Type Operation type could be memory or I/O\r |
| 36 | @param Width Signifies the width of the memory or I/O operations.\r |
| 37 | @param Count The number of memory or I/O operations to perform.\r |
| 38 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
| 39 | \r |
| 40 | @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r |
| 41 | @retval EFI_SUCCESS Success Operation.\r |
| 42 | **/\r |
| ead42efc |
43 | EFI_STATUS\r |
| 44 | PciIoVerifyBarAccess (\r |
| 45 | PCI_IO_DEVICE *PciIoDevice,\r |
| 46 | UINT8 BarIndex,\r |
| 47 | PCI_BAR_TYPE Type,\r |
| 48 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 49 | IN UINTN Count,\r |
| 50 | UINT64 *Offset\r |
| ed66e1bc |
51 | );\r |
| ead42efc |
52 | \r |
| 57076f45 |
53 | /**\r |
| 54 | Verifies access to a PCI Config Header\r |
| 55 | \r |
| 56 | @param PciIoDevice Pci device instance\r |
| 57 | @param Width Signifies the width of the memory or I/O operations.\r |
| 58 | @param Count The number of memory or I/O operations to perform.\r |
| 59 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
| 60 | \r |
| 97404058 |
61 | @retval EFI_INVALID_PARAMETER Invalid Width.\r |
| 62 | @retval EFI_UNSUPPORTED Offset overflow.\r |
| 63 | @retval EFI_SUCCESS Success operation.\r |
| 57076f45 |
64 | **/\r |
| ead42efc |
65 | EFI_STATUS\r |
| 66 | PciIoVerifyConfigAccess (\r |
| 67 | PCI_IO_DEVICE *PciIoDevice,\r |
| 68 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 69 | IN UINTN Count,\r |
| 70 | IN UINT64 *Offset\r |
| ed66e1bc |
71 | );\r |
| ead42efc |
72 | \r |
| 57076f45 |
73 | /**\r |
| 74 | Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r |
| 75 | satisfied or after a defined duration.\r |
| 76 | \r |
| 77 | @param This Pointer to protocol instance of EFI_PCI_IO_PROTOCOL\r |
| 78 | @param Width Signifies the width of the memory or I/O operations.\r |
| 79 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 80 | base address for the memory or I/O operation to perform. \r |
| 81 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
| 82 | @param Mask Mask used for the polling criteria.\r |
| 83 | @param Value The comparison value used for the polling exit criteria.\r |
| 84 | @param Delay The number of 100 ns units to poll.\r |
| 85 | @param Result Pointer to the last value read from the memory location.\r |
| 86 | \r |
| 87 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r |
| 88 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r |
| 89 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 90 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 91 | **/\r |
| ead42efc |
92 | EFI_STATUS\r |
| 93 | EFIAPI\r |
| 94 | PciIoPollMem (\r |
| 95 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 96 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 97 | IN UINT8 BarIndex,\r |
| 98 | IN UINT64 Offset,\r |
| 99 | IN UINT64 Mask,\r |
| 100 | IN UINT64 Value,\r |
| 101 | IN UINT64 Delay,\r |
| 102 | OUT UINT64 *Result\r |
| ed66e1bc |
103 | );\r |
| ead42efc |
104 | \r |
| 57076f45 |
105 | /** \r |
| 106 | Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r |
| 107 | satisfied or after a defined duration.\r |
| 108 | \r |
| 109 | @param This A pointer to the EFI_PCI_IO_PROTOCOL.\r |
| 110 | @param Width Signifies the width of the memory or I/O operations.\r |
| eeefcb9d |
111 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 112 | base address for the memory or I/O operation to perform. \r |
| 113 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r |
| 57076f45 |
114 | @param Mask Mask used for the polling criteria.\r |
| 115 | @param Value The comparison value used for the polling exit criteria.\r |
| 116 | @param Delay The number of 100 ns units to poll.\r |
| 117 | @param Result Pointer to the last value read from the memory location.\r |
| 118 | \r |
| 119 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r |
| 120 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r |
| 121 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 122 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 123 | \r |
| 124 | **/\r |
| ead42efc |
125 | EFI_STATUS\r |
| 126 | EFIAPI\r |
| 127 | PciIoPollIo (\r |
| 128 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 129 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 130 | IN UINT8 BarIndex,\r |
| 131 | IN UINT64 Offset,\r |
| 132 | IN UINT64 Mask,\r |
| 133 | IN UINT64 Value,\r |
| 134 | IN UINT64 Delay,\r |
| 135 | OUT UINT64 *Result\r |
| ed66e1bc |
136 | );\r |
| ead42efc |
137 | \r |
| 57076f45 |
138 | /** \r |
| 139 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r |
| 140 | \r |
| 141 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
| 142 | @param Width Signifies the width of the memory or I/O operations.\r |
| 143 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 144 | base address for the memory or I/O operation to perform. \r |
| 145 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r |
| 146 | @param Count The number of memory or I/O operations to perform.\r |
| 147 | @param Buffer For read operations, the destination buffer to store the results. For write\r |
| 148 | operations, the source buffer to write data from. \r |
| 149 | \r |
| 150 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
| 151 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r |
| 152 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r |
| 153 | valid for the PCI BAR specified by BarIndex. \r |
| 154 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 155 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 156 | \r |
| 157 | **/\r |
| ead42efc |
158 | EFI_STATUS\r |
| 159 | EFIAPI\r |
| 160 | PciIoMemRead (\r |
| 161 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 162 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 163 | IN UINT8 BarIndex,\r |
| 164 | IN UINT64 Offset,\r |
| 165 | IN UINTN Count,\r |
| 166 | IN OUT VOID *Buffer\r |
| ed66e1bc |
167 | );\r |
| ead42efc |
168 | \r |
| 57076f45 |
169 | /** \r |
| 170 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r |
| 171 | \r |
| 172 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
| 173 | @param Width Signifies the width of the memory or I/O operations.\r |
| 174 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 175 | base address for the memory or I/O operation to perform. \r |
| 176 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r |
| 177 | @param Count The number of memory or I/O operations to perform.\r |
| 178 | @param Buffer For read operations, the destination buffer to store the results. For write\r |
| 179 | operations, the source buffer to write data from. \r |
| 180 | \r |
| 181 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
| 182 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r |
| 183 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r |
| 184 | valid for the PCI BAR specified by BarIndex. \r |
| 185 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 186 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 187 | \r |
| 188 | **/\r |
| ead42efc |
189 | EFI_STATUS\r |
| 190 | EFIAPI\r |
| 191 | PciIoMemWrite (\r |
| 192 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 193 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 194 | IN UINT8 BarIndex,\r |
| 195 | IN UINT64 Offset,\r |
| 196 | IN UINTN Count,\r |
| 197 | IN OUT VOID *Buffer\r |
| ed66e1bc |
198 | );\r |
| ead42efc |
199 | \r |
| 57076f45 |
200 | /** \r |
| 201 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r |
| 202 | \r |
| 203 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
| 204 | @param Width Signifies the width of the memory or I/O operations.\r |
| 205 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 206 | base address for the memory or I/O operation to perform. \r |
| 207 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r |
| 208 | @param Count The number of memory or I/O operations to perform.\r |
| 209 | @param Buffer For read operations, the destination buffer to store the results. For write\r |
| 210 | operations, the source buffer to write data from. \r |
| 211 | \r |
| 212 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
| 213 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r |
| 214 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r |
| 215 | valid for the PCI BAR specified by BarIndex. \r |
| 216 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 217 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 218 | \r |
| 219 | **/\r |
| ead42efc |
220 | EFI_STATUS\r |
| 221 | EFIAPI\r |
| 222 | PciIoIoRead (\r |
| 223 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 224 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 225 | IN UINT8 BarIndex,\r |
| 226 | IN UINT64 Offset,\r |
| 227 | IN UINTN Count,\r |
| 228 | IN OUT VOID *Buffer\r |
| ed66e1bc |
229 | );\r |
| ead42efc |
230 | \r |
| 57076f45 |
231 | /** \r |
| 232 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r |
| 233 | \r |
| 234 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
| 235 | @param Width Signifies the width of the memory or I/O operations.\r |
| 236 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 237 | base address for the memory or I/O operation to perform. \r |
| 238 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r |
| 239 | @param Count The number of memory or I/O operations to perform.\r |
| 240 | @param Buffer For read operations, the destination buffer to store the results. For write\r |
| 241 | operations, the source buffer to write data from. \r |
| 242 | \r |
| 243 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
| 244 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r |
| 245 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r |
| 246 | valid for the PCI BAR specified by BarIndex. \r |
| 247 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 248 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 249 | \r |
| 250 | **/\r |
| ead42efc |
251 | EFI_STATUS\r |
| 252 | EFIAPI\r |
| 253 | PciIoIoWrite (\r |
| 254 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 255 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 256 | IN UINT8 BarIndex,\r |
| 257 | IN UINT64 Offset,\r |
| 258 | IN UINTN Count,\r |
| 259 | IN OUT VOID *Buffer\r |
| ed66e1bc |
260 | );\r |
| ead42efc |
261 | \r |
| 57076f45 |
262 | /** \r |
| 263 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r |
| 264 | \r |
| 265 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 266 | @param Width Signifies the width of the memory operations.\r |
| 267 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
| 268 | @param Count The number of PCI configuration operations to perform.\r |
| 269 | @param Buffer For read operations, the destination buffer to store the results. For write\r |
| 270 | operations, the source buffer to write data from.\r |
| 271 | \r |
| 272 | \r |
| 273 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
| 274 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r |
| 275 | valid for the PCI configuration header of the PCI controller.\r |
| 276 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r |
| 277 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r |
| 278 | \r |
| 279 | **/\r |
| ead42efc |
280 | EFI_STATUS\r |
| 281 | EFIAPI\r |
| 282 | PciIoConfigRead (\r |
| 283 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 284 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 285 | IN UINT32 Offset,\r |
| 286 | IN UINTN Count,\r |
| 287 | IN OUT VOID *Buffer\r |
| ed66e1bc |
288 | );\r |
| ead42efc |
289 | \r |
| 57076f45 |
290 | /** \r |
| 291 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r |
| 292 | \r |
| 293 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 294 | @param Width Signifies the width of the memory operations.\r |
| 295 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
| 296 | @param Count The number of PCI configuration operations to perform.\r |
| 297 | @param Buffer For read operations, the destination buffer to store the results. For write\r |
| 298 | operations, the source buffer to write data from.\r |
| 299 | \r |
| 300 | \r |
| 301 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
| 302 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r |
| 303 | valid for the PCI configuration header of the PCI controller.\r |
| 304 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r |
| 305 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r |
| 306 | \r |
| 307 | **/\r |
| ead42efc |
308 | EFI_STATUS\r |
| 309 | EFIAPI\r |
| 310 | PciIoConfigWrite (\r |
| 311 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 312 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 313 | IN UINT32 Offset,\r |
| 314 | IN UINTN Count,\r |
| 315 | IN OUT VOID *Buffer\r |
| ed66e1bc |
316 | );\r |
| ead42efc |
317 | \r |
| 57076f45 |
318 | /** \r |
| 319 | Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r |
| 320 | memory space.\r |
| 321 | \r |
| 322 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
| 323 | @param Width Signifies the width of the memory operations.\r |
| 324 | @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r |
| 325 | base address for the memory operation to perform. \r |
| 326 | @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r |
| 327 | start the memory writes for the copy operation. \r |
| 328 | @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r |
| 329 | base address for the memory operation to perform. \r |
| 330 | @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r |
| 331 | the memory reads for the copy operation. \r |
| 332 | @param Count The number of memory operations to perform. Bytes moved is Width\r |
| 333 | size * Count, starting at DestOffset and SrcOffset. \r |
| 334 | \r |
| 335 | @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r |
| 336 | @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r |
| 337 | @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r |
| 338 | @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r |
| 339 | is not valid for the PCI BAR specified by DestBarIndex. \r |
| 340 | @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r |
| 341 | not valid for the PCI BAR specified by SrcBarIndex. \r |
| 342 | @retval EFI_INVALID_PARAMETER Width is invalid.\r |
| 343 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 344 | \r |
| 345 | **/\r |
| ead42efc |
346 | EFI_STATUS\r |
| 347 | EFIAPI\r |
| 348 | PciIoCopyMem (\r |
| 349 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 350 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
| 351 | IN UINT8 DestBarIndex,\r |
| 352 | IN UINT64 DestOffset,\r |
| 353 | IN UINT8 SrcBarIndex,\r |
| 354 | IN UINT64 SrcOffset,\r |
| 355 | IN UINTN Count\r |
| ed66e1bc |
356 | );\r |
| ead42efc |
357 | \r |
| 57076f45 |
358 | /** \r |
| 359 | Provides the PCI controller-Cspecific addresses needed to access system memory.\r |
| 360 | \r |
| 361 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
| 362 | @param Operation Indicates if the bus master is going to read or write to system memory.\r |
| 363 | @param HostAddress The system memory address to map to the PCI controller.\r |
| 364 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r |
| 365 | that were mapped. \r |
| 366 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r |
| 367 | access the hosts HostAddress. \r |
| 368 | @param Mapping A resulting value to pass to Unmap().\r |
| 369 | \r |
| 370 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r |
| 371 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r |
| 372 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 373 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
| 374 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r |
| 375 | \r |
| 376 | **/\r |
| ead42efc |
377 | EFI_STATUS\r |
| 378 | EFIAPI\r |
| 379 | PciIoMap (\r |
| 380 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 381 | IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r |
| 382 | IN VOID *HostAddress,\r |
| 383 | IN OUT UINTN *NumberOfBytes,\r |
| 384 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r |
| 385 | OUT VOID **Mapping\r |
| ed66e1bc |
386 | );\r |
| ead42efc |
387 | \r |
| 57076f45 |
388 | /** \r |
| 389 | Completes the Map() operation and releases any corresponding resources.\r |
| 390 | \r |
| 391 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 392 | @param Mapping The mapping value returned from Map().\r |
| 393 | \r |
| 394 | @retval EFI_SUCCESS The range was unmapped.\r |
| 395 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r |
| 396 | \r |
| 397 | **/\r |
| ead42efc |
398 | EFI_STATUS\r |
| 399 | EFIAPI\r |
| 400 | PciIoUnmap (\r |
| 401 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 402 | IN VOID *Mapping\r |
| ed66e1bc |
403 | );\r |
| ead42efc |
404 | \r |
| 57076f45 |
405 | /** \r |
| 406 | Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r |
| 407 | mapping. \r |
| 408 | \r |
| 409 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
| 410 | @param Type This parameter is not used and must be ignored.\r |
| 411 | @param MemoryType The type of memory to allocate, EfiBootServicesData or\r |
| 412 | EfiRuntimeServicesData. \r |
| 413 | @param Pages The number of pages to allocate. \r |
| 414 | @param HostAddress A pointer to store the base system memory address of the\r |
| 415 | allocated range. \r |
| 416 | @param Attributes The requested bit mask of attributes for the allocated range.\r |
| 417 | \r |
| 418 | @retval EFI_SUCCESS The requested memory pages were allocated.\r |
| 419 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r |
| 420 | MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r |
| 421 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
| 422 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r |
| 423 | \r |
| 424 | **/\r |
| ead42efc |
425 | EFI_STATUS\r |
| 426 | EFIAPI\r |
| 427 | PciIoAllocateBuffer (\r |
| 428 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 429 | IN EFI_ALLOCATE_TYPE Type,\r |
| 430 | IN EFI_MEMORY_TYPE MemoryType,\r |
| 431 | IN UINTN Pages,\r |
| 432 | OUT VOID **HostAddress,\r |
| 433 | IN UINT64 Attributes\r |
| ed66e1bc |
434 | );\r |
| ead42efc |
435 | \r |
| 57076f45 |
436 | /** \r |
| 437 | Frees memory that was allocated with AllocateBuffer().\r |
| 438 | \r |
| 439 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 440 | @param Pages The number of pages to free. \r |
| 441 | @param HostAddress The base system memory address of the allocated range. \r |
| 442 | \r |
| 443 | @retval EFI_SUCCESS The requested memory pages were freed.\r |
| 444 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r |
| 445 | was not allocated with AllocateBuffer().\r |
| 446 | \r |
| 447 | **/\r |
| ead42efc |
448 | EFI_STATUS\r |
| 449 | EFIAPI\r |
| 450 | PciIoFreeBuffer (\r |
| 451 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 452 | IN UINTN Pages,\r |
| 453 | IN VOID *HostAddress\r |
| ed66e1bc |
454 | );\r |
| ead42efc |
455 | \r |
| 57076f45 |
456 | /** \r |
| 457 | Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r |
| 458 | \r |
| 459 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 460 | \r |
| 461 | @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r |
| 462 | bridge to system memory. \r |
| 463 | @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r |
| 464 | host bridge due to a hardware error. \r |
| 465 | \r |
| 466 | **/\r |
| ead42efc |
467 | EFI_STATUS\r |
| 468 | EFIAPI\r |
| 469 | PciIoFlush (\r |
| 470 | IN EFI_PCI_IO_PROTOCOL *This\r |
| ed66e1bc |
471 | );\r |
| ead42efc |
472 | \r |
| 57076f45 |
473 | /** \r |
| 474 | Retrieves this PCI controller's current PCI bus number, device number, and function number.\r |
| 475 | \r |
| 476 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 477 | @param SegmentNumber The PCI controller's current PCI segment number.\r |
| 478 | @param BusNumber The PCI controller's current PCI bus number.\r |
| 479 | @param DeviceNumber The PCI controller's current PCI device number.\r |
| 480 | @param FunctionNumber The PCI controller's current PCI function number.\r |
| 481 | \r |
| 482 | @retval EFI_SUCCESS The PCI controller location was returned. \r |
| 483 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r |
| 484 | \r |
| 485 | **/\r |
| ead42efc |
486 | EFI_STATUS\r |
| 487 | EFIAPI\r |
| 488 | PciIoGetLocation (\r |
| 489 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 490 | OUT UINTN *Segment,\r |
| 491 | OUT UINTN *Bus,\r |
| 492 | OUT UINTN *Device,\r |
| 493 | OUT UINTN *Function\r |
| ed66e1bc |
494 | );\r |
| ead42efc |
495 | \r |
| 57076f45 |
496 | /**\r |
| 497 | Check BAR type for PCI resource.\r |
| 498 | \r |
| 499 | @param PciIoDevice PCI device instance\r |
| 500 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 501 | base address for the memory or I/O operation to perform. \r |
| 502 | @param BarType Memory or I/O\r |
| 503 | \r |
| 504 | @return whether Pci device's bar type is same with input BarType.\r |
| 505 | **/\r |
| ead42efc |
506 | BOOLEAN\r |
| 507 | CheckBarType (\r |
| 508 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 509 | UINT8 BarIndex,\r |
| 510 | PCI_BAR_TYPE BarType\r |
| ed66e1bc |
511 | );\r |
| ead42efc |
512 | \r |
| 57076f45 |
513 | /**\r |
| 514 | Set/Disable new attributes to a Root Bridge\r |
| 515 | \r |
| 516 | @param PciIoDevice Pci device instance\r |
| 517 | @param Attributes New attribute want to be set\r |
| 518 | @param Operation Set or Disable\r |
| 519 | \r |
| 520 | @retval EFI_UNSUPPORTED If root bridge does not support change attribute\r |
| 521 | @retval EFI_SUCCESS Success operation.\r |
| 522 | **/\r |
| ead42efc |
523 | EFI_STATUS\r |
| 524 | ModifyRootBridgeAttributes (\r |
| 525 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 526 | IN UINT64 Attributes,\r |
| 527 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r |
| ed66e1bc |
528 | );\r |
| ead42efc |
529 | \r |
| 57076f45 |
530 | /**\r |
| 531 | Check whether this device can be enable/disable to snoop\r |
| 532 | \r |
| 533 | @param PciIoDevice Pci device instance\r |
| 534 | @param Operation Enable/Disable\r |
| 535 | \r |
| 536 | @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop\r |
| 537 | @retval EFI_SUCCESS Snoop can be supported.\r |
| 538 | **/\r |
| ead42efc |
539 | EFI_STATUS\r |
| 540 | SupportPaletteSnoopAttributes (\r |
| 541 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 542 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r |
| ed66e1bc |
543 | );\r |
| ead42efc |
544 | \r |
| 57076f45 |
545 | /** \r |
| 546 | Performs an operation on the attributes that this PCI controller supports. The operations include\r |
| 547 | getting the set of supported attributes, retrieving the current attributes, setting the current \r |
| 548 | attributes, enabling attributes, and disabling attributes. \r |
| 549 | \r |
| 550 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 551 | @param Operation The operation to perform on the attributes for this PCI controller.\r |
| 552 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r |
| 553 | operations. \r |
| 554 | @param Result A pointer to the result mask of attributes that are returned for the Get\r |
| 555 | and Supported operations. \r |
| 556 | \r |
| 557 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r |
| 558 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r |
| 559 | @retval EFI_UNSUPPORTED one or more of the bits set in \r |
| 560 | Attributes are not supported by this PCI controller or one of\r |
| 561 | its parent bridges when Operation is Set, Enable or Disable.\r |
| 562 | \r |
| 563 | **/\r |
| ead42efc |
564 | EFI_STATUS\r |
| 565 | EFIAPI\r |
| 566 | PciIoAttributes (\r |
| 567 | IN EFI_PCI_IO_PROTOCOL * This,\r |
| 568 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r |
| 569 | IN UINT64 Attributes,\r |
| 570 | OUT UINT64 *Result OPTIONAL\r |
| ed66e1bc |
571 | );\r |
| ead42efc |
572 | \r |
| 57076f45 |
573 | /** \r |
| 574 | Gets the attributes that this PCI controller supports setting on a BAR using\r |
| 575 | SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r |
| 576 | \r |
| 577 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 578 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 579 | base address for resource range. The legal range for this field is 0..5.\r |
| 580 | @param Supports A pointer to the mask of attributes that this PCI controller supports\r |
| 581 | setting for this BAR with SetBarAttributes(). \r |
| 582 | @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r |
| 583 | configuration of this BAR of the PCI controller. \r |
| 584 | \r |
| 585 | @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r |
| 586 | controller supports are returned in Supports. If Resources \r |
| 587 | is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r |
| 588 | controller is currently using are returned in Resources. \r |
| 589 | @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r |
| 590 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r |
| 591 | @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r |
| 592 | Resources. \r |
| 593 | \r |
| 594 | **/\r |
| ead42efc |
595 | EFI_STATUS\r |
| 596 | EFIAPI\r |
| 597 | PciIoGetBarAttributes (\r |
| 598 | IN EFI_PCI_IO_PROTOCOL * This,\r |
| 599 | IN UINT8 BarIndex,\r |
| 600 | OUT UINT64 *Supports, OPTIONAL\r |
| 601 | OUT VOID **Resources OPTIONAL\r |
| ed66e1bc |
602 | );\r |
| ead42efc |
603 | \r |
| 57076f45 |
604 | /** \r |
| 605 | Sets the attributes for a range of a BAR on a PCI controller.\r |
| 606 | \r |
| 607 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r |
| 608 | @param Attributes The mask of attributes to set for the resource range specified by\r |
| 609 | BarIndex, Offset, and Length. \r |
| 610 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
| 611 | base address for resource range. The legal range for this field is 0..5.\r |
| 612 | @param Offset A pointer to the BAR relative base address of the resource range to be\r |
| 613 | modified by the attributes specified by Attributes. \r |
| 614 | @param Length A pointer to the length of the resource range to be modified by the\r |
| 615 | attributes specified by Attributes. \r |
| 616 | \r |
| 617 | @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r |
| 618 | range specified by BarIndex, Offset, and Length were \r |
| 619 | set on the PCI controller, and the actual resource range is returned\r |
| 620 | in Offset and Length. \r |
| 621 | @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r |
| 622 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r |
| 623 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r |
| 624 | resource range specified by BarIndex, Offset, and \r |
| 625 | Length. \r |
| 626 | \r |
| 627 | **/\r |
| ead42efc |
628 | EFI_STATUS\r |
| 629 | EFIAPI\r |
| 630 | PciIoSetBarAttributes (\r |
| 631 | IN EFI_PCI_IO_PROTOCOL *This,\r |
| 632 | IN UINT64 Attributes,\r |
| 633 | IN UINT8 BarIndex,\r |
| 634 | IN OUT UINT64 *Offset,\r |
| 635 | IN OUT UINT64 *Length\r |
| ed66e1bc |
636 | );\r |
| ead42efc |
637 | \r |
| 57076f45 |
638 | /**\r |
| 639 | Program parent bridge's attribute recurrently.\r |
| 640 | \r |
| 641 | @param PciIoDevice Child Pci device instance\r |
| 642 | @param Operation The operation to perform on the attributes for this PCI controller.\r |
| 643 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r |
| 644 | operations.\r |
| 645 | \r |
| 646 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r |
| 647 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r |
| 648 | @retval EFI_UNSUPPORTED one or more of the bits set in \r |
| 649 | Attributes are not supported by this PCI controller or one of\r |
| 650 | its parent bridges when Operation is Set, Enable or Disable.\r |
| 651 | \r |
| 652 | **/\r |
| ead42efc |
653 | EFI_STATUS\r |
| 654 | UpStreamBridgesAttributes (\r |
| 655 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 656 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r |
| 657 | IN UINT64 Attributes\r |
| ed66e1bc |
658 | );\r |
| ead42efc |
659 | \r |
| 57076f45 |
660 | /**\r |
| 661 | Test whether two Pci device has same parent bridge.\r |
| 662 | \r |
| 663 | @param PciDevice1 the frist pci device for testing\r |
| 664 | @param PciDevice2 the second pci device for testing\r |
| 665 | \r |
| 666 | @return whether two Pci device has same parent bridge.\r |
| 667 | **/\r |
| ead42efc |
668 | BOOLEAN\r |
| 669 | PciDevicesOnTheSamePath (\r |
| 670 | IN PCI_IO_DEVICE *PciDevice1,\r |
| 671 | IN PCI_IO_DEVICE *PciDevice2\r |
| ed66e1bc |
672 | );\r |
| ead42efc |
673 | \r |
| 674 | #endif\r |
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