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clean up the un-suitable ';' location when declaring the functions.
[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciLib.h
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3dbba770 1/** @file\r
ead42efc 2\r
3Copyright (c) 2006 - 2007, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12Module Name:\r
13\r
14 PciLib.h\r
15\r
16Abstract:\r
17\r
18 PCI Bus Driver Lib header file.\r
19 Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable\r
20 support hot plug.\r
21\r
22Revision History\r
23\r
3dbba770 24**/\r
ead42efc 25\r
26#ifndef _EFI_PCI_LIB_H\r
27#define _EFI_PCI_LIB_H\r
28\r
29//\r
30// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask\r
31//\r
32#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01\r
33#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02\r
34#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04\r
35#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08\r
36#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a\r
37\r
a43264f4 38typedef struct {\r
39 EFI_HANDLE Handle;\r
40} EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;\r
41\r
42typedef struct {\r
43 UINT32 Bar;\r
44 UINT16 DevicePathSize;\r
45 UINT16 ReqResSize;\r
46 UINT16 AllocResSize;\r
47 UINT8 *DevicePath;\r
48 UINT8 *ReqRes;\r
49 UINT8 *AllocRes;\r
50} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;\r
51\r
57076f45 52/**\r
53 Install protocol gEfiPciHotPlugRequestProtocolGuid\r
54 @param Status return status of protocol installation.\r
55**/\r
a43264f4 56void\r
ead42efc 57InstallHotPlugRequestProtocol (\r
58 IN EFI_STATUS *Status\r
ed66e1bc 59 );\r
ead42efc 60\r
57076f45 61/**\r
62 Install protocol gEfiPciHotplugDeviceGuid into hotplug device\r
63 instance\r
64 \r
65 @param PciIoDevice hotplug device instance\r
66 \r
67**/\r
ead42efc 68VOID\r
69InstallPciHotplugGuid (\r
70 IN PCI_IO_DEVICE *PciIoDevice\r
ed66e1bc 71 );\r
ead42efc 72\r
57076f45 73/**\r
74 UnInstall protocol gEfiPciHotplugDeviceGuid into hotplug device\r
75 instance\r
76 \r
77 @param PciIoDevice hotplug device instance\r
78 \r
79**/\r
ead42efc 80VOID\r
81UninstallPciHotplugGuid (\r
82 IN PCI_IO_DEVICE *PciIoDevice\r
ed66e1bc 83 );\r
ead42efc 84\r
57076f45 85/**\r
86 Retrieve the BAR information via PciIo interface\r
87 \r
88 @param PciIoDevice Pci device instance\r
89**/\r
ead42efc 90VOID\r
91GetBackPcCardBar (\r
92 IN PCI_IO_DEVICE *PciIoDevice\r
ed66e1bc 93 );\r
ead42efc 94\r
57076f45 95/**\r
96 Remove rejected pci device from specific root bridge\r
97 handle.\r
98 \r
99 @param RootBridgeHandle specific parent root bridge handle\r
100 @param Bridge Bridge device instance\r
101 \r
102 @retval EFI_SUCCESS Success operation.\r
103**/\r
ead42efc 104EFI_STATUS\r
105RemoveRejectedPciDevices (\r
106 EFI_HANDLE RootBridgeHandle,\r
107 IN PCI_IO_DEVICE *Bridge\r
ed66e1bc 108 );\r
ead42efc 109\r
57076f45 110/**\r
111 Wrapper function for allocating resource for pci host bridge.\r
112 \r
113 @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
114 \r
115**/\r
ead42efc 116EFI_STATUS\r
117PciHostBridgeResourceAllocator (\r
118 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
ed66e1bc 119 );\r
ead42efc 120\r
121EFI_STATUS\r
122PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
123 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
ed66e1bc 124 );\r
ead42efc 125\r
126EFI_STATUS\r
127PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
128 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
ed66e1bc 129 );\r
ead42efc 130\r
57076f45 131/**\r
132 Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r
133 Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug \r
134 \r
135 @param Bridge Bridge device instance\r
136 @param StartBusNumber start point\r
137 @param SubBusNumber Point to sub bus number\r
138 @param PaddedBusRange Customized bus number\r
139 \r
140 @retval EFI_SUCCESS Success\r
141 @retval EFI_DEVICE_ERROR Fail to scan bus\r
142**/\r
ead42efc 143EFI_STATUS\r
144PciScanBus (\r
145 IN PCI_IO_DEVICE *Bridge,\r
146 IN UINT8 StartBusNumber,\r
147 OUT UINT8 *SubBusNumber,\r
148 OUT UINT8 *PaddedBusRange\r
ed66e1bc 149 );\r
ead42efc 150\r
151EFI_STATUS\r
152PciScanBus_WithHotPlugDeviceSupport (\r
153 IN PCI_IO_DEVICE *Bridge,\r
154 IN UINT8 StartBusNumber,\r
155 OUT UINT8 *SubBusNumber,\r
156 OUT UINT8 *PaddedBusRange\r
ed66e1bc 157 );\r
ead42efc 158\r
159EFI_STATUS\r
160PciScanBus_WithoutHotPlugDeviceSupport (\r
161 IN PCI_IO_DEVICE *Bridge,\r
162 IN UINT8 StartBusNumber,\r
163 OUT UINT8 *SubBusNumber,\r
164 OUT UINT8 *PaddedBusRange\r
ed66e1bc 165 );\r
ead42efc 166\r
57076f45 167/**\r
168 Process Option Rom on this host bridge\r
169 \r
170 @param Bridge Pci bridge device instance\r
171 \r
172 @retval EFI_SUCCESS Success\r
173**/\r
174\r
ead42efc 175EFI_STATUS\r
176PciRootBridgeP2CProcess (\r
177 IN PCI_IO_DEVICE *Bridge\r
ed66e1bc 178 );\r
ead42efc 179\r
57076f45 180/**\r
181 Process Option Rom on this host bridge\r
182 \r
183 @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
184 \r
185 @retval EFI_NOT_FOUND Can not find the root bridge instance\r
186 @retval EFI_SUCCESS Success process\r
187**/\r
ead42efc 188EFI_STATUS\r
189PciHostBridgeP2CProcess (\r
190 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
ed66e1bc 191 );\r
ead42efc 192\r
57076f45 193/**\r
194 This function is used to enumerate the entire host bridge\r
195 in a given platform\r
ead42efc 196\r
57076f45 197 @param PciResAlloc A pointer to the resource allocate protocol.\r
ead42efc 198\r
57076f45 199 @retval EFI_OUT_OF_RESOURCES no enough resource\r
200 @retval EFI_SUCCESS Success\r
ead42efc 201\r
bcd70414 202**/\r
ead42efc 203\r
204EFI_STATUS\r
205PciHostBridgeEnumerator (\r
206 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
ed66e1bc 207 );\r
ead42efc 208\r
209/**\r
210 Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
211\r
212 @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
213 @param Width Signifies the width of the memory operations.\r
214 @Param Address The address within the PCI configuration space for the PCI controller.\r
215 @param Buffer For read operations, the destination buffer to store the results. For\r
216 write operations, the source buffer to write data from.\r
217\r
218 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
219 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
220 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
221 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
222\r
223**/\r
224EFI_STATUS\r
225PciIoRead (\r
226 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
227 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
228 IN UINT32 Address,\r
229 IN UINTN Count,\r
230 IN OUT VOID *Buffer\r
231 );\r
232\r
233/**\r
234 Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
235\r
236 @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
237 @param Width Signifies the width of the memory operations.\r
238 @Param Address The address within the PCI configuration space for the PCI controller.\r
239 @param Buffer For read operations, the destination buffer to store the results. For\r
240 write operations, the source buffer to write data from.\r
241\r
242 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
243 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
244 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
245 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
246\r
247**/\r
248EFI_STATUS\r
249PciIoWrite (\r
250 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
251 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
252 IN UINT32 Address,\r
253 IN UINTN Count,\r
254 IN OUT VOID *Buffer\r
255 );\r
256\r
257/**\r
258 Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
259\r
260 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
261 @param Pci A pointer to PCI_TYPE00.\r
262 @param Width Signifies the width of the memory operations.\r
263 @Param Address The address within the PCI configuration space for the PCI controller.\r
264 @param Buffer For read operations, the destination buffer to store the results. For\r
265 write operations, the source buffer to write data from.\r
266\r
267 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
268 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
269 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
270 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
271\r
272**/\r
273EFI_STATUS\r
274PciRootBridgeIoWrite (\r
275 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
276 IN PCI_TYPE00 *Pci,\r
277 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
278 IN UINT64 Address,\r
279 IN UINTN Count,\r
280 IN OUT VOID *Buffer\r
281 );\r
282\r
283/**\r
284 Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
285\r
286 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
287 @param Pci A pointer to PCI_TYPE00.\r
288 @param Width Signifies the width of the memory operations.\r
289 @Param Address The address within the PCI configuration space for the PCI controller.\r
290 @param Buffer For read operations, the destination buffer to store the results. For\r
291 write operations, the source buffer to write data from.\r
292\r
293 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
294 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
295 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
296 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
297\r
298**/\r
299EFI_STATUS\r
300PciRootBridgeIoRead (\r
301 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
302 IN PCI_TYPE00 *Pci,\r
303 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
304 IN UINT64 Address,\r
305 IN UINTN Count,\r
306 IN OUT VOID *Buffer\r
307 );\r
308#endif\r