[mirror_edk2.git] / IntelFrameworkModulePkg / Universal / CpuIoDxe / CpuIo.h

/** @file\r
  Internal include file of CPU I/O DXE Driver.\r
\r
  Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __CPU_IO_DXE_H__\r
#define __CPU_IO_DXE_H__\r
\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/CpuIo.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
#define MAX_IO_PORT_ADDRESS   0xFFFF\r
\r
/**\r
  Reads memory-mapped registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuMemoryServiceRead (\r
  IN  EFI_CPU_IO_PROTOCOL        *This,\r
  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                     Address,\r
  IN  UINTN                      Count,\r
  OUT VOID                       *Buffer\r
  );\r
\r
/**\r
  Writes memory-mapped registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuMemoryServiceWrite (\r
  IN EFI_CPU_IO_PROTOCOL        *This,\r
  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                     Address,\r
  IN UINTN                      Count,\r
  IN VOID                       *Buffer\r
  );\r
\r
/**\r
  Reads I/O registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuIoServiceRead (\r
  IN  EFI_CPU_IO_PROTOCOL        *This,\r
  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                     Address,\r
  IN  UINTN                      Count,\r
  OUT VOID                       *Buffer\r
  );\r
\r
/**\r
  Write I/O registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuIoServiceWrite (\r
  IN EFI_CPU_IO_PROTOCOL        *This,\r
  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                     Address,\r
  IN UINTN                      Count,\r
  IN VOID                       *Buffer\r
  );\r
\r
#endif\r
Commit	Line	Data
55a503bc	1	/** @file\r
	2	Internal include file of CPU I/O DXE Driver.\r
	3	\r
0a6f4824	4	Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>\r
180a5a35	5	This program and the accompanying materials\r
55a503bc	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __CPU_IO_DXE_H__\r
	16	#define __CPU_IO_DXE_H__\r
	17	\r
	18	\r
	19	#include <PiDxe.h>\r
	20	\r
	21	#include <Protocol/CpuIo.h>\r
	22	\r
	23	#include <Library/BaseLib.h>\r
	24	#include <Library/DebugLib.h>\r
	25	#include <Library/IoLib.h>\r
	26	#include <Library/UefiBootServicesTableLib.h>\r
	27	\r
	28	#define MAX_IO_PORT_ADDRESS 0xFFFF\r
	29	\r
	30	/**\r
	31	Reads memory-mapped registers.\r
	32	\r
0a6f4824 LG	33	The I/O operations are carried out exactly as requested. The caller is responsible\r
	34	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	35	platform might require. For example on some platforms, width requests of\r
	36	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	37	be handled by the driver.\r
0a6f4824 LG	38	\r
	39	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	40	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	41	each of the Count operations that is performed.\r
0a6f4824 LG	42	\r
	43	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	44	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	45	incremented for each of the Count operations that is performed. The read or\r
55a503bc	46	write operation is performed Count times on the same Address.\r
0a6f4824 LG	47	\r
	48	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	49	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	50	incremented for each of the Count operations that is performed. The read or\r
55a503bc	51	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	52	\r
55a503bc	53	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	54	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	55	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	56	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	57	bytes moved is Width size * Count, starting at Address.\r
	58	@param[out] Buffer For read operations, the destination buffer to store the results.\r
	59	For write operations, the source buffer from which to write data.\r
	60	\r
	61	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	62	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	63	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	64	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	65	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	66	and Count is not valid for this PI system.\r
	67	\r
	68	**/\r
	69	EFI_STATUS\r
	70	EFIAPI\r
	71	CpuMemoryServiceRead (\r
	72	IN EFI_CPU_IO_PROTOCOL *This,\r
	73	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	74	IN UINT64 Address,\r
	75	IN UINTN Count,\r
	76	OUT VOID *Buffer\r
	77	);\r
	78	\r
	79	/**\r
	80	Writes memory-mapped registers.\r
	81	\r
0a6f4824 LG	82	The I/O operations are carried out exactly as requested. The caller is responsible\r
	83	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	84	platform might require. For example on some platforms, width requests of\r
	85	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	86	be handled by the driver.\r
0a6f4824 LG	87	\r
	88	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	89	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	90	each of the Count operations that is performed.\r
0a6f4824 LG	91	\r
	92	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	93	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	94	incremented for each of the Count operations that is performed. The read or\r
55a503bc	95	write operation is performed Count times on the same Address.\r
0a6f4824 LG	96	\r
	97	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	98	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	99	incremented for each of the Count operations that is performed. The read or\r
55a503bc	100	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	101	\r
55a503bc	102	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	103	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	104	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	105	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	106	bytes moved is Width size * Count, starting at Address.\r
	107	@param[in] Buffer For read operations, the destination buffer to store the results.\r
	108	For write operations, the source buffer from which to write data.\r
	109	\r
	110	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	111	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	112	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	113	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	114	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	115	and Count is not valid for this PI system.\r
	116	\r
	117	**/\r
	118	EFI_STATUS\r
	119	EFIAPI\r
	120	CpuMemoryServiceWrite (\r
	121	IN EFI_CPU_IO_PROTOCOL *This,\r
	122	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	123	IN UINT64 Address,\r
	124	IN UINTN Count,\r
	125	IN VOID *Buffer\r
	126	);\r
	127	\r
	128	/**\r
	129	Reads I/O registers.\r
	130	\r
0a6f4824 LG	131	The I/O operations are carried out exactly as requested. The caller is responsible\r
	132	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	133	platform might require. For example on some platforms, width requests of\r
	134	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	135	be handled by the driver.\r
0a6f4824 LG	136	\r
	137	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	138	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	139	each of the Count operations that is performed.\r
0a6f4824 LG	140	\r
	141	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	142	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	143	incremented for each of the Count operations that is performed. The read or\r
55a503bc	144	write operation is performed Count times on the same Address.\r
0a6f4824 LG	145	\r
	146	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	147	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	148	incremented for each of the Count operations that is performed. The read or\r
55a503bc	149	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	150	\r
55a503bc	151	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	152	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	153	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	154	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	155	bytes moved is Width size * Count, starting at Address.\r
	156	@param[out] Buffer For read operations, the destination buffer to store the results.\r
	157	For write operations, the source buffer from which to write data.\r
	158	\r
	159	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	160	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	161	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	162	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	163	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	164	and Count is not valid for this PI system.\r
	165	\r
	166	**/\r
	167	EFI_STATUS\r
	168	EFIAPI\r
	169	CpuIoServiceRead (\r
	170	IN EFI_CPU_IO_PROTOCOL *This,\r
	171	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	172	IN UINT64 Address,\r
	173	IN UINTN Count,\r
	174	OUT VOID *Buffer\r
	175	);\r
	176	\r
	177	/**\r
	178	Write I/O registers.\r
	179	\r
0a6f4824 LG	180	The I/O operations are carried out exactly as requested. The caller is responsible\r
	181	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	182	platform might require. For example on some platforms, width requests of\r
	183	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	184	be handled by the driver.\r
0a6f4824 LG	185	\r
	186	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	187	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	188	each of the Count operations that is performed.\r
0a6f4824 LG	189	\r
	190	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	191	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	192	incremented for each of the Count operations that is performed. The read or\r
55a503bc	193	write operation is performed Count times on the same Address.\r
0a6f4824 LG	194	\r
	195	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	196	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	197	incremented for each of the Count operations that is performed. The read or\r
55a503bc	198	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	199	\r
55a503bc	200	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	201	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	202	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	203	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	204	bytes moved is Width size * Count, starting at Address.\r
	205	@param[in] Buffer For read operations, the destination buffer to store the results.\r
	206	For write operations, the source buffer from which to write data.\r
	207	\r
	208	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	209	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	210	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	211	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	212	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	213	and Count is not valid for this PI system.\r
0a6f4824	214	\r
55a503bc	215	**/\r
	216	EFI_STATUS\r
	217	EFIAPI\r
	218	CpuIoServiceWrite (\r
	219	IN EFI_CPU_IO_PROTOCOL *This,\r
	220	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	221	IN UINT64 Address,\r
	222	IN UINTN Count,\r
	223	IN VOID *Buffer\r
	224	);\r
	225	\r
	226	#endif\r