[mirror_edk2.git] / IntelFrameworkModulePkg / Universal / CpuIoDxe / CpuIo.h

/** @file\r
  Internal include file of CPU I/O DXE Driver.\r
\r
  Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __CPU_IO_DXE_H__\r
#define __CPU_IO_DXE_H__\r
\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/CpuIo.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
#define MAX_IO_PORT_ADDRESS   0xFFFF\r
\r
/**\r
  Reads memory-mapped registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuMemoryServiceRead (\r
  IN  EFI_CPU_IO_PROTOCOL        *This,\r
  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                     Address,\r
  IN  UINTN                      Count,\r
  OUT VOID                       *Buffer\r
  );\r
\r
/**\r
  Writes memory-mapped registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuMemoryServiceWrite (\r
  IN EFI_CPU_IO_PROTOCOL        *This,\r
  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                     Address,\r
  IN UINTN                      Count,\r
  IN VOID                       *Buffer\r
  );\r
\r
/**\r
  Reads I/O registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuIoServiceRead (\r
  IN  EFI_CPU_IO_PROTOCOL        *This,\r
  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                     Address,\r
  IN  UINTN                      Count,\r
  OUT VOID                       *Buffer\r
  );\r
\r
/**\r
  Write I/O registers.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
  each of the Count operations that is performed.\r
\r
  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times on the same Address.\r
\r
  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
  incremented for each of the Count operations that is performed. The read or\r
  write operation is performed Count times from the first element of Buffer.\r
\r
  @param[in]  This     A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
  @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
  @param[in]  Address  The base address of the I/O operation.\r
  @param[in]  Count    The number of I/O operations to perform. The number of\r
                       bytes moved is Width size * Count, starting at Address.\r
  @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                       For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The data was read from or written to the PI system.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
CpuIoServiceWrite (\r
  IN EFI_CPU_IO_PROTOCOL        *This,\r
  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                     Address,\r
  IN UINTN                      Count,\r
  IN VOID                       *Buffer\r
  );\r
\r
#endif\r
Commit	Line	Data
55a503bc	1	/** @file\r
	2	Internal include file of CPU I/O DXE Driver.\r
	3	\r
0a6f4824	4	Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>\r
c0a00b14	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
55a503bc	6	\r
	7	**/\r
	8	\r
	9	#ifndef __CPU_IO_DXE_H__\r
	10	#define __CPU_IO_DXE_H__\r
	11	\r
	12	\r
	13	#include <PiDxe.h>\r
	14	\r
	15	#include <Protocol/CpuIo.h>\r
	16	\r
	17	#include <Library/BaseLib.h>\r
	18	#include <Library/DebugLib.h>\r
	19	#include <Library/IoLib.h>\r
	20	#include <Library/UefiBootServicesTableLib.h>\r
	21	\r
	22	#define MAX_IO_PORT_ADDRESS 0xFFFF\r
	23	\r
	24	/**\r
	25	Reads memory-mapped registers.\r
	26	\r
0a6f4824 LG	27	The I/O operations are carried out exactly as requested. The caller is responsible\r
	28	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	29	platform might require. For example on some platforms, width requests of\r
	30	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	31	be handled by the driver.\r
0a6f4824 LG	32	\r
	33	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	34	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	35	each of the Count operations that is performed.\r
0a6f4824 LG	36	\r
	37	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	38	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	39	incremented for each of the Count operations that is performed. The read or\r
55a503bc	40	write operation is performed Count times on the same Address.\r
0a6f4824 LG	41	\r
	42	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	43	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	44	incremented for each of the Count operations that is performed. The read or\r
55a503bc	45	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	46	\r
55a503bc	47	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	48	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	49	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	50	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	51	bytes moved is Width size * Count, starting at Address.\r
	52	@param[out] Buffer For read operations, the destination buffer to store the results.\r
	53	For write operations, the source buffer from which to write data.\r
	54	\r
	55	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	56	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	57	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	58	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	59	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	60	and Count is not valid for this PI system.\r
	61	\r
	62	**/\r
	63	EFI_STATUS\r
	64	EFIAPI\r
	65	CpuMemoryServiceRead (\r
	66	IN EFI_CPU_IO_PROTOCOL *This,\r
	67	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	68	IN UINT64 Address,\r
	69	IN UINTN Count,\r
	70	OUT VOID *Buffer\r
	71	);\r
	72	\r
	73	/**\r
	74	Writes memory-mapped registers.\r
	75	\r
0a6f4824 LG	76	The I/O operations are carried out exactly as requested. The caller is responsible\r
	77	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	78	platform might require. For example on some platforms, width requests of\r
	79	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	80	be handled by the driver.\r
0a6f4824 LG	81	\r
	82	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	83	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	84	each of the Count operations that is performed.\r
0a6f4824 LG	85	\r
	86	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	87	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	88	incremented for each of the Count operations that is performed. The read or\r
55a503bc	89	write operation is performed Count times on the same Address.\r
0a6f4824 LG	90	\r
	91	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	92	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	93	incremented for each of the Count operations that is performed. The read or\r
55a503bc	94	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	95	\r
55a503bc	96	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	97	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	98	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	99	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	100	bytes moved is Width size * Count, starting at Address.\r
	101	@param[in] Buffer For read operations, the destination buffer to store the results.\r
	102	For write operations, the source buffer from which to write data.\r
	103	\r
	104	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	105	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	106	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	107	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	108	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	109	and Count is not valid for this PI system.\r
	110	\r
	111	**/\r
	112	EFI_STATUS\r
	113	EFIAPI\r
	114	CpuMemoryServiceWrite (\r
	115	IN EFI_CPU_IO_PROTOCOL *This,\r
	116	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	117	IN UINT64 Address,\r
	118	IN UINTN Count,\r
	119	IN VOID *Buffer\r
	120	);\r
	121	\r
	122	/**\r
	123	Reads I/O registers.\r
	124	\r
0a6f4824 LG	125	The I/O operations are carried out exactly as requested. The caller is responsible\r
	126	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	127	platform might require. For example on some platforms, width requests of\r
	128	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	129	be handled by the driver.\r
0a6f4824 LG	130	\r
	131	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	132	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	133	each of the Count operations that is performed.\r
0a6f4824 LG	134	\r
	135	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	136	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	137	incremented for each of the Count operations that is performed. The read or\r
55a503bc	138	write operation is performed Count times on the same Address.\r
0a6f4824 LG	139	\r
	140	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	141	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	142	incremented for each of the Count operations that is performed. The read or\r
55a503bc	143	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	144	\r
55a503bc	145	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	146	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	147	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	148	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	149	bytes moved is Width size * Count, starting at Address.\r
	150	@param[out] Buffer For read operations, the destination buffer to store the results.\r
	151	For write operations, the source buffer from which to write data.\r
	152	\r
	153	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	154	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	155	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	156	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	157	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	158	and Count is not valid for this PI system.\r
	159	\r
	160	**/\r
	161	EFI_STATUS\r
	162	EFIAPI\r
	163	CpuIoServiceRead (\r
	164	IN EFI_CPU_IO_PROTOCOL *This,\r
	165	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	166	IN UINT64 Address,\r
	167	IN UINTN Count,\r
	168	OUT VOID *Buffer\r
	169	);\r
	170	\r
	171	/**\r
	172	Write I/O registers.\r
	173	\r
0a6f4824 LG	174	The I/O operations are carried out exactly as requested. The caller is responsible\r
	175	for satisfying any alignment and I/O width restrictions that a PI System on a\r
	176	platform might require. For example on some platforms, width requests of\r
	177	EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
55a503bc	178	be handled by the driver.\r
0a6f4824 LG	179	\r
	180	If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
	181	or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
55a503bc	182	each of the Count operations that is performed.\r
0a6f4824 LG	183	\r
	184	If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
	185	EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
	186	incremented for each of the Count operations that is performed. The read or\r
55a503bc	187	write operation is performed Count times on the same Address.\r
0a6f4824 LG	188	\r
	189	If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
	190	EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
	191	incremented for each of the Count operations that is performed. The read or\r
55a503bc	192	write operation is performed Count times from the first element of Buffer.\r
0a6f4824	193	\r
55a503bc	194	@param[in] This A pointer to the EFI_CPU_IO_PROTOCOL instance.\r
55a503bc	195	@param[in] Width Signifies the width of the I/O or Memory operation.\r
0a6f4824 LG	196	@param[in] Address The base address of the I/O operation.\r
0a6f4824 LG	197	@param[in] Count The number of I/O operations to perform. The number of\r
55a503bc	198	bytes moved is Width size * Count, starting at Address.\r
	199	@param[in] Buffer For read operations, the destination buffer to store the results.\r
	200	For write operations, the source buffer from which to write data.\r
	201	\r
	202	@retval EFI_SUCCESS The data was read from or written to the PI system.\r
	203	@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
	204	@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
	205	@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
0a6f4824	206	@retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
55a503bc	207	and Count is not valid for this PI system.\r
0a6f4824	208	\r
55a503bc	209	**/\r
	210	EFI_STATUS\r
	211	EFIAPI\r
	212	CpuIoServiceWrite (\r
	213	IN EFI_CPU_IO_PROTOCOL *This,\r
	214	IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
	215	IN UINT64 Address,\r
	216	IN UINTN Count,\r
	217	IN VOID *Buffer\r
	218	);\r
	219	\r
	220	#endif\r