]>
Commit | Line | Data |
---|---|---|
79964ac8 | 1 | /** @file\r |
2 | I/O Library.\r | |
c4fa3eac | 3 | The implementation of I/O operation for this library instance \r |
4 | are based on EFI_CPU_IO_PROTOCOL.\r | |
5 | \r | |
79964ac8 | 6 | Copyright (c) 2006, Intel Corporation<BR>\r |
7 | All rights reserved. This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | Module Name: IoLib.c\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
694363f8 | 19 | \r |
79964ac8 | 20 | #include "DxeCpuIoLibInternal.h"\r |
21 | \r | |
22 | //\r | |
23 | // Globle varible to cache pointer to CpuIo protocol.\r | |
24 | //\r | |
25 | STATIC EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;\r | |
26 | STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r | |
27 | \r | |
28 | /**\r | |
29 | The constructor function caches the pointer to CpuIo protocol.\r | |
30 | \r | |
31 | The constructor function locates CpuIo protocol from protocol database.\r | |
32 | It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r | |
33 | \r | |
34 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
35 | @param SystemTable A pointer to the EFI System Table.\r | |
36 | \r | |
37 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r | |
38 | \r | |
39 | **/\r | |
40 | EFI_STATUS\r | |
41 | EFIAPI\r | |
42 | IoLibConstructor (\r | |
43 | IN EFI_HANDLE ImageHandle,\r | |
44 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
45 | )\r | |
46 | {\r | |
47 | EFI_STATUS Status;\r | |
48 | \r | |
856500d8 | 49 | Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID **) &mPciRootBridgeIo);\r |
79964ac8 | 50 | if (EFI_ERROR (Status)) {\r |
856500d8 | 51 | Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **) &mCpuIo);\r |
79964ac8 | 52 | }\r |
53 | ASSERT_EFI_ERROR (Status);\r | |
54 | \r | |
55 | return Status;\r | |
56 | }\r | |
57 | \r | |
58 | /**\r | |
59 | Reads registers in the EFI CPU I/O space.\r | |
60 | \r | |
61 | Reads the I/O port specified by Port with registers width specified by Width.\r | |
62 | The read value is returned. If such operations are not supported, then ASSERT().\r | |
63 | This function must guarantee that all I/O read and write operations are serialized.\r | |
64 | \r | |
65 | @param Port The base address of the I/O operation.\r | |
66 | The caller is responsible for aligning the Address if required.\r | |
67 | @param Width The width of the I/O operation.\r | |
68 | \r | |
69 | @return Data read from registers in the EFI CPU I/O space.\r | |
70 | \r | |
71 | **/\r | |
72 | UINT64\r | |
73 | EFIAPI\r | |
74 | IoReadWorker (\r | |
75 | IN UINTN Port,\r | |
76 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r | |
77 | )\r | |
78 | {\r | |
79 | EFI_STATUS Status;\r | |
80 | UINT64 Data;\r | |
81 | \r | |
82 | if (mPciRootBridgeIo != NULL) {\r | |
856500d8 | 83 | Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r |
79964ac8 | 84 | } else {\r |
85 | Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r | |
86 | }\r | |
87 | ASSERT_EFI_ERROR (Status);\r | |
88 | \r | |
89 | return Data;\r | |
90 | }\r | |
91 | \r | |
92 | /**\r | |
93 | Writes registers in the EFI CPU I/O space.\r | |
94 | \r | |
95 | Writes the I/O port specified by Port with registers width and value specified by Width\r | |
96 | and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r | |
97 | This function must guarantee that all I/O read and write operations are serialized.\r | |
98 | \r | |
99 | @param Port The base address of the I/O operation.\r | |
100 | The caller is responsible for aligning the Address if required.\r | |
101 | @param Width The width of the I/O operation.\r | |
102 | @param Data The value to write to the I/O port.\r | |
103 | \r | |
104 | @return The paramter of Data.\r | |
105 | \r | |
106 | **/\r | |
107 | UINT64\r | |
108 | EFIAPI\r | |
109 | IoWriteWorker (\r | |
110 | IN UINTN Port,\r | |
111 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
112 | IN UINT64 Data\r | |
113 | )\r | |
114 | {\r | |
115 | EFI_STATUS Status;\r | |
116 | \r | |
117 | if (mPciRootBridgeIo != NULL) {\r | |
856500d8 | 118 | Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r |
79964ac8 | 119 | } else {\r |
120 | Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r | |
121 | }\r | |
122 | ASSERT_EFI_ERROR (Status);\r | |
123 | \r | |
124 | return Data;\r | |
125 | }\r | |
126 | \r | |
127 | /**\r | |
128 | Reads memory-mapped registers in the EFI system memory space.\r | |
129 | \r | |
130 | Reads the MMIO registers specified by Address with registers width specified by Width.\r | |
131 | The read value is returned. If such operations are not supported, then ASSERT().\r | |
132 | This function must guarantee that all MMIO read and write operations are serialized.\r | |
133 | \r | |
134 | @param Address The MMIO register to read.\r | |
135 | The caller is responsible for aligning the Address if required.\r | |
136 | @param Width The width of the I/O operation.\r | |
137 | \r | |
138 | @return Data read from registers in the EFI system memory space.\r | |
139 | \r | |
140 | **/\r | |
141 | UINT64\r | |
142 | EFIAPI\r | |
143 | MmioReadWorker (\r | |
144 | IN UINTN Address,\r | |
145 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r | |
146 | )\r | |
147 | {\r | |
148 | EFI_STATUS Status;\r | |
149 | UINT64 Data;\r | |
150 | \r | |
151 | if (mPciRootBridgeIo != NULL) {\r | |
856500d8 | 152 | Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r |
79964ac8 | 153 | } else {\r |
154 | Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r | |
155 | }\r | |
156 | ASSERT_EFI_ERROR (Status);\r | |
157 | \r | |
158 | return Data;\r | |
159 | }\r | |
160 | \r | |
161 | /**\r | |
162 | Writes memory-mapped registers in the EFI system memory space.\r | |
163 | \r | |
164 | Writes the MMIO registers specified by Address with registers width and value specified by Width\r | |
165 | and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r | |
166 | This function must guarantee that all MMIO read and write operations are serialized.\r | |
167 | \r | |
168 | @param Address The MMIO register to read.\r | |
169 | The caller is responsible for aligning the Address if required.\r | |
170 | @param Width The width of the I/O operation.\r | |
171 | \r | |
172 | @return Data read from registers in the EFI system memory space.\r | |
173 | \r | |
174 | **/\r | |
175 | UINT64\r | |
176 | EFIAPI\r | |
177 | MmioWriteWorker (\r | |
178 | IN UINTN Address,\r | |
179 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
180 | IN UINT64 Data\r | |
181 | )\r | |
182 | {\r | |
183 | EFI_STATUS Status;\r | |
184 | \r | |
185 | if (mPciRootBridgeIo != NULL) {\r | |
856500d8 | 186 | Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r |
79964ac8 | 187 | } else {\r |
188 | Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r | |
189 | }\r | |
190 | ASSERT_EFI_ERROR (Status);\r | |
191 | \r | |
192 | return Data;\r | |
193 | }\r | |
194 | \r | |
195 | /**\r | |
196 | Reads an 8-bit I/O port.\r | |
197 | \r | |
198 | Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r | |
199 | This function must guarantee that all I/O read and write operations are\r | |
200 | serialized.\r | |
201 | \r | |
202 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
203 | \r | |
204 | @param Port The I/O port to read.\r | |
205 | \r | |
206 | @return The value read.\r | |
207 | \r | |
208 | **/\r | |
209 | UINT8\r | |
210 | EFIAPI\r | |
211 | IoRead8 (\r | |
212 | IN UINTN Port\r | |
213 | )\r | |
214 | {\r | |
215 | return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);\r | |
216 | }\r | |
217 | \r | |
218 | /**\r | |
219 | Writes an 8-bit I/O port.\r | |
220 | \r | |
221 | Writes the 8-bit I/O port specified by Port with the value specified by Value\r | |
222 | and returns Value. This function must guarantee that all I/O read and write\r | |
223 | operations are serialized.\r | |
224 | \r | |
225 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
226 | \r | |
227 | @param Port The I/O port to write.\r | |
228 | @param Value The value to write to the I/O port.\r | |
229 | \r | |
230 | @return The value written the I/O port.\r | |
231 | \r | |
232 | **/\r | |
233 | UINT8\r | |
234 | EFIAPI\r | |
235 | IoWrite8 (\r | |
236 | IN UINTN Port,\r | |
237 | IN UINT8 Value\r | |
238 | )\r | |
239 | {\r | |
240 | return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);\r | |
241 | }\r | |
242 | \r | |
243 | /**\r | |
244 | Reads a 16-bit I/O port.\r | |
245 | \r | |
246 | Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r | |
247 | This function must guarantee that all I/O read and write operations are\r | |
248 | serialized.\r | |
249 | \r | |
250 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
251 | \r | |
252 | @param Port The I/O port to read.\r | |
253 | \r | |
254 | @return The value read.\r | |
255 | \r | |
256 | **/\r | |
257 | UINT16\r | |
258 | EFIAPI\r | |
259 | IoRead16 (\r | |
260 | IN UINTN Port\r | |
261 | )\r | |
262 | {\r | |
263 | //\r | |
264 | // Make sure Port is aligned on a 16-bit boundary.\r | |
265 | //\r | |
266 | ASSERT ((Port & 1) == 0);\r | |
267 | return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);\r | |
268 | }\r | |
269 | \r | |
270 | /**\r | |
271 | Writes a 16-bit I/O port.\r | |
272 | \r | |
273 | Writes the 16-bit I/O port specified by Port with the value specified by Value\r | |
274 | and returns Value. This function must guarantee that all I/O read and write\r | |
275 | operations are serialized.\r | |
276 | \r | |
277 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
278 | \r | |
279 | @param Port The I/O port to write.\r | |
280 | @param Value The value to write to the I/O port.\r | |
281 | \r | |
282 | @return The value written the I/O port.\r | |
283 | \r | |
284 | **/\r | |
285 | UINT16\r | |
286 | EFIAPI\r | |
287 | IoWrite16 (\r | |
288 | IN UINTN Port,\r | |
289 | IN UINT16 Value\r | |
290 | )\r | |
291 | {\r | |
292 | //\r | |
293 | // Make sure Port is aligned on a 16-bit boundary.\r | |
294 | //\r | |
295 | ASSERT ((Port & 1) == 0);\r | |
296 | return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);\r | |
297 | }\r | |
298 | \r | |
299 | /**\r | |
300 | Reads a 32-bit I/O port.\r | |
301 | \r | |
302 | Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r | |
303 | This function must guarantee that all I/O read and write operations are\r | |
304 | serialized.\r | |
305 | \r | |
306 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
307 | \r | |
308 | @param Port The I/O port to read.\r | |
309 | \r | |
310 | @return The value read.\r | |
311 | \r | |
312 | **/\r | |
313 | UINT32\r | |
314 | EFIAPI\r | |
315 | IoRead32 (\r | |
316 | IN UINTN Port\r | |
317 | )\r | |
318 | {\r | |
319 | //\r | |
320 | // Make sure Port is aligned on a 32-bit boundary.\r | |
321 | //\r | |
322 | ASSERT ((Port & 3) == 0);\r | |
323 | return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);\r | |
324 | }\r | |
325 | \r | |
326 | /**\r | |
327 | Writes a 32-bit I/O port.\r | |
328 | \r | |
329 | Writes the 32-bit I/O port specified by Port with the value specified by Value\r | |
330 | and returns Value. This function must guarantee that all I/O read and write\r | |
331 | operations are serialized.\r | |
332 | \r | |
333 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
334 | \r | |
335 | @param Port The I/O port to write.\r | |
336 | @param Value The value to write to the I/O port.\r | |
337 | \r | |
338 | @return The value written the I/O port.\r | |
339 | \r | |
340 | **/\r | |
341 | UINT32\r | |
342 | EFIAPI\r | |
343 | IoWrite32 (\r | |
344 | IN UINTN Port,\r | |
345 | IN UINT32 Value\r | |
346 | )\r | |
347 | {\r | |
348 | //\r | |
349 | // Make sure Port is aligned on a 32-bit boundary.\r | |
350 | //\r | |
351 | ASSERT ((Port & 3) == 0);\r | |
352 | return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);\r | |
353 | }\r | |
354 | \r | |
355 | /**\r | |
356 | Reads a 64-bit I/O port.\r | |
357 | \r | |
358 | Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r | |
359 | This function must guarantee that all I/O read and write operations are\r | |
360 | serialized.\r | |
361 | \r | |
362 | If 64-bit I/O port operations are not supported, then ASSERT().\r | |
363 | \r | |
364 | @param Port The I/O port to read.\r | |
365 | \r | |
366 | @return The value read.\r | |
367 | \r | |
368 | **/\r | |
369 | UINT64\r | |
370 | EFIAPI\r | |
371 | IoRead64 (\r | |
372 | IN UINTN Port\r | |
373 | )\r | |
374 | {\r | |
375 | //\r | |
376 | // Make sure Port is aligned on a 64-bit boundary.\r | |
377 | //\r | |
378 | ASSERT ((Port & 7) == 0);\r | |
379 | return IoReadWorker (Port, EfiCpuIoWidthUint64);\r | |
380 | }\r | |
381 | \r | |
382 | /**\r | |
383 | Writes a 64-bit I/O port.\r | |
384 | \r | |
385 | Writes the 64-bit I/O port specified by Port with the value specified by Value\r | |
386 | and returns Value. This function must guarantee that all I/O read and write\r | |
387 | operations are serialized.\r | |
388 | \r | |
389 | If 64-bit I/O port operations are not supported, then ASSERT().\r | |
390 | \r | |
391 | @param Port The I/O port to write.\r | |
392 | @param Value The value to write to the I/O port.\r | |
393 | \r | |
394 | @return The value written the I/O port.\r | |
395 | \r | |
396 | **/\r | |
397 | UINT64\r | |
398 | EFIAPI\r | |
399 | IoWrite64 (\r | |
400 | IN UINTN Port,\r | |
401 | IN UINT64 Value\r | |
402 | )\r | |
403 | {\r | |
404 | //\r | |
405 | // Make sure Port is aligned on a 64-bit boundary.\r | |
406 | //\r | |
407 | ASSERT ((Port & 7) == 0);\r | |
408 | return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);\r | |
409 | }\r | |
410 | \r | |
411 | /**\r | |
412 | Reads an 8-bit MMIO register.\r | |
413 | \r | |
414 | Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r | |
415 | returned. This function must guarantee that all MMIO read and write\r | |
416 | operations are serialized.\r | |
417 | \r | |
418 | If 8-bit MMIO register operations are not supported, then ASSERT().\r | |
419 | \r | |
420 | @param Address The MMIO register to read.\r | |
421 | \r | |
422 | @return The value read.\r | |
423 | \r | |
424 | **/\r | |
425 | UINT8\r | |
426 | EFIAPI\r | |
427 | MmioRead8 (\r | |
428 | IN UINTN Address\r | |
429 | )\r | |
430 | {\r | |
431 | return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);\r | |
432 | }\r | |
433 | \r | |
434 | /**\r | |
435 | Writes an 8-bit MMIO register.\r | |
436 | \r | |
437 | Writes the 8-bit MMIO register specified by Address with the value specified\r | |
438 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
439 | and write operations are serialized.\r | |
440 | \r | |
441 | If 8-bit MMIO register operations are not supported, then ASSERT().\r | |
442 | \r | |
443 | @param Address The MMIO register to write.\r | |
444 | @param Value The value to write to the MMIO register.\r | |
445 | \r | |
446 | **/\r | |
447 | UINT8\r | |
448 | EFIAPI\r | |
449 | MmioWrite8 (\r | |
450 | IN UINTN Address,\r | |
451 | IN UINT8 Value\r | |
452 | )\r | |
453 | {\r | |
454 | return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);\r | |
455 | }\r | |
456 | \r | |
457 | /**\r | |
458 | Reads a 16-bit MMIO register.\r | |
459 | \r | |
460 | Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r | |
461 | returned. This function must guarantee that all MMIO read and write\r | |
462 | operations are serialized.\r | |
463 | \r | |
464 | If 16-bit MMIO register operations are not supported, then ASSERT().\r | |
465 | \r | |
466 | @param Address The MMIO register to read.\r | |
467 | \r | |
468 | @return The value read.\r | |
469 | \r | |
470 | **/\r | |
471 | UINT16\r | |
472 | EFIAPI\r | |
473 | MmioRead16 (\r | |
474 | IN UINTN Address\r | |
475 | )\r | |
476 | {\r | |
477 | //\r | |
478 | // Make sure Address is aligned on a 16-bit boundary.\r | |
479 | //\r | |
480 | ASSERT ((Address & 1) == 0);\r | |
481 | return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);\r | |
482 | }\r | |
483 | \r | |
484 | /**\r | |
485 | Writes a 16-bit MMIO register.\r | |
486 | \r | |
487 | Writes the 16-bit MMIO register specified by Address with the value specified\r | |
488 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
489 | and write operations are serialized.\r | |
490 | \r | |
491 | If 16-bit MMIO register operations are not supported, then ASSERT().\r | |
492 | \r | |
493 | @param Address The MMIO register to write.\r | |
494 | @param Value The value to write to the MMIO register.\r | |
495 | \r | |
496 | **/\r | |
497 | UINT16\r | |
498 | EFIAPI\r | |
499 | MmioWrite16 (\r | |
500 | IN UINTN Address,\r | |
501 | IN UINT16 Value\r | |
502 | )\r | |
503 | {\r | |
504 | //\r | |
505 | // Make sure Address is aligned on a 16-bit boundary.\r | |
506 | //\r | |
507 | ASSERT ((Address & 1) == 0);\r | |
508 | return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);\r | |
509 | }\r | |
510 | \r | |
511 | /**\r | |
512 | Reads a 32-bit MMIO register.\r | |
513 | \r | |
514 | Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r | |
515 | returned. This function must guarantee that all MMIO read and write\r | |
516 | operations are serialized.\r | |
517 | \r | |
518 | If 32-bit MMIO register operations are not supported, then ASSERT().\r | |
519 | \r | |
520 | @param Address The MMIO register to read.\r | |
521 | \r | |
522 | @return The value read.\r | |
523 | \r | |
524 | **/\r | |
525 | UINT32\r | |
526 | EFIAPI\r | |
527 | MmioRead32 (\r | |
528 | IN UINTN Address\r | |
529 | )\r | |
530 | {\r | |
531 | //\r | |
532 | // Make sure Address is aligned on a 32-bit boundary.\r | |
533 | //\r | |
534 | ASSERT ((Address & 3) == 0);\r | |
535 | return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);\r | |
536 | }\r | |
537 | \r | |
538 | /**\r | |
539 | Writes a 32-bit MMIO register.\r | |
540 | \r | |
541 | Writes the 32-bit MMIO register specified by Address with the value specified\r | |
542 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
543 | and write operations are serialized.\r | |
544 | \r | |
545 | If 32-bit MMIO register operations are not supported, then ASSERT().\r | |
546 | \r | |
547 | @param Address The MMIO register to write.\r | |
548 | @param Value The value to write to the MMIO register.\r | |
549 | \r | |
550 | **/\r | |
551 | UINT32\r | |
552 | EFIAPI\r | |
553 | MmioWrite32 (\r | |
554 | IN UINTN Address,\r | |
555 | IN UINT32 Value\r | |
556 | )\r | |
557 | {\r | |
558 | //\r | |
559 | // Make sure Address is aligned on a 32-bit boundary.\r | |
560 | //\r | |
561 | ASSERT ((Address & 3) == 0);\r | |
562 | return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);\r | |
563 | }\r | |
564 | \r | |
565 | /**\r | |
566 | Reads a 64-bit MMIO register.\r | |
567 | \r | |
568 | Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r | |
569 | returned. This function must guarantee that all MMIO read and write\r | |
570 | operations are serialized.\r | |
571 | \r | |
572 | If 64-bit MMIO register operations are not supported, then ASSERT().\r | |
573 | \r | |
574 | @param Address The MMIO register to read.\r | |
575 | \r | |
576 | @return The value read.\r | |
577 | \r | |
578 | **/\r | |
579 | UINT64\r | |
580 | EFIAPI\r | |
581 | MmioRead64 (\r | |
582 | IN UINTN Address\r | |
583 | )\r | |
584 | {\r | |
585 | //\r | |
586 | // Make sure Address is aligned on a 64-bit boundary.\r | |
587 | //\r | |
588 | ASSERT ((Address & 7) == 0);\r | |
589 | return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);\r | |
590 | }\r | |
591 | \r | |
592 | /**\r | |
593 | Writes a 64-bit MMIO register.\r | |
594 | \r | |
595 | Writes the 64-bit MMIO register specified by Address with the value specified\r | |
596 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
597 | and write operations are serialized.\r | |
598 | \r | |
599 | If 64-bit MMIO register operations are not supported, then ASSERT().\r | |
600 | \r | |
601 | @param Address The MMIO register to write.\r | |
602 | @param Value The value to write to the MMIO register.\r | |
603 | \r | |
604 | **/\r | |
605 | UINT64\r | |
606 | EFIAPI\r | |
607 | MmioWrite64 (\r | |
608 | IN UINTN Address,\r | |
609 | IN UINT64 Value\r | |
610 | )\r | |
611 | {\r | |
612 | //\r | |
613 | // Make sure Address is aligned on a 64-bit boundary.\r | |
614 | //\r | |
615 | ASSERT ((Address & 7) == 0);\r | |
616 | return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);\r | |
617 | }\r |