1. fixed one bug in Common/FrameworkFirmwareFileSystem.h
[mirror_edk2.git] / IntelFrameworkPkg / Library / DxeIoLibCpuIo / IoLib.c
CommitLineData
79964ac8 1/** @file\r
2 I/O Library.\r
3\r
4 Copyright (c) 2006, Intel Corporation<BR>\r
5 All rights reserved. This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13 Module Name: IoLib.c\r
14\r
15**/\r
16\r
53f93f7e 17//\r
18// Include common header file for this module.\r
19//\r
20#include "CommonHeader.h"\r
21\r
79964ac8 22#include "DxeCpuIoLibInternal.h"\r
23\r
24//\r
25// Globle varible to cache pointer to CpuIo protocol.\r
26//\r
27STATIC EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;\r
28STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r
29\r
30/**\r
31 The constructor function caches the pointer to CpuIo protocol.\r
32\r
33 The constructor function locates CpuIo protocol from protocol database.\r
34 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r
35\r
36 @param ImageHandle The firmware allocated handle for the EFI image.\r
37 @param SystemTable A pointer to the EFI System Table.\r
38\r
39 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
40\r
41**/\r
42EFI_STATUS\r
43EFIAPI\r
44IoLibConstructor (\r
45 IN EFI_HANDLE ImageHandle,\r
46 IN EFI_SYSTEM_TABLE *SystemTable\r
47 )\r
48{\r
49 EFI_STATUS Status;\r
50\r
51 Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, &mPciRootBridgeIo);\r
52 if (EFI_ERROR (Status)) {\r
53 Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &mCpuIo);\r
54 }\r
55 ASSERT_EFI_ERROR (Status);\r
56\r
57 return Status;\r
58}\r
59\r
60/**\r
61 Reads registers in the EFI CPU I/O space.\r
62\r
63 Reads the I/O port specified by Port with registers width specified by Width.\r
64 The read value is returned. If such operations are not supported, then ASSERT().\r
65 This function must guarantee that all I/O read and write operations are serialized.\r
66\r
67 @param Port The base address of the I/O operation.\r
68 The caller is responsible for aligning the Address if required.\r
69 @param Width The width of the I/O operation.\r
70\r
71 @return Data read from registers in the EFI CPU I/O space.\r
72\r
73**/\r
74UINT64\r
75EFIAPI\r
76IoReadWorker (\r
77 IN UINTN Port,\r
78 IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
79 )\r
80{\r
81 EFI_STATUS Status;\r
82 UINT64 Data;\r
83\r
84 if (mPciRootBridgeIo != NULL) {\r
85 Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, Width, Port, 1, &Data);\r
86 } else {\r
87 Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r
88 }\r
89 ASSERT_EFI_ERROR (Status);\r
90\r
91 return Data;\r
92}\r
93\r
94/**\r
95 Writes registers in the EFI CPU I/O space.\r
96\r
97 Writes the I/O port specified by Port with registers width and value specified by Width\r
98 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
99 This function must guarantee that all I/O read and write operations are serialized.\r
100\r
101 @param Port The base address of the I/O operation.\r
102 The caller is responsible for aligning the Address if required.\r
103 @param Width The width of the I/O operation.\r
104 @param Data The value to write to the I/O port.\r
105\r
106 @return The paramter of Data.\r
107\r
108**/\r
109UINT64\r
110EFIAPI\r
111IoWriteWorker (\r
112 IN UINTN Port,\r
113 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
114 IN UINT64 Data\r
115 )\r
116{\r
117 EFI_STATUS Status;\r
118\r
119 if (mPciRootBridgeIo != NULL) {\r
120 Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, Width, Port, 1, &Data);\r
121 } else {\r
122 Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r
123 }\r
124 ASSERT_EFI_ERROR (Status);\r
125\r
126 return Data;\r
127}\r
128\r
129/**\r
130 Reads memory-mapped registers in the EFI system memory space.\r
131\r
132 Reads the MMIO registers specified by Address with registers width specified by Width.\r
133 The read value is returned. If such operations are not supported, then ASSERT().\r
134 This function must guarantee that all MMIO read and write operations are serialized.\r
135\r
136 @param Address The MMIO register to read.\r
137 The caller is responsible for aligning the Address if required.\r
138 @param Width The width of the I/O operation.\r
139\r
140 @return Data read from registers in the EFI system memory space.\r
141\r
142**/\r
143UINT64\r
144EFIAPI\r
145MmioReadWorker (\r
146 IN UINTN Address,\r
147 IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
148 )\r
149{\r
150 EFI_STATUS Status;\r
151 UINT64 Data;\r
152\r
153 if (mPciRootBridgeIo != NULL) {\r
53f93f7e 154 Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, Width, Address, 1, &Data);\r
79964ac8 155 } else {\r
156 Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r
157 }\r
158 ASSERT_EFI_ERROR (Status);\r
159\r
160 return Data;\r
161}\r
162\r
163/**\r
164 Writes memory-mapped registers in the EFI system memory space.\r
165\r
166 Writes the MMIO registers specified by Address with registers width and value specified by Width\r
167 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
168 This function must guarantee that all MMIO read and write operations are serialized.\r
169\r
170 @param Address The MMIO register to read.\r
171 The caller is responsible for aligning the Address if required.\r
172 @param Width The width of the I/O operation.\r
173\r
174 @return Data read from registers in the EFI system memory space.\r
175\r
176**/\r
177UINT64\r
178EFIAPI\r
179MmioWriteWorker (\r
180 IN UINTN Address,\r
181 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
182 IN UINT64 Data\r
183 )\r
184{\r
185 EFI_STATUS Status;\r
186\r
187 if (mPciRootBridgeIo != NULL) {\r
188 Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, Width, Address, 1, &Data);\r
189 } else {\r
190 Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r
191 }\r
192 ASSERT_EFI_ERROR (Status);\r
193\r
194 return Data;\r
195}\r
196\r
197/**\r
198 Reads an 8-bit I/O port.\r
199\r
200 Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
201 This function must guarantee that all I/O read and write operations are\r
202 serialized.\r
203\r
204 If 8-bit I/O port operations are not supported, then ASSERT().\r
205\r
206 @param Port The I/O port to read.\r
207\r
208 @return The value read.\r
209\r
210**/\r
211UINT8\r
212EFIAPI\r
213IoRead8 (\r
214 IN UINTN Port\r
215 )\r
216{\r
217 return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);\r
218}\r
219\r
220/**\r
221 Writes an 8-bit I/O port.\r
222\r
223 Writes the 8-bit I/O port specified by Port with the value specified by Value\r
224 and returns Value. This function must guarantee that all I/O read and write\r
225 operations are serialized.\r
226\r
227 If 8-bit I/O port operations are not supported, then ASSERT().\r
228\r
229 @param Port The I/O port to write.\r
230 @param Value The value to write to the I/O port.\r
231\r
232 @return The value written the I/O port.\r
233\r
234**/\r
235UINT8\r
236EFIAPI\r
237IoWrite8 (\r
238 IN UINTN Port,\r
239 IN UINT8 Value\r
240 )\r
241{\r
242 return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);\r
243}\r
244\r
245/**\r
246 Reads a 16-bit I/O port.\r
247\r
248 Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
249 This function must guarantee that all I/O read and write operations are\r
250 serialized.\r
251\r
252 If 16-bit I/O port operations are not supported, then ASSERT().\r
253\r
254 @param Port The I/O port to read.\r
255\r
256 @return The value read.\r
257\r
258**/\r
259UINT16\r
260EFIAPI\r
261IoRead16 (\r
262 IN UINTN Port\r
263 )\r
264{\r
265 //\r
266 // Make sure Port is aligned on a 16-bit boundary.\r
267 //\r
268 ASSERT ((Port & 1) == 0);\r
269 return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);\r
270}\r
271\r
272/**\r
273 Writes a 16-bit I/O port.\r
274\r
275 Writes the 16-bit I/O port specified by Port with the value specified by Value\r
276 and returns Value. This function must guarantee that all I/O read and write\r
277 operations are serialized.\r
278\r
279 If 16-bit I/O port operations are not supported, then ASSERT().\r
280\r
281 @param Port The I/O port to write.\r
282 @param Value The value to write to the I/O port.\r
283\r
284 @return The value written the I/O port.\r
285\r
286**/\r
287UINT16\r
288EFIAPI\r
289IoWrite16 (\r
290 IN UINTN Port,\r
291 IN UINT16 Value\r
292 )\r
293{\r
294 //\r
295 // Make sure Port is aligned on a 16-bit boundary.\r
296 //\r
297 ASSERT ((Port & 1) == 0);\r
298 return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);\r
299}\r
300\r
301/**\r
302 Reads a 32-bit I/O port.\r
303\r
304 Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
305 This function must guarantee that all I/O read and write operations are\r
306 serialized.\r
307\r
308 If 32-bit I/O port operations are not supported, then ASSERT().\r
309\r
310 @param Port The I/O port to read.\r
311\r
312 @return The value read.\r
313\r
314**/\r
315UINT32\r
316EFIAPI\r
317IoRead32 (\r
318 IN UINTN Port\r
319 )\r
320{\r
321 //\r
322 // Make sure Port is aligned on a 32-bit boundary.\r
323 //\r
324 ASSERT ((Port & 3) == 0);\r
325 return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);\r
326}\r
327\r
328/**\r
329 Writes a 32-bit I/O port.\r
330\r
331 Writes the 32-bit I/O port specified by Port with the value specified by Value\r
332 and returns Value. This function must guarantee that all I/O read and write\r
333 operations are serialized.\r
334\r
335 If 32-bit I/O port operations are not supported, then ASSERT().\r
336\r
337 @param Port The I/O port to write.\r
338 @param Value The value to write to the I/O port.\r
339\r
340 @return The value written the I/O port.\r
341\r
342**/\r
343UINT32\r
344EFIAPI\r
345IoWrite32 (\r
346 IN UINTN Port,\r
347 IN UINT32 Value\r
348 )\r
349{\r
350 //\r
351 // Make sure Port is aligned on a 32-bit boundary.\r
352 //\r
353 ASSERT ((Port & 3) == 0);\r
354 return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);\r
355}\r
356\r
357/**\r
358 Reads a 64-bit I/O port.\r
359\r
360 Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
361 This function must guarantee that all I/O read and write operations are\r
362 serialized.\r
363\r
364 If 64-bit I/O port operations are not supported, then ASSERT().\r
365\r
366 @param Port The I/O port to read.\r
367\r
368 @return The value read.\r
369\r
370**/\r
371UINT64\r
372EFIAPI\r
373IoRead64 (\r
374 IN UINTN Port\r
375 )\r
376{\r
377 //\r
378 // Make sure Port is aligned on a 64-bit boundary.\r
379 //\r
380 ASSERT ((Port & 7) == 0);\r
381 return IoReadWorker (Port, EfiCpuIoWidthUint64);\r
382}\r
383\r
384/**\r
385 Writes a 64-bit I/O port.\r
386\r
387 Writes the 64-bit I/O port specified by Port with the value specified by Value\r
388 and returns Value. This function must guarantee that all I/O read and write\r
389 operations are serialized.\r
390\r
391 If 64-bit I/O port operations are not supported, then ASSERT().\r
392\r
393 @param Port The I/O port to write.\r
394 @param Value The value to write to the I/O port.\r
395\r
396 @return The value written the I/O port.\r
397\r
398**/\r
399UINT64\r
400EFIAPI\r
401IoWrite64 (\r
402 IN UINTN Port,\r
403 IN UINT64 Value\r
404 )\r
405{\r
406 //\r
407 // Make sure Port is aligned on a 64-bit boundary.\r
408 //\r
409 ASSERT ((Port & 7) == 0);\r
410 return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);\r
411}\r
412\r
413/**\r
414 Reads an 8-bit MMIO register.\r
415\r
416 Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
417 returned. This function must guarantee that all MMIO read and write\r
418 operations are serialized.\r
419\r
420 If 8-bit MMIO register operations are not supported, then ASSERT().\r
421\r
422 @param Address The MMIO register to read.\r
423\r
424 @return The value read.\r
425\r
426**/\r
427UINT8\r
428EFIAPI\r
429MmioRead8 (\r
430 IN UINTN Address\r
431 )\r
432{\r
433 return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);\r
434}\r
435\r
436/**\r
437 Writes an 8-bit MMIO register.\r
438\r
439 Writes the 8-bit MMIO register specified by Address with the value specified\r
440 by Value and returns Value. This function must guarantee that all MMIO read\r
441 and write operations are serialized.\r
442\r
443 If 8-bit MMIO register operations are not supported, then ASSERT().\r
444\r
445 @param Address The MMIO register to write.\r
446 @param Value The value to write to the MMIO register.\r
447\r
448**/\r
449UINT8\r
450EFIAPI\r
451MmioWrite8 (\r
452 IN UINTN Address,\r
453 IN UINT8 Value\r
454 )\r
455{\r
456 return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);\r
457}\r
458\r
459/**\r
460 Reads a 16-bit MMIO register.\r
461\r
462 Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
463 returned. This function must guarantee that all MMIO read and write\r
464 operations are serialized.\r
465\r
466 If 16-bit MMIO register operations are not supported, then ASSERT().\r
467\r
468 @param Address The MMIO register to read.\r
469\r
470 @return The value read.\r
471\r
472**/\r
473UINT16\r
474EFIAPI\r
475MmioRead16 (\r
476 IN UINTN Address\r
477 )\r
478{\r
479 //\r
480 // Make sure Address is aligned on a 16-bit boundary.\r
481 //\r
482 ASSERT ((Address & 1) == 0);\r
483 return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);\r
484}\r
485\r
486/**\r
487 Writes a 16-bit MMIO register.\r
488\r
489 Writes the 16-bit MMIO register specified by Address with the value specified\r
490 by Value and returns Value. This function must guarantee that all MMIO read\r
491 and write operations are serialized.\r
492\r
493 If 16-bit MMIO register operations are not supported, then ASSERT().\r
494\r
495 @param Address The MMIO register to write.\r
496 @param Value The value to write to the MMIO register.\r
497\r
498**/\r
499UINT16\r
500EFIAPI\r
501MmioWrite16 (\r
502 IN UINTN Address,\r
503 IN UINT16 Value\r
504 )\r
505{\r
506 //\r
507 // Make sure Address is aligned on a 16-bit boundary.\r
508 //\r
509 ASSERT ((Address & 1) == 0);\r
510 return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);\r
511}\r
512\r
513/**\r
514 Reads a 32-bit MMIO register.\r
515\r
516 Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
517 returned. This function must guarantee that all MMIO read and write\r
518 operations are serialized.\r
519\r
520 If 32-bit MMIO register operations are not supported, then ASSERT().\r
521\r
522 @param Address The MMIO register to read.\r
523\r
524 @return The value read.\r
525\r
526**/\r
527UINT32\r
528EFIAPI\r
529MmioRead32 (\r
530 IN UINTN Address\r
531 )\r
532{\r
533 //\r
534 // Make sure Address is aligned on a 32-bit boundary.\r
535 //\r
536 ASSERT ((Address & 3) == 0);\r
537 return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);\r
538}\r
539\r
540/**\r
541 Writes a 32-bit MMIO register.\r
542\r
543 Writes the 32-bit MMIO register specified by Address with the value specified\r
544 by Value and returns Value. This function must guarantee that all MMIO read\r
545 and write operations are serialized.\r
546\r
547 If 32-bit MMIO register operations are not supported, then ASSERT().\r
548\r
549 @param Address The MMIO register to write.\r
550 @param Value The value to write to the MMIO register.\r
551\r
552**/\r
553UINT32\r
554EFIAPI\r
555MmioWrite32 (\r
556 IN UINTN Address,\r
557 IN UINT32 Value\r
558 )\r
559{\r
560 //\r
561 // Make sure Address is aligned on a 32-bit boundary.\r
562 //\r
563 ASSERT ((Address & 3) == 0);\r
564 return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);\r
565}\r
566\r
567/**\r
568 Reads a 64-bit MMIO register.\r
569\r
570 Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
571 returned. This function must guarantee that all MMIO read and write\r
572 operations are serialized.\r
573\r
574 If 64-bit MMIO register operations are not supported, then ASSERT().\r
575\r
576 @param Address The MMIO register to read.\r
577\r
578 @return The value read.\r
579\r
580**/\r
581UINT64\r
582EFIAPI\r
583MmioRead64 (\r
584 IN UINTN Address\r
585 )\r
586{\r
587 //\r
588 // Make sure Address is aligned on a 64-bit boundary.\r
589 //\r
590 ASSERT ((Address & 7) == 0);\r
591 return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);\r
592}\r
593\r
594/**\r
595 Writes a 64-bit MMIO register.\r
596\r
597 Writes the 64-bit MMIO register specified by Address with the value specified\r
598 by Value and returns Value. This function must guarantee that all MMIO read\r
599 and write operations are serialized.\r
600\r
601 If 64-bit MMIO register operations are not supported, then ASSERT().\r
602\r
603 @param Address The MMIO register to write.\r
604 @param Value The value to write to the MMIO register.\r
605\r
606**/\r
607UINT64\r
608EFIAPI\r
609MmioWrite64 (\r
610 IN UINTN Address,\r
611 IN UINT64 Value\r
612 )\r
613{\r
614 //\r
615 // Make sure Address is aligned on a 64-bit boundary.\r
616 //\r
617 ASSERT ((Address & 7) == 0);\r
618 return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);\r
619}\r