[mirror_edk2.git] / IntelFsp2Pkg / Include / Guid / FspHeaderFile.h

/** @file\r
  Intel FSP Header File definition from Intel Firmware Support Package External\r
  Architecture Specification v2.0 and above.\r
\r
  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Base.h>\r
\r
#ifndef __FSP_HEADER_FILE_H__\r
#define __FSP_HEADER_FILE_H__\r
\r
#define FSP_HEADER_REVISION_3  3\r
\r
#define FSPE_HEADER_REVISION_1  1\r
#define FSPP_HEADER_REVISION_1  1\r
\r
///\r
/// Fixed FSP header offset in the FSP image\r
///\r
#define FSP_INFO_HEADER_OFF  0x94\r
\r
#define OFFSET_IN_FSP_INFO_HEADER(x)  (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r
\r
#define FSP_INFO_HEADER_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'H')\r
\r
#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT       BIT0\r
#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT  BIT1\r
#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT     BIT2\r
#define FSP_IA32                               0\r
#define FSP_X64                                1\r
\r
  #pragma pack(1)\r
\r
///\r
/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.\r
///\r
typedef struct {\r
  ///\r
  /// Byte 0x00: Signature ('FSPH') for the FSP Information Header.\r
  ///\r
  UINT32    Signature;\r
  ///\r
  /// Byte 0x04: Length of the FSP Information Header.\r
  ///\r
  UINT32    HeaderLength;\r
  ///\r
  /// Byte 0x08: Reserved.\r
  ///\r
  UINT8     Reserved1[2];\r
  ///\r
  /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.\r
  ///            For revision v2.4 the value will be 0x24.\r
  ///\r
  UINT8     SpecVersion;\r
  ///\r
  /// Byte 0x0B: Revision of the FSP Information Header.\r
  ///            The Current value for this field is 0x7.\r
  ///\r
  UINT8     HeaderRevision;\r
  ///\r
  /// Byte 0x0C: Revision of the FSP binary.\r
  ///            Major.Minor.Revision.Build\r
  ///            If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:\r
  ///               7 : 0  - Build Number\r
  ///              15 : 8  - Revision\r
  ///              23 : 16 - Minor Version\r
  ///              31 : 24 - Major Version\r
  ///            If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision\r
  ///            while ExtendedImageRevision specifies the high-order bytes of the build number and revision.\r
  ///               7 : 0  - Low Byte of Build Number\r
  ///              15 : 8  - Low Byte of Revision\r
  ///              23 : 16 - Minor Version\r
  ///              31 : 24 - Major Version\r
  ///\r
  UINT32    ImageRevision;\r
  ///\r
  /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.\r
  ///\r
  CHAR8     ImageId[8];\r
  ///\r
  /// Byte 0x18: Size of the entire FSP binary.\r
  ///\r
  UINT32    ImageSize;\r
  ///\r
  /// Byte 0x1C: FSP binary preferred base address.\r
  ///\r
  UINT32    ImageBase;\r
  ///\r
  /// Byte 0x20: Attribute for the FSP binary.\r
  ///   Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.\r
  ///   Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.\r
  ///   Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.\r
  ///   Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP utilizes the FSP Variable Services defined in Section 9.6 to store non-volatile data. This bit is only valid if FSP HeaderRevision is >= 7.\r
  ///   Bits 15:4 - Reserved\r
  ///\r
  UINT16    ImageAttribute;\r
  ///\r
  /// Byte 0x22: Attributes of the FSP Component.\r
  ///   Bit 0 - Build Type\r
  ///     0 - Debug Build\r
  ///     1 - Release Build\r
  ///   Bit 1 - Release Type\r
  ///     0 - Test Release\r
  ///     1 - Official Release\r
  ///   Bit 11:2 - Reserved\r
  ///   Bits 15:12 - Component Type\r
  ///     0000 - Reserved\r
  ///     0001 - FSP-T\r
  ///     0010 - FSP-M\r
  ///     0011 - FSP-S\r
  ///     0100 - FSP-I (FSP SMM)\r
  ///     0101 to 0111 - Reserved\r
  ///     1000 - FSP-O\r
  ///     1001 to 1111 - Reserved\r
  ///\r
  UINT16    ComponentAttribute;\r
  ///\r
  /// Byte 0x24: Offset of the FSP configuration region.\r
  ///\r
  UINT32    CfgRegionOffset;\r
  ///\r
  /// Byte 0x28: Size of the FSP configuration region.\r
  ///\r
  UINT32    CfgRegionSize;\r
  ///\r
  /// Byte 0x2C: Reserved2.\r
  ///\r
  UINT32    Reserved2;\r
  ///\r
  /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.\r
  ///\r
  UINT32    TempRamInitEntryOffset;\r
  ///\r
  /// Byte 0x34: Reserved3.\r
  ///\r
  UINT32    Reserved3;\r
  ///\r
  /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.\r
  ///\r
  UINT32    NotifyPhaseEntryOffset;\r
  ///\r
  /// Byte 0x3C: The offset for the API to initialize the memory.\r
  ///\r
  UINT32    FspMemoryInitEntryOffset;\r
  ///\r
  /// Byte 0x40: The offset for the API to tear down temporary RAM.\r
  ///\r
  UINT32    TempRamExitEntryOffset;\r
  ///\r
  /// Byte 0x44: The offset for the API to initialize the CPU and chipset.\r
  ///\r
  UINT32    FspSiliconInitEntryOffset;\r
  ///\r
  /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.\r
  ///            This value is only valid if FSP HeaderRevision is >= 5.\r
  ///            If the value is set to 0x00000000, then this API is not available in this component.\r
  ///\r
  UINT32    FspMultiPhaseSiInitEntryOffset;\r
  ///\r
  /// Byte 0x4C: Extended revision of the FSP binary.\r
  ///            This value is only valid if FSP HeaderRevision is >= 6.\r
  ///            ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.\r
  ///               7 : 0 - High Byte of Build Number\r
  ///              15 : 8 - High Byte of Revision\r
  ///            The FSP binary build number can be decoded as follows:\r
  ///            Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]\r
  ///            Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]\r
  ///            Minor Version = ImageRevision[23:16]\r
  ///            Major Version = ImageRevision[31:24]\r
  ///\r
  UINT16    ExtendedImageRevision;\r
  ///\r
  /// Byte 0x4E: Reserved4.\r
  ///\r
  UINT16    Reserved4;\r
  ///\r
  /// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.\r
  ///\r
  UINT32    FspMultiPhaseMemInitEntryOffset;\r
  ///\r
  /// Byte 0x54: Offset for the API to initialize SMM.\r
  ///\r
  UINT32    FspSmmInitEntryOffset;\r
} FSP_INFO_HEADER;\r
\r
///\r
/// Signature of the FSP Extended Header\r
///\r
#define FSP_INFO_EXTENDED_HEADER_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'E')\r
\r
///\r
/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.\r
///\r
typedef struct {\r
  ///\r
  /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.\r
  ///\r
  UINT32    Signature;\r
  ///\r
  /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.\r
  ///\r
  UINT32    Length;\r
  ///\r
  /// Byte 0x08: FSP producer defined revision of the table.\r
  ///\r
  UINT8     Revision;\r
  ///\r
  /// Byte 0x09: Reserved for future use.\r
  ///\r
  UINT8     Reserved;\r
  ///\r
  /// Byte 0x0A: FSP producer identification string\r
  ///\r
  CHAR8     FspProducerId[6];\r
  ///\r
  /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.\r
  ///\r
  UINT32    FspProducerRevision;\r
  ///\r
  /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.\r
  ///\r
  UINT32    FspProducerDataSize;\r
  ///\r
  /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.\r
  ///\r
} FSP_INFO_EXTENDED_HEADER;\r
\r
//\r
// A generic table search algorithm for additional tables can be implemented with a\r
// signature search algorithm until a terminator signature 'FSPP' is found.\r
//\r
#define FSP_FSPP_SIGNATURE         SIGNATURE_32 ('F', 'S', 'P', 'P')\r
#define FSP_PATCH_TABLE_SIGNATURE  FSP_FSPP_SIGNATURE\r
\r
///\r
/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.\r
///\r
typedef struct {\r
  ///\r
  /// Byte 0x00: FSP Patch Table Signature "FSPP".\r
  ///\r
  UINT32    Signature;\r
  ///\r
  /// Byte 0x04: Size including the PatchData.\r
  ///\r
  UINT16    HeaderLength;\r
  ///\r
  /// Byte 0x06: Revision is set to 0x01.\r
  ///\r
  UINT8     HeaderRevision;\r
  ///\r
  /// Byte 0x07: Reserved for future use.\r
  ///\r
  UINT8     Reserved;\r
  ///\r
  /// Byte 0x08: Number of entries to Patch.\r
  ///\r
  UINT32    PatchEntryNum;\r
  ///\r
  /// Byte 0x0C: Patch Data.\r
  ///\r
  // UINT32  PatchData[];\r
} FSP_PATCH_TABLE;\r
\r
  #pragma pack()\r
\r
extern EFI_GUID  gFspHeaderFileGuid;\r
\r
#endif\r
Commit	Line	Data
cf1d4549 JY	1	/** @file\r
cf1d4549 JY	2	Intel FSP Header File definition from Intel Firmware Support Package External\r
f2cdb268	3	Architecture Specification v2.0 and above.\r
cf1d4549	4	\r
00aa71ce	5	Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
9672cd30	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
cf1d4549 JY	7	\r
	8	**/\r
	9	\r
00aa71ce TK	10	#include <Base.h>\r
00aa71ce TK	11	\r
cf1d4549 JY	12	#ifndef __FSP_HEADER_FILE_H__\r
	13	#define __FSP_HEADER_FILE_H__\r
	14	\r
111f2228	15	#define FSP_HEADER_REVISION_3 3\r
cf1d4549 JY	16	\r
	17	#define FSPE_HEADER_REVISION_1 1\r
	18	#define FSPP_HEADER_REVISION_1 1\r
	19	\r
	20	///\r
	21	/// Fixed FSP header offset in the FSP image\r
	22	///\r
111f2228	23	#define FSP_INFO_HEADER_OFF 0x94\r
cf1d4549 JY	24	\r
	25	#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r
	26	\r
	27	#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')\r
	28	\r
48249243 HZ	29	#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0\r
	30	#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1\r
	31	#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2\r
	32	#define FSP_IA32 0\r
	33	#define FSP_X64 1\r
00aa71ce	34	\r
48249243	35	#pragma pack(1)\r
cf1d4549 JY	36	\r
	37	///\r
	38	/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.\r
	39	///\r
	40	typedef struct {\r
	41	///\r
	42	/// Byte 0x00: Signature ('FSPH') for the FSP Information Header.\r
	43	///\r
111f2228	44	UINT32 Signature;\r
cf1d4549 JY	45	///\r
	46	/// Byte 0x04: Length of the FSP Information Header.\r
	47	///\r
111f2228	48	UINT32 HeaderLength;\r
cf1d4549 JY	49	///\r
	50	/// Byte 0x08: Reserved.\r
	51	///\r
111f2228	52	UINT8 Reserved1[2];\r
cf1d4549 JY	53	///\r
cf1d4549 JY	54	/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.\r
5a3641bf	55	/// For revision v2.4 the value will be 0x24.\r
cf1d4549	56	///\r
111f2228	57	UINT8 SpecVersion;\r
cf1d4549 JY	58	///\r
cf1d4549 JY	59	/// Byte 0x0B: Revision of the FSP Information Header.\r
00aa71ce	60	/// The Current value for this field is 0x7.\r
cf1d4549	61	///\r
111f2228	62	UINT8 HeaderRevision;\r
cf1d4549 JY	63	///\r
cf1d4549 JY	64	/// Byte 0x0C: Revision of the FSP binary.\r
4cc1458d CC	65	/// Major.Minor.Revision.Build\r
	66	/// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:\r
	67	/// 7 : 0 - Build Number\r
	68	/// 15 : 8 - Revision\r
	69	/// 23 : 16 - Minor Version\r
	70	/// 31 : 24 - Major Version\r
	71	/// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision\r
	72	/// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.\r
	73	/// 7 : 0 - Low Byte of Build Number\r
	74	/// 15 : 8 - Low Byte of Revision\r
	75	/// 23 : 16 - Minor Version\r
	76	/// 31 : 24 - Major Version\r
cf1d4549	77	///\r
111f2228	78	UINT32 ImageRevision;\r
cf1d4549 JY	79	///\r
	80	/// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.\r
	81	///\r
111f2228	82	CHAR8 ImageId[8];\r
cf1d4549 JY	83	///\r
	84	/// Byte 0x18: Size of the entire FSP binary.\r
	85	///\r
111f2228	86	UINT32 ImageSize;\r
cf1d4549 JY	87	///\r
	88	/// Byte 0x1C: FSP binary preferred base address.\r
	89	///\r
111f2228	90	UINT32 ImageBase;\r
cf1d4549 JY	91	///\r
cf1d4549 JY	92	/// Byte 0x20: Attribute for the FSP binary.\r
00aa71ce TK	93	/// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.\r
	94	/// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.\r
	95	/// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.\r
5a3641bf CC	96	/// Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP utilizes the FSP Variable Services defined in Section 9.6 to store non-volatile data. This bit is only valid if FSP HeaderRevision is >= 7.\r
5a3641bf CC	97	/// Bits 15:4 - Reserved\r
cf1d4549	98	///\r
111f2228	99	UINT16 ImageAttribute;\r
cf1d4549 JY	100	///\r
cf1d4549 JY	101	/// Byte 0x22: Attributes of the FSP Component.\r
5a3641bf CC	102	/// Bit 0 - Build Type\r
	103	/// 0 - Debug Build\r
	104	/// 1 - Release Build\r
	105	/// Bit 1 - Release Type\r
	106	/// 0 - Test Release\r
	107	/// 1 - Official Release\r
	108	/// Bit 11:2 - Reserved\r
	109	/// Bits 15:12 - Component Type\r
	110	/// 0000 - Reserved\r
	111	/// 0001 - FSP-T\r
	112	/// 0010 - FSP-M\r
	113	/// 0011 - FSP-S\r
	114	/// 0100 - FSP-I (FSP SMM)\r
	115	/// 0101 to 0111 - Reserved\r
	116	/// 1000 - FSP-O\r
	117	/// 1001 to 1111 - Reserved\r
cf1d4549	118	///\r
111f2228	119	UINT16 ComponentAttribute;\r
cf1d4549 JY	120	///\r
	121	/// Byte 0x24: Offset of the FSP configuration region.\r
	122	///\r
111f2228	123	UINT32 CfgRegionOffset;\r
cf1d4549 JY	124	///\r
	125	/// Byte 0x28: Size of the FSP configuration region.\r
	126	///\r
111f2228	127	UINT32 CfgRegionSize;\r
cf1d4549 JY	128	///\r
	129	/// Byte 0x2C: Reserved2.\r
	130	///\r
111f2228	131	UINT32 Reserved2;\r
cf1d4549 JY	132	///\r
	133	/// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.\r
	134	///\r
111f2228	135	UINT32 TempRamInitEntryOffset;\r
cf1d4549 JY	136	///\r
	137	/// Byte 0x34: Reserved3.\r
	138	///\r
111f2228	139	UINT32 Reserved3;\r
cf1d4549 JY	140	///\r
	141	/// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.\r
	142	///\r
111f2228	143	UINT32 NotifyPhaseEntryOffset;\r
cf1d4549 JY	144	///\r
	145	/// Byte 0x3C: The offset for the API to initialize the memory.\r
	146	///\r
111f2228	147	UINT32 FspMemoryInitEntryOffset;\r
cf1d4549 JY	148	///\r
	149	/// Byte 0x40: The offset for the API to tear down temporary RAM.\r
	150	///\r
111f2228	151	UINT32 TempRamExitEntryOffset;\r
cf1d4549 JY	152	///\r
	153	/// Byte 0x44: The offset for the API to initialize the CPU and chipset.\r
	154	///\r
111f2228	155	UINT32 FspSiliconInitEntryOffset;\r
f2cdb268 CC	156	///\r
	157	/// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.\r
	158	/// This value is only valid if FSP HeaderRevision is >= 5.\r
	159	/// If the value is set to 0x00000000, then this API is not available in this component.\r
	160	///\r
111f2228	161	UINT32 FspMultiPhaseSiInitEntryOffset;\r
4cc1458d CC	162	///\r
	163	/// Byte 0x4C: Extended revision of the FSP binary.\r
	164	/// This value is only valid if FSP HeaderRevision is >= 6.\r
	165	/// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.\r
	166	/// 7 : 0 - High Byte of Build Number\r
	167	/// 15 : 8 - High Byte of Revision\r
	168	/// The FSP binary build number can be decoded as follows:\r
	169	/// Build Number = (ExtendedImageRevision[7:0] << 8) \| ImageRevision[7:0]\r
	170	/// Revision = (ExtendedImageRevision[15:8] << 8) \| ImageRevision[15:8]\r
	171	/// Minor Version = ImageRevision[23:16]\r
	172	/// Major Version = ImageRevision[31:24]\r
	173	///\r
111f2228	174	UINT16 ExtendedImageRevision;\r
4cc1458d CC	175	///\r
	176	/// Byte 0x4E: Reserved4.\r
	177	///\r
111f2228	178	UINT16 Reserved4;\r
48249243 HZ	179	///\r
	180	/// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.\r
	181	///\r
	182	UINT32 FspMultiPhaseMemInitEntryOffset;\r
	183	///\r
	184	/// Byte 0x54: Offset for the API to initialize SMM.\r
	185	///\r
	186	UINT32 FspSmmInitEntryOffset;\r
cf1d4549 JY	187	} FSP_INFO_HEADER;\r
	188	\r
	189	///\r
	190	/// Signature of the FSP Extended Header\r
	191	///\r
	192	#define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')\r
	193	\r
	194	///\r
	195	/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.\r
	196	///\r
	197	typedef struct {\r
	198	///\r
	199	/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.\r
	200	///\r
111f2228	201	UINT32 Signature;\r
cf1d4549 JY	202	///\r
	203	/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.\r
	204	///\r
111f2228	205	UINT32 Length;\r
cf1d4549 JY	206	///\r
	207	/// Byte 0x08: FSP producer defined revision of the table.\r
	208	///\r
111f2228	209	UINT8 Revision;\r
cf1d4549 JY	210	///\r
	211	/// Byte 0x09: Reserved for future use.\r
	212	///\r
111f2228	213	UINT8 Reserved;\r
cf1d4549	214	///\r
e37bb20c	215	/// Byte 0x0A: FSP producer identification string\r
cf1d4549	216	///\r
111f2228	217	CHAR8 FspProducerId[6];\r
cf1d4549 JY	218	///\r
	219	/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.\r
	220	///\r
111f2228	221	UINT32 FspProducerRevision;\r
cf1d4549 JY	222	///\r
	223	/// Byte 0x14: Size of the FSP producer defined data (n) in bytes.\r
	224	///\r
111f2228	225	UINT32 FspProducerDataSize;\r
cf1d4549 JY	226	///\r
	227	/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.\r
	228	///\r
	229	} FSP_INFO_EXTENDED_HEADER;\r
	230	\r
	231	//\r
	232	// A generic table search algorithm for additional tables can be implemented with a\r
	233	// signature search algorithm until a terminator signature 'FSPP' is found.\r
	234	//\r
111f2228	235	#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')\r
cf1d4549 JY	236	#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE\r
	237	\r
	238	///\r
	239	/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.\r
	240	///\r
	241	typedef struct {\r
	242	///\r
	243	/// Byte 0x00: FSP Patch Table Signature "FSPP".\r
	244	///\r
111f2228	245	UINT32 Signature;\r
cf1d4549 JY	246	///\r
	247	/// Byte 0x04: Size including the PatchData.\r
	248	///\r
111f2228	249	UINT16 HeaderLength;\r
cf1d4549 JY	250	///\r
	251	/// Byte 0x06: Revision is set to 0x01.\r
	252	///\r
111f2228	253	UINT8 HeaderRevision;\r
cf1d4549 JY	254	///\r
	255	/// Byte 0x07: Reserved for future use.\r
	256	///\r
111f2228	257	UINT8 Reserved;\r
cf1d4549 JY	258	///\r
	259	/// Byte 0x08: Number of entries to Patch.\r
	260	///\r
111f2228	261	UINT32 PatchEntryNum;\r
cf1d4549 JY	262	///\r
	263	/// Byte 0x0C: Patch Data.\r
	264	///\r
111f2228	265	// UINT32 PatchData[];\r
cf1d4549 JY	266	} FSP_PATCH_TABLE;\r
cf1d4549 JY	267	\r
48249243	268	#pragma pack()\r
cf1d4549	269	\r
111f2228	270	extern EFI_GUID gFspHeaderFileGuid;\r
cf1d4549 JY	271	\r
cf1d4549 JY	272	#endif\r