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cf1d4549 JY |
1 | ;------------------------------------------------------------------------------\r |
2 | ;\r | |
3 | ; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | ; This program and the accompanying materials\r | |
5 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
6 | ; which accompanies this distribution. The full text of the license may be found at\r | |
7 | ; http://opensource.org/licenses/bsd-license.php.\r | |
8 | ;\r | |
9 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | ;\r | |
12 | ; Module Name:\r | |
13 | ;\r | |
14 | ; PeiCoreEntry.asm\r | |
15 | ;\r | |
16 | ; Abstract:\r | |
17 | ;\r | |
18 | ; Find and call SecStartup\r | |
19 | ;\r | |
20 | ;------------------------------------------------------------------------------\r | |
21 | \r | |
22 | .686p\r | |
23 | .xmm\r | |
24 | .model flat, c\r | |
25 | .code\r | |
26 | \r | |
27 | EXTRN SecStartup:NEAR\r | |
28 | EXTRN PlatformInit:NEAR\r | |
29 | \r | |
30 | CallPeiCoreEntryPoint PROC PUBLIC\r | |
31 | ;\r | |
32 | ; Obtain the hob list pointer\r | |
33 | ;\r | |
34 | mov eax, [esp+4]\r | |
35 | ;\r | |
36 | ; Obtain the stack information\r | |
37 | ; ECX: start of range\r | |
38 | ; EDX: end of range\r | |
39 | ;\r | |
40 | mov ecx, [esp+8]\r | |
41 | mov edx, [esp+0Ch]\r | |
42 | \r | |
43 | ;\r | |
44 | ; Platform init\r | |
45 | ;\r | |
46 | pushad\r | |
47 | push edx\r | |
48 | push ecx\r | |
49 | push eax\r | |
50 | call PlatformInit\r | |
51 | pop eax\r | |
52 | pop eax\r | |
53 | pop eax\r | |
54 | popad\r | |
55 | \r | |
56 | ;\r | |
57 | ; Set stack top pointer\r | |
58 | ;\r | |
59 | mov esp, edx\r | |
60 | \r | |
61 | ;\r | |
62 | ; Push the hob list pointer\r | |
63 | ;\r | |
64 | push eax\r | |
65 | \r | |
66 | ;\r | |
67 | ; Save the value\r | |
68 | ; ECX: start of range\r | |
69 | ; EDX: end of range\r | |
70 | ;\r | |
71 | mov ebp, esp\r | |
72 | push ecx\r | |
73 | push edx\r | |
74 | \r | |
75 | ;\r | |
76 | ; Push processor count to stack first, then BIST status (AP then BSP)\r | |
77 | ;\r | |
78 | mov eax, 1\r | |
79 | cpuid\r | |
80 | shr ebx, 16\r | |
81 | and ebx, 0000000FFh\r | |
82 | cmp bl, 1\r | |
83 | jae PushProcessorCount\r | |
84 | \r | |
85 | ;\r | |
86 | ; Some processors report 0 logical processors. Effectively 0 = 1.\r | |
87 | ; So we fix up the processor count\r | |
88 | ;\r | |
89 | inc ebx\r | |
90 | \r | |
91 | PushProcessorCount:\r | |
92 | push ebx\r | |
93 | \r | |
94 | ;\r | |
95 | ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST\r | |
96 | ; for all processor threads\r | |
97 | ;\r | |
98 | xor ecx, ecx\r | |
99 | mov cl, bl\r | |
100 | PushBist:\r | |
101 | movd eax, mm0\r | |
102 | push eax\r | |
103 | loop PushBist\r | |
104 | \r | |
105 | ; Save Time-Stamp Counter\r | |
106 | movd eax, mm5\r | |
107 | push eax\r | |
108 | \r | |
109 | movd eax, mm6\r | |
110 | push eax\r | |
111 | \r | |
112 | ;\r | |
113 | ; Pass entry point of the PEI core\r | |
114 | ;\r | |
115 | mov edi, 0FFFFFFE0h\r | |
116 | push DWORD PTR ds:[edi]\r | |
117 | \r | |
118 | ;\r | |
119 | ; Pass BFV into the PEI Core\r | |
120 | ;\r | |
121 | mov edi, 0FFFFFFFCh\r | |
122 | push DWORD PTR ds:[edi]\r | |
123 | \r | |
124 | ;\r | |
125 | ; Pass stack size into the PEI Core\r | |
126 | ;\r | |
127 | mov ecx, [ebp - 4]\r | |
128 | mov edx, [ebp - 8]\r | |
129 | push ecx ; RamBase\r | |
130 | \r | |
131 | sub edx, ecx\r | |
132 | push edx ; RamSize\r | |
133 | \r | |
134 | ;\r | |
135 | ; Pass Control into the PEI Core\r | |
136 | ;\r | |
137 | call SecStartup\r | |
138 | CallPeiCoreEntryPoint ENDP\r | |
139 | \r | |
140 | END\r |