projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2d24f4e7 LG |
1 | ;------------------------------------------------------------------------------\r |
| 2 | ;\r | |
| 3 | ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 512e23a3 | 4 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 2d24f4e7 LG |
5 | ;\r |
| 6 | ; Module Name:\r | |
| 7 | ;\r | |
| 8 | ; PeiCoreEntry.nasm\r | |
| 9 | ;\r | |
| 10 | ; Abstract:\r | |
| 11 | ;\r | |
| 12 | ; Find and call SecStartup\r | |
| 13 | ;\r | |
| 14 | ;------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | SECTION .text\r | |
| 17 | \r | |
| 18 | extern ASM_PFX(SecStartup)\r | |
| 19 | extern ASM_PFX(PlatformInit)\r | |
| 20 | \r | |
| 21 | global ASM_PFX(CallPeiCoreEntryPoint)\r | |
| 22 | ASM_PFX(CallPeiCoreEntryPoint):\r | |
| 23 | ;\r | |
| 24 | ; Obtain the hob list pointer\r | |
| 25 | ;\r | |
| 26 | mov eax, [esp+4]\r | |
| 27 | ;\r | |
| 28 | ; Obtain the stack information\r | |
| 29 | ; ECX: start of range\r | |
| 30 | ; EDX: end of range\r | |
| 31 | ;\r | |
| 32 | mov ecx, [esp+8]\r | |
| 33 | mov edx, [esp+0xC]\r | |
| 34 | \r | |
| 35 | ;\r | |
| 36 | ; Platform init\r | |
| 37 | ;\r | |
| 38 | pushad\r | |
| 39 | push edx\r | |
| 40 | push ecx\r | |
| 41 | push eax\r | |
| 42 | call ASM_PFX(PlatformInit)\r | |
| 43 | pop eax\r | |
| 44 | pop eax\r | |
| 45 | pop eax\r | |
| 46 | popad\r | |
| 47 | \r | |
| 48 | ;\r | |
| 49 | ; Set stack top pointer\r | |
| 50 | ;\r | |
| 51 | mov esp, edx\r | |
| 52 | \r | |
| 53 | ;\r | |
| 54 | ; Push the hob list pointer\r | |
| 55 | ;\r | |
| 56 | push eax\r | |
| 57 | \r | |
| 58 | ;\r | |
| 59 | ; Save the value\r | |
| 60 | ; ECX: start of range\r | |
| 61 | ; EDX: end of range\r | |
| 62 | ;\r | |
| 63 | mov ebp, esp\r | |
| 64 | push ecx\r | |
| 65 | push edx\r | |
| 66 | \r | |
| 67 | ;\r | |
| 68 | ; Push processor count to stack first, then BIST status (AP then BSP)\r | |
| 69 | ;\r | |
| 70 | mov eax, 1\r | |
| 71 | cpuid\r | |
| 72 | shr ebx, 16\r | |
| 73 | and ebx, 0xFF\r | |
| 74 | cmp bl, 1\r | |
| 75 | jae PushProcessorCount\r | |
| 76 | \r | |
| 77 | ;\r | |
| 78 | ; Some processors report 0 logical processors. Effectively 0 = 1.\r | |
| 79 | ; So we fix up the processor count\r | |
| 80 | ;\r | |
| 81 | inc ebx\r | |
| 82 | \r | |
| 83 | PushProcessorCount:\r | |
| 84 | push ebx\r | |
| 85 | \r | |
| 86 | ;\r | |
| 87 | ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST\r | |
| 88 | ; for all processor threads\r | |
| 89 | ;\r | |
| 90 | xor ecx, ecx\r | |
| 91 | mov cl, bl\r | |
| 92 | PushBist:\r | |
| 93 | movd eax, mm0\r | |
| 94 | push eax\r | |
| 95 | loop PushBist\r | |
| 96 | \r | |
| 97 | ; Save Time-Stamp Counter\r | |
| 98 | movd eax, mm5\r | |
| 99 | push eax\r | |
| 100 | \r | |
| 101 | movd eax, mm6\r | |
| 102 | push eax\r | |
| 103 | \r | |
| 104 | ;\r | |
| 105 | ; Pass entry point of the PEI core\r | |
| 106 | ;\r | |
| 107 | mov edi, 0xFFFFFFE0\r | |
| 108 | push DWORD [edi]\r | |
| 109 | \r | |
| 110 | ;\r | |
| 111 | ; Pass BFV into the PEI Core\r | |
| 112 | ;\r | |
| 113 | mov edi, 0xFFFFFFFC\r | |
| 114 | push DWORD [edi]\r | |
| 115 | \r | |
| 116 | ;\r | |
| 117 | ; Pass stack size into the PEI Core\r | |
| 118 | ;\r | |
| 119 | mov ecx, [ebp - 4]\r | |
| 120 | mov edx, [ebp - 8]\r | |
| 121 | push ecx ; RamBase\r | |
| 122 | \r | |
| 123 | sub edx, ecx\r | |
| 124 | push edx ; RamSize\r | |
| 125 | \r | |
| 126 | ;\r | |
| 127 | ; Pass Control into the PEI Core\r | |
| 128 | ;\r | |
| 129 | call ASM_PFX(SecStartup)\r | |
| 130 | \r |