MdeModulePkg: fix some issues in ScsiDisk to co-work with UFS stack
[mirror_edk2.git] / IntelFspPkg / FspSecCore / Ia32 / FspApiEntry.asm
CommitLineData
d5fb1edf
JY
1;; @file\r
2; Provide FSP API entry points.\r
c8ec22a2 3;\r
d5fb1edf 4; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
c8ec22a2
JY
5; This program and the accompanying materials\r
6; are licensed and made available under the terms and conditions of the BSD License\r
7; which accompanies this distribution. The full text of the license may be found at\r
8; http://opensource.org/licenses/bsd-license.php.\r
9;\r
10; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
d5fb1edf 12;;\r
c8ec22a2
JY
13\r
14 .586p\r
15 .model flat,C\r
16 .code\r
17 .xmm\r
18\r
19INCLUDE SaveRestoreSse.inc\r
9da59186 20INCLUDE MicrocodeLoad.inc\r
c8ec22a2
JY
21\r
22;\r
23; Following are fixed PCDs\r
24;\r
25EXTERN PcdGet32(PcdTemporaryRamBase):DWORD\r
26EXTERN PcdGet32(PcdTemporaryRamSize):DWORD\r
27EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD\r
d5fb1edf 28EXTERN PcdGet32(PcdFspAreaSize):DWORD\r
c8ec22a2
JY
29\r
30;\r
31; Following functions will be provided in C\r
32;\r
d5fb1edf 33\r
c8ec22a2
JY
34EXTERN SecStartup:PROC\r
35EXTERN FspApiCallingCheck:PROC\r
36\r
37;\r
38; Following functions will be provided in PlatformSecLib\r
39;\r
40EXTERN GetFspBaseAddress:PROC\r
41EXTERN GetBootFirmwareVolumeOffset:PROC\r
c8ec22a2 42EXTERN Pei2LoaderSwitchStack:PROC\r
9da59186 43EXTERN LoadMicrocode(LoadMicrocodeDefault):PROC\r
c030e74c 44EXTERN SecPlatformInit(SecPlatformInitDefault):PROC\r
d5fb1edf 45EXTERN SecCarInit:PROC\r
c8ec22a2
JY
46\r
47;\r
48; Define the data length that we saved on the stack top\r
49;\r
50DATA_LEN_OF_PER0 EQU 18h\r
51DATA_LEN_OF_MCUD EQU 18h\r
52DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r
53\r
d5fb1edf
JY
54;\r
55; Define SSE macros\r
56;\r
57LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister\r
58 mov esi, ReturnAddress\r
1c54ceb7 59 movd MmxRegister, esi ; save ReturnAddress into MMX\r
d5fb1edf
JY
60ENDM\r
61\r
62CALL_MMX_EXT MACRO RoutineLabel, MmxRegister\r
63 local ReturnAddress\r
64 mov esi, offset ReturnAddress\r
1c54ceb7 65 movd MmxRegister, esi ; save ReturnAddress into MMX\r
d5fb1edf
JY
66 jmp RoutineLabel\r
67ReturnAddress:\r
68ENDM\r
69\r
70RET_ESI_EXT MACRO MmxRegister\r
9da59186 71 movd esi, MmxRegister ; move ReturnAddress from MMX to ESI\r
d5fb1edf
JY
72 jmp esi\r
73ENDM\r
74\r
75CALL_MMX MACRO RoutineLabel\r
76 CALL_MMX_EXT RoutineLabel, mm7\r
77ENDM\r
78\r
79RET_ESI MACRO\r
9da59186 80 RET_ESI_EXT mm7\r
d5fb1edf
JY
81ENDM\r
82\r
c8ec22a2 83;------------------------------------------------------------------------------\r
c030e74c 84SecPlatformInitDefault PROC NEAR PUBLIC\r
c8ec22a2 85 ; Inputs:\r
1c54ceb7 86 ; mm7 -> Return address\r
c8ec22a2
JY
87 ; Outputs:\r
88 ; eax -> 0 - Successful, Non-zero - Failed.\r
89 ; Register Usage:\r
90 ; eax is cleared and ebp is used for return address.\r
91 ; All others reserved.\r
1c54ceb7 92 \r
c8ec22a2 93 ; Save return address to EBP\r
c0a8cf34 94 movd ebp, mm7\r
c8ec22a2
JY
95\r
96 xor eax, eax\r
97exit:\r
98 jmp ebp\r
c030e74c 99SecPlatformInitDefault ENDP\r
c8ec22a2
JY
100\r
101;------------------------------------------------------------------------------\r
9da59186 102LoadMicrocodeDefault PROC NEAR PUBLIC\r
c8ec22a2 103 ; Inputs:\r
9da59186 104 ; esp -> LoadMicrocodeParams pointer\r
c8ec22a2
JY
105 ; Register Usage:\r
106 ; esp Preserved\r
107 ; All others destroyed\r
108 ; Assumptions:\r
109 ; No memory available, stack is hard-coded and used for return address\r
110 ; Executed by SBSP and NBSP\r
111 ; Beginning of microcode update region starts on paragraph boundary\r
112\r
113 ;\r
114 ;\r
115 ; Save return address to EBP\r
d5fb1edf 116 movd ebp, mm7\r
c8ec22a2
JY
117\r
118 cmp esp, 0\r
119 jz paramerror\r
9da59186 120 mov eax, dword ptr [esp + 4] ; Parameter pointer\r
c8ec22a2
JY
121 cmp eax, 0\r
122 jz paramerror\r
123 mov esp, eax\r
9da59186 124 mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
c8ec22a2
JY
125 cmp esi, 0\r
126 jnz check_main_header\r
127\r
128paramerror:\r
129 mov eax, 080000002h\r
130 jmp exit\r
131\r
9da59186 132 mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
c8ec22a2
JY
133\r
134check_main_header:\r
135 ; Get processor signature and platform ID from the installed processor\r
136 ; and save into registers for later use\r
137 ; ebx = processor signature\r
138 ; edx = platform ID\r
139 mov eax, 1\r
140 cpuid\r
141 mov ebx, eax\r
142 mov ecx, MSR_IA32_PLATFORM_ID\r
143 rdmsr\r
144 mov ecx, edx\r
145 shr ecx, 50-32\r
146 and ecx, 7h\r
147 mov edx, 1\r
148 shl edx, cl\r
149\r
150 ; Current register usage\r
151 ; esp -> stack with paramters\r
152 ; esi -> microcode update to check\r
153 ; ebx = processor signature\r
154 ; edx = platform ID\r
155\r
156 ; Check for valid microcode header\r
157 ; Minimal test checking for header version and loader version as 1\r
158 mov eax, dword ptr 1\r
9da59186 159 cmp [esi].MicrocodeHdr.MicrocodeHdrVersion, eax\r
c8ec22a2 160 jne advance_fixed_size\r
9da59186 161 cmp [esi].MicrocodeHdr.MicrocodeHdrLoader, eax\r
c8ec22a2
JY
162 jne advance_fixed_size\r
163\r
164 ; Check if signature and plaform ID match\r
9da59186 165 cmp ebx, [esi].MicrocodeHdr.MicrocodeHdrProcessor\r
c8ec22a2 166 jne @f\r
9da59186 167 test edx, [esi].MicrocodeHdr.MicrocodeHdrFlags\r
c8ec22a2
JY
168 jnz load_check ; Jif signature and platform ID match\r
169\r
170@@:\r
171 ; Check if extended header exists\r
9da59186 172 ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r
c8ec22a2 173 xor eax, eax\r
9da59186 174 cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax\r
c8ec22a2 175 je next_microcode\r
9da59186 176 cmp [esi].MicrocodeHdr.MicrocodeHdrDataSize, eax\r
c8ec22a2
JY
177 je next_microcode\r
178\r
179 ; Then verify total size - sizeof header > data size\r
9da59186
JY
180 mov ecx, [esi].MicrocodeHdr.MicrocodeHdrTotalSize\r
181 sub ecx, sizeof MicrocodeHdr\r
182 cmp ecx, [esi].MicrocodeHdr.MicrocodeHdrDataSize\r
c8ec22a2
JY
183 jng next_microcode ; Jif extended header does not exist\r
184\r
185 ; Set edi -> extended header\r
186 mov edi, esi\r
9da59186
JY
187 add edi, sizeof MicrocodeHdr\r
188 add edi, [esi].MicrocodeHdr.MicrocodeHdrDataSize\r
c8ec22a2
JY
189\r
190 ; Get count of extended structures\r
9da59186 191 mov ecx, [edi].ExtSigHdr.ExtSigHdrCount\r
c8ec22a2
JY
192\r
193 ; Move pointer to first signature structure\r
9da59186 194 add edi, sizeof ExtSigHdr\r
c8ec22a2
JY
195\r
196check_ext_sig:\r
197 ; Check if extended signature and platform ID match\r
9da59186 198 cmp [edi].ExtSig.ExtSigProcessor, ebx\r
c8ec22a2 199 jne @f\r
9da59186 200 test [edi].ExtSig.ExtSigFlags, edx\r
c8ec22a2
JY
201 jnz load_check ; Jif signature and platform ID match\r
202@@:\r
203 ; Check if any more extended signatures exist\r
9da59186 204 add edi, sizeof ExtSig\r
c8ec22a2
JY
205 loop check_ext_sig\r
206\r
207next_microcode:\r
208 ; Advance just after end of this microcode\r
209 xor eax, eax\r
9da59186 210 cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax\r
c8ec22a2 211 je @f\r
9da59186 212 add esi, [esi].MicrocodeHdr.MicrocodeHdrTotalSize\r
c8ec22a2
JY
213 jmp check_address\r
214@@:\r
215 add esi, dword ptr 2048\r
216 jmp check_address\r
217\r
218advance_fixed_size:\r
219 ; Advance by 4X dwords\r
220 add esi, dword ptr 1024\r
221\r
222check_address:\r
223 ; Is valid Microcode start point ?\r
9da59186 224 cmp dword ptr [esi].MicrocodeHdr.MicrocodeHdrVersion, 0ffffffffh\r
c8ec22a2
JY
225 jz done\r
226\r
975f1c64 227 ; Is automatic size detection ?\r
9da59186 228 mov eax, [esp].LoadMicrocodeParams.MicrocodeCodeSize\r
975f1c64
JY
229 cmp eax, 0ffffffffh\r
230 jz @f\r
231\r
c8ec22a2 232 ; Address >= microcode region address + microcode region size?\r
9da59186 233 add eax, [esp].LoadMicrocodeParams.MicrocodeCodeAddr\r
c8ec22a2 234 cmp esi, eax\r
9da59186 235 jae done ;Jif address is outside of microcode region\r
c8ec22a2
JY
236 jmp check_main_header\r
237\r
975f1c64 238@@:\r
c8ec22a2
JY
239load_check:\r
240 ; Get the revision of the current microcode update loaded\r
241 mov ecx, MSR_IA32_BIOS_SIGN_ID\r
242 xor eax, eax ; Clear EAX\r
243 xor edx, edx ; Clear EDX\r
244 wrmsr ; Load 0 to MSR at 8Bh\r
245\r
246 mov eax, 1\r
247 cpuid\r
248 mov ecx, MSR_IA32_BIOS_SIGN_ID\r
249 rdmsr ; Get current microcode signature\r
250\r
251 ; Verify this microcode update is not already loaded\r
9da59186 252 cmp [esi].MicrocodeHdr.MicrocodeHdrRevision, edx\r
c8ec22a2
JY
253 je continue\r
254\r
255load_microcode:\r
256 ; EAX contains the linear address of the start of the Update Data\r
257 ; EDX contains zero\r
258 ; ECX contains 79h (IA32_BIOS_UPDT_TRIG)\r
259 ; Start microcode load with wrmsr\r
260 mov eax, esi\r
9da59186 261 add eax, sizeof MicrocodeHdr\r
c8ec22a2
JY
262 xor edx, edx\r
263 mov ecx, MSR_IA32_BIOS_UPDT_TRIG\r
264 wrmsr\r
265 mov eax, 1\r
266 cpuid\r
267\r
268continue:\r
269 jmp next_microcode\r
270\r
271done:\r
272 mov eax, 1\r
273 cpuid\r
274 mov ecx, MSR_IA32_BIOS_SIGN_ID\r
275 rdmsr ; Get current microcode signature\r
276 xor eax, eax\r
277 cmp edx, 0\r
278 jnz exit\r
279 mov eax, 08000000Eh\r
280\r
281exit:\r
282 jmp ebp\r
283\r
9da59186 284LoadMicrocodeDefault ENDP\r
c8ec22a2 285\r
d5fb1edf 286EstablishStackFsp PROC NEAR PRIVATE\r
d5fb1edf 287 ;\r
9da59186 288 ; Save parameter pointer in edx\r
d5fb1edf 289 ;\r
9da59186
JY
290 mov edx, dword ptr [esp + 4]\r
291\r
d5fb1edf
JY
292 ;\r
293 ; Enable FSP STACK\r
294 ;\r
295 mov esp, PcdGet32 (PcdTemporaryRamBase)\r
9da59186 296 add esp, PcdGet32 (PcdTemporaryRamSize)\r
d5fb1edf 297\r
9da59186 298 push DATA_LEN_OF_MCUD ; Size of the data region\r
d5fb1edf
JY
299 push 4455434Dh ; Signature of the data region 'MCUD'\r
300 push dword ptr [edx + 12] ; Code size\r
301 push dword ptr [edx + 8] ; Code base\r
d5fb1edf 302 push dword ptr [edx + 4] ; Microcode size\r
9da59186 303 push dword ptr [edx] ; Microcode base\r
d5fb1edf 304\r
d5fb1edf
JY
305 ;\r
306 ; Save API entry/exit timestamp into stack\r
307 ;\r
308 push DATA_LEN_OF_PER0 ; Size of the data region \r
309 push 30524550h ; Signature of the data region 'PER0'\r
95c95ac0
JY
310 LOAD_EDX\r
311 push edx\r
312 LOAD_EAX\r
d5fb1edf
JY
313 push eax\r
314 rdtsc\r
315 push edx\r
316 push eax\r
317\r
318 ;\r
319 ; Terminator for the data on stack\r
320 ; \r
321 push 0\r
322\r
323 ;\r
9da59186 324 ; Set ECX/EDX to the BootLoader temporary memory range\r
d5fb1edf
JY
325 ;\r
326 mov ecx, PcdGet32 (PcdTemporaryRamBase)\r
327 mov edx, ecx\r
328 add edx, PcdGet32 (PcdTemporaryRamSize)\r
329 sub edx, PcdGet32 (PcdFspTemporaryRamSize)\r
330\r
331 xor eax, eax\r
9da59186 332\r
d5fb1edf
JY
333 RET_ESI\r
334\r
335EstablishStackFsp ENDP\r
336\r
337\r
c8ec22a2
JY
338;----------------------------------------------------------------------------\r
339; TempRamInit API\r
340;\r
341; This FSP API will load the microcode update, enable code caching for the\r
342; region specified by the boot loader and also setup a temporary stack to be\r
343; used till main memory is initialized.\r
344;\r
345;----------------------------------------------------------------------------\r
346TempRamInitApi PROC NEAR PUBLIC\r
347 ;\r
348 ; Ensure SSE is enabled\r
349 ;\r
350 ENABLE_SSE\r
351\r
352 ;\r
353 ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6\r
354 ;\r
355 SAVE_REGS\r
356\r
357 ;\r
1c54ceb7 358 ; Save timestamp into XMM6\r
c8ec22a2
JY
359 ;\r
360 rdtsc\r
95c95ac0
JY
361 SAVE_EAX\r
362 SAVE_EDX\r
363\r
364 ;\r
365 ; Check Parameter\r
366 ;\r
367 mov eax, dword ptr [esp + 4]\r
368 cmp eax, 0\r
369 mov eax, 80000002h\r
370 jz NemInitExit\r
371\r
c8ec22a2
JY
372 ;\r
373 ; CPUID/DeviceID check\r
9da59186 374 ; and Sec Platform Init\r
c8ec22a2 375 ;\r
d5fb1edf 376 CALL_MMX SecPlatformInit\r
95c95ac0
JY
377 cmp eax, 0\r
378 jnz NemInitExit\r
d5fb1edf 379 \r
c8ec22a2 380 ; Load microcode\r
95c95ac0 381 LOAD_ESP\r
9da59186
JY
382 CALL_MMX LoadMicrocode\r
383 SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.\r
384 ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r
95c95ac0
JY
385\r
386 ; Call Sec CAR Init\r
387 LOAD_ESP\r
388 CALL_MMX SecCarInit\r
389 cmp eax, 0\r
390 jnz NemInitExit\r
c8ec22a2 391\r
95c95ac0 392 LOAD_ESP\r
d5fb1edf 393 CALL_MMX EstablishStackFsp\r
c8ec22a2 394\r
9da59186
JY
395 LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
396\r
c8ec22a2
JY
397NemInitExit:\r
398 ;\r
399 ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r
400 ;\r
401 LOAD_REGS\r
402 ret\r
403TempRamInitApi ENDP\r
404\r
405;----------------------------------------------------------------------------\r
406; FspInit API\r
407;\r
408; This FSP API will perform the processor and chipset initialization.\r
409; This API will not return. Instead, it transfers the control to the\r
410; ContinuationFunc provided in the parameter.\r
411;\r
412;----------------------------------------------------------------------------\r
413FspInitApi PROC NEAR PUBLIC\r
d5fb1edf
JY
414 mov eax, 1\r
415 jmp FspApiCommon\r
416 FspInitApi ENDP\r
417\r
418;----------------------------------------------------------------------------\r
419; NotifyPhase API\r
420;\r
421; This FSP API will notify the FSP about the different phases in the boot\r
422; process\r
423;\r
424;----------------------------------------------------------------------------\r
425NotifyPhaseApi PROC C PUBLIC\r
426 mov eax, 2\r
427 jmp FspApiCommon\r
428NotifyPhaseApi ENDP\r
429\r
430;----------------------------------------------------------------------------\r
431; FspMemoryInit API\r
432;\r
433; This FSP API is called after TempRamInit and initializes the memory.\r
434;\r
435;----------------------------------------------------------------------------\r
436FspMemoryInitApi PROC NEAR PUBLIC\r
437 mov eax, 3\r
438 jmp FspApiCommon\r
439FspMemoryInitApi ENDP\r
440\r
441\r
442;----------------------------------------------------------------------------\r
443; TempRamExitApi API\r
444;\r
445; This API tears down temporary RAM\r
446;\r
447;----------------------------------------------------------------------------\r
448TempRamExitApi PROC C PUBLIC\r
449 mov eax, 4\r
450 jmp FspApiCommon\r
451TempRamExitApi ENDP\r
452\r
453\r
454;----------------------------------------------------------------------------\r
455; FspSiliconInit API\r
456;\r
457; This FSP API initializes the CPU and the chipset including the IO\r
458; controllers in the chipset to enable normal operation of these devices.\r
459;\r
460;----------------------------------------------------------------------------\r
461FspSiliconInitApi PROC C PUBLIC\r
462 mov eax, 5\r
463 jmp FspApiCommon\r
464FspSiliconInitApi ENDP\r
465\r
466;----------------------------------------------------------------------------\r
467; FspApiCommon API\r
468;\r
469; This is the FSP API common entry point to resume the FSP execution\r
470;\r
471;----------------------------------------------------------------------------\r
472FspApiCommon PROC C PUBLIC\r
c8ec22a2 473 ;\r
d5fb1edf 474 ; EAX holds the API index\r
c8ec22a2 475 ;\r
d5fb1edf
JY
476\r
477 ;\r
478 ; Stack must be ready\r
479 ; \r
480 push eax\r
481 add esp, 4\r
482 cmp eax, dword ptr [esp - 4]\r
c8ec22a2
JY
483 jz @F\r
484 mov eax, 080000003h\r
485 jmp exit\r
486\r
487@@:\r
488 ;\r
d5fb1edf 489 ; Verify the calling condition\r
c8ec22a2
JY
490 ;\r
491 pushad\r
9da59186 492 push [esp + 4 * 8 + 4]\r
d5fb1edf 493 push eax\r
c8ec22a2 494 call FspApiCallingCheck\r
9da59186 495 add esp, 8\r
c8ec22a2
JY
496 cmp eax, 0\r
497 jz @F\r
d5fb1edf
JY
498 mov dword ptr [esp + 4 * 7], eax\r
499 popad\r
500 ret\r
c8ec22a2
JY
501\r
502@@:\r
d5fb1edf
JY
503 popad\r
504 cmp eax, 1 ; FspInit API\r
505 jz @F\r
506 cmp eax, 3 ; FspMemoryInit API\r
507 jz @F\r
508 jmp Pei2LoaderSwitchStack\r
509\r
9da59186 510@@:\r
d5fb1edf
JY
511 ;\r
512 ; FspInit and FspMemoryInit APIs, setup the initial stack frame\r
9da59186 513 ;\r
d5fb1edf 514 \r
c8ec22a2
JY
515 ;\r
516 ; Store the address in FSP which will return control to the BL\r
517 ;\r
518 push offset exit\r
519\r
520 ;\r
521 ; Create a Task Frame in the stack for the Boot Loader\r
522 ;\r
523 pushfd ; 2 pushf for 4 byte alignment\r
524 cli\r
525 pushad\r
526\r
527 ; Reserve 8 bytes for IDT save/restore\r
528 sub esp, 8\r
9da59186 529 sidt fword ptr [esp]\r
c8ec22a2
JY
530\r
531 ;\r
532 ; Setup new FSP stack\r
533 ;\r
d5fb1edf 534 mov edi, esp\r
c8ec22a2
JY
535 mov esp, PcdGet32(PcdTemporaryRamBase)\r
536 add esp, PcdGet32(PcdTemporaryRamSize)\r
537 sub esp, (DATA_LEN_AT_STACK_TOP + 40h)\r
538\r
539 ;\r
d5fb1edf 540 ; Pass the API Idx to SecStartup\r
c8ec22a2
JY
541 ;\r
542 push eax\r
d5fb1edf
JY
543 \r
544 ;\r
9da59186 545 ; Pass the BootLoader stack to SecStartup\r
d5fb1edf
JY
546 ;\r
547 push edi\r
c8ec22a2
JY
548\r
549 ;\r
550 ; Pass entry point of the PEI core\r
551 ;\r
552 call GetFspBaseAddress\r
d5fb1edf
JY
553 mov edi, eax\r
554 add edi, PcdGet32 (PcdFspAreaSize) \r
c8ec22a2 555 sub edi, 20h\r
d5fb1edf 556 add eax, DWORD PTR ds:[edi]\r
c8ec22a2
JY
557 push eax\r
558\r
559 ;\r
560 ; Pass BFV into the PEI Core\r
561 ; It uses relative address to calucate the actual boot FV base\r
562 ; For FSP impleantion with single FV, PcdFlashFvRecoveryBase and\r
563 ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,\r
564 ; they are different. The code below can handle both cases.\r
565 ;\r
566 call GetFspBaseAddress\r
567 mov edi, eax\r
568 call GetBootFirmwareVolumeOffset\r
569 add eax, edi\r
570 push eax\r
571\r
572 ;\r
573 ; Pass stack base and size into the PEI Core\r
574 ;\r
575 mov eax, PcdGet32(PcdTemporaryRamBase)\r
576 add eax, PcdGet32(PcdTemporaryRamSize)\r
577 sub eax, PcdGet32(PcdFspTemporaryRamSize)\r
578 push eax\r
579 push PcdGet32(PcdFspTemporaryRamSize)\r
580\r
581 ;\r
582 ; Pass Control into the PEI Core\r
583 ;\r
584 call SecStartup\r
585\r
9da59186 586exit:\r
c8ec22a2
JY
587 ret\r
588\r
d5fb1edf 589FspApiCommon ENDP\r
c8ec22a2
JY
590\r
591END\r