projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| c8ec22a2 JY |
1 | #------------------------------------------------------------------------------\r |
| 2 | #\r | |
| d5fb1edf | 3 | # Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r |
| c8ec22a2 JY |
4 | # This program and the accompanying materials\r |
| 5 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 6 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 7 | # http://opensource.org/licenses/bsd-license.php.\r | |
| 8 | #\r | |
| 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 11 | #\r | |
| 12 | # Abstract:\r | |
| 13 | #\r | |
| 14 | #------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | #\r | |
| 17 | # Float control word initial value:\r | |
| 18 | # all exceptions masked, double-precision, round-to-nearest\r | |
| 19 | #\r | |
| 20 | ASM_PFX(mFpuControlWord): .word 0x027F\r | |
| 21 | #\r | |
| 22 | # Multimedia-extensions control word:\r | |
| 23 | # all exceptions masked, round-to-nearest, flush to zero for masked underflow\r | |
| 24 | #\r | |
| 25 | ASM_PFX(mMmxControlWord): .long 0x01F80\r | |
| 26 | \r | |
| 27 | \r | |
| 28 | \r | |
| 29 | #\r | |
| 30 | # Initializes floating point units for requirement of UEFI specification.\r | |
| 31 | #\r | |
| 32 | # This function initializes floating-point control word to 0x027F (all exceptions\r | |
| 33 | # masked,double-precision, round-to-nearest) and multimedia-extensions control word\r | |
| 34 | # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r | |
| 35 | # for masked underflow).\r | |
| 36 | #\r | |
| 37 | ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)\r | |
| 38 | ASM_PFX(InitializeFloatingPointUnits):\r | |
| 39 | \r | |
| 40 | pushl %ebx\r | |
| 41 | \r | |
| 42 | #\r | |
| 43 | # Initialize floating point units\r | |
| 44 | #\r | |
| 45 | finit\r | |
| 46 | fldcw ASM_PFX(mFpuControlWord)\r | |
| 47 | \r | |
| 48 | #\r | |
| 49 | # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r | |
| 50 | # whether the processor supports SSE instruction.\r | |
| 51 | #\r | |
| 52 | movl $1, %eax\r | |
| 53 | cpuid\r | |
| 54 | btl $25, %edx\r | |
| 55 | jnc Done\r | |
| 56 | \r | |
| 57 | #\r | |
| 58 | # Set OSFXSR bit 9 in CR4\r | |
| 59 | #\r | |
| 60 | movl %cr4, %eax\r | |
| d5fb1edf | 61 | orl $BIT9, %eax\r |
| c8ec22a2 JY |
62 | movl %eax, %cr4\r |
| 63 | \r | |
| 64 | #\r | |
| 65 | # The processor should support SSE instruction and we can use\r | |
| 66 | # ldmxcsr instruction\r | |
| 67 | #\r | |
| 68 | ldmxcsr ASM_PFX(mMmxControlWord)\r | |
| 69 | \r | |
| 70 | Done:\r | |
| 71 | popl %ebx\r | |
| 72 | \r | |
| 73 | ret\r |