projects / mirror_edk2.git / blame
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|---|---|---|
| a33a2f62 JY |
1 | /** @file\r |
| 2 | Intel FSP Info Header definition from Intel Firmware Support Package External\r | |
| 3 | Architecture Specification, April 2014, revision 001.\r | |
| 4 | \r | |
| 5 | Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php.\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef _FSP_INFO_HEADER_H_\r | |
| 17 | #define _FSP_INFO_HEADER_H_\r | |
| 18 | \r | |
| 19 | ///\r | |
| 20 | /// Fixed FSP header offset in the FSP image\r | |
| 21 | ///\r | |
| 22 | #define FSP_INFO_HEADER_OFF 0x94\r | |
| 23 | \r | |
| 24 | #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r | |
| 25 | \r | |
| 26 | #pragma pack(1)\r | |
| 27 | \r | |
| 28 | typedef struct {\r | |
| 29 | ///\r | |
| 30 | /// Signature ('FSPH') for the FSP Information Header\r | |
| 31 | ///\r | |
| 32 | UINT32 Signature;\r | |
| 33 | ///\r | |
| 34 | /// Length of the FSP Information Header\r | |
| 35 | ///\r | |
| 36 | UINT32 HeaderLength;\r | |
| 37 | ///\r | |
| 38 | /// Reserved\r | |
| 39 | ///\r | |
| 40 | UINT8 Reserved1[3];\r | |
| 41 | ///\r | |
| 42 | /// Revision of the FSP Information Header\r | |
| 43 | ///\r | |
| 44 | UINT8 HeaderRevision;\r | |
| 45 | ///\r | |
| 46 | /// Revision of the FSP binary\r | |
| 47 | ///\r | |
| 48 | UINT32 ImageRevision;\r | |
| 49 | \r | |
| 50 | \r | |
| 51 | ///\r | |
| 52 | /// Signature string that will help match the FSP Binary to a supported\r | |
| 53 | /// hardware configuration.\r | |
| 54 | ///\r | |
| 55 | CHAR8 ImageId[8];\r | |
| 56 | ///\r | |
| 57 | /// Size of the entire FSP binary\r | |
| 58 | ///\r | |
| 59 | UINT32 ImageSize;\r | |
| 60 | ///\r | |
| 61 | /// FSP binary preferred base address\r | |
| 62 | ///\r | |
| 63 | UINT32 ImageBase;\r | |
| 64 | \r | |
| 65 | \r | |
| 66 | ///\r | |
| 67 | /// Attribute for the FSP binary\r | |
| 68 | ///\r | |
| 69 | UINT32 ImageAttribute;\r | |
| 70 | ///\r | |
| 71 | /// Offset of the FSP configuration region\r | |
| 72 | ///\r | |
| 73 | UINT32 CfgRegionOffset;\r | |
| 74 | ///\r | |
| 75 | /// Size of the FSP configuration region\r | |
| 76 | ///\r | |
| 77 | UINT32 CfgRegionSize;\r | |
| 78 | ///\r | |
| 79 | /// Number of API entries this FSP supports\r | |
| 80 | ///\r | |
| 81 | UINT32 ApiEntryNum;\r | |
| 82 | \r | |
| 83 | \r | |
| 84 | ///\r | |
| 85 | /// TempRamInit API entry offset\r | |
| 86 | ///\r | |
| 87 | UINT32 TempRamInitEntryOffset;\r | |
| 88 | ///\r | |
| 89 | /// FspInit API entry offset\r | |
| 90 | ///\r | |
| 91 | UINT32 FspInitEntryOffset;\r | |
| 92 | ///\r | |
| 93 | /// NotifyPhase API entry offset\r | |
| 94 | ///\r | |
| 95 | UINT32 NotifyPhaseEntryOffset;\r | |
| 96 | ///\r | |
| 97 | /// Reserved\r | |
| 98 | ///\r | |
| 99 | UINT32 Reserved2;\r | |
| 100 | \r | |
| 101 | } FSP_INFO_HEADER;\r | |
| 102 | \r | |
| 103 | #pragma pack()\r | |
| 104 | \r | |
| 105 | #endif\r |