projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a33a2f62 JY |
1 | #------------------------------------------------------------------------------\r |
| 2 | #\r | |
| 3 | # Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 19486360 | 4 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| a33a2f62 JY |
5 | #\r |
| 6 | # Module Name:\r | |
| 7 | #\r | |
| 8 | # PeiCoreEntry.S\r | |
| 9 | #\r | |
| 10 | # Abstract:\r | |
| 11 | #\r | |
| 12 | # Find and call SecStartup\r | |
| 13 | #\r | |
| 14 | #------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)\r | |
| 17 | ASM_PFX(CallPeiCoreEntryPoint):\r | |
| 18 | #\r | |
| 19 | # Obtain the hob list pointer\r | |
| 20 | #\r | |
| 21 | movl 0x4(%esp), %eax\r | |
| 22 | #\r | |
| 23 | # Obtain the stack information\r | |
| 24 | # ECX: start of range\r | |
| 25 | # EDX: end of range\r | |
| 26 | #\r | |
| 27 | movl 0x8(%esp), %ecx\r | |
| 28 | movl 0xC(%esp), %edx\r | |
| 29 | \r | |
| 30 | #\r | |
| 31 | # Platform init\r | |
| 32 | #\r | |
| 33 | pushal\r | |
| 34 | pushl %edx\r | |
| 35 | pushl %ecx\r | |
| 36 | pushl %eax\r | |
| 37 | call ASM_PFX(PlatformInit)\r | |
| 38 | popl %eax\r | |
| 39 | popl %eax\r | |
| 40 | popl %eax\r | |
| 41 | popal\r | |
| 42 | \r | |
| 43 | #\r | |
| 44 | # Set stack top pointer\r | |
| 45 | #\r | |
| 46 | movl %edx, %esp\r | |
| 47 | \r | |
| 48 | #\r | |
| 49 | # Push the hob list pointer\r | |
| 50 | #\r | |
| 51 | pushl %eax\r | |
| 52 | \r | |
| 53 | #\r | |
| 54 | # Save the value\r | |
| 55 | # ECX: start of range\r | |
| 56 | # EDX: end of range\r | |
| 57 | #\r | |
| 58 | movl %esp, %ebp\r | |
| 59 | pushl %ecx\r | |
| 60 | pushl %edx\r | |
| 61 | \r | |
| 62 | #\r | |
| 63 | # Push processor count to stack first, then BIST status (AP then BSP)\r | |
| 64 | #\r | |
| 65 | movl $1, %eax\r | |
| 66 | cpuid\r | |
| 67 | shr $16, %ebx\r | |
| 68 | andl $0x000000FF, %ebx\r | |
| 69 | cmp $1, %bl\r | |
| 70 | jae PushProcessorCount\r | |
| 71 | \r | |
| 72 | #\r | |
| 73 | # Some processors report 0 logical processors. Effectively 0 = 1.\r | |
| 74 | # So we fix up the processor count\r | |
| 75 | #\r | |
| 76 | inc %ebx\r | |
| 77 | \r | |
| 78 | PushProcessorCount:\r | |
| 79 | pushl %ebx\r | |
| 80 | \r | |
| 81 | #\r | |
| 82 | # We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST\r | |
| 83 | # for all processor threads\r | |
| 84 | #\r | |
| 85 | xorl %ecx, %ecx\r | |
| 86 | movb %bl, %cl\r | |
| 87 | PushBist:\r | |
| 88 | movd %mm0, %eax\r | |
| 89 | pushl %eax\r | |
| 90 | loop PushBist\r | |
| 91 | \r | |
| 92 | # Save Time-Stamp Counter\r | |
| 93 | movd %mm5, %eax\r | |
| 94 | pushl %eax\r | |
| 95 | \r | |
| 96 | movd %mm6, %eax\r | |
| 97 | pushl %eax\r | |
| 98 | \r | |
| 99 | #\r | |
| 100 | # Pass entry point of the PEI core\r | |
| 101 | #\r | |
| 102 | movl $0xFFFFFFE0, %edi\r | |
| 103 | pushl %ds:(%edi)\r | |
| 104 | \r | |
| 105 | #\r | |
| 106 | # Pass BFV into the PEI Core\r | |
| 107 | #\r | |
| 108 | movl $0xFFFFFFFC, %edi\r | |
| 109 | pushl %ds:(%edi)\r | |
| 110 | \r | |
| 111 | #\r | |
| 112 | # Pass stack size into the PEI Core\r | |
| 113 | #\r | |
| 114 | movl -4(%ebp), %ecx\r | |
| 115 | movl -8(%ebp), %edx\r | |
| 116 | pushl %ecx # RamBase\r | |
| 117 | \r | |
| 118 | subl %ecx, %edx\r | |
| 119 | pushl %edx # RamSize\r | |
| 120 | \r | |
| 121 | #\r | |
| 122 | # Pass Control into the PEI Core\r | |
| 123 | #\r | |
| 124 | call ASM_PFX(SecStartup)\r |