[mirror_edk2.git] / IntelSiliconPkg / Feature / VTd / PlatformVTdInfoSamplePei / PlatformVTdInfoSamplePei.c

/** @file\r
  Platform VTd Info Sample PEI driver.\r
\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <PiPei.h>\r
\r
#include <Ppi/VtdInfo.h>\r
\r
#include <Library/PeiServicesLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
#define R_SA_MCHBAR               (0x48)\r
#define R_SA_GGC                  (0x50)\r
#define N_SKL_SA_GGC_GGMS_OFFSET  (0x6)\r
#define B_SKL_SA_GGC_GGMS_MASK    (0xc0)\r
#define N_SKL_SA_GGC_GMS_OFFSET   (0x8)\r
#define B_SKL_SA_GGC_GMS_MASK     (0xff00)\r
#define V_SKL_SA_GGC_GGMS_8MB     3\r
#define R_SA_TOLUD                (0xbc)\r
\r
#define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD\r
#define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, USB, SATA etc\r
\r
EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};\r
\r
typedef struct {\r
  EFI_ACPI_DMAR_HEADER                         DmarHeader;\r
  //\r
  // VTd engine 1 - integrated graphic\r
  //\r
  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd1;\r
  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Drhd11;\r
  EFI_ACPI_DMAR_PCI_PATH                       Drhd111;\r
  //\r
  // VTd engine 2 - all rest\r
  //\r
  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd2;\r
  //\r
  // RMRR 1 - integrated graphic\r
  //\r
  EFI_ACPI_DMAR_RMRR_HEADER                    Rmrr1;\r
  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Rmrr11;\r
  EFI_ACPI_DMAR_PCI_PATH                       Rmrr111;\r
} MY_VTD_INFO_PPI;\r
\r
MY_VTD_INFO_PPI  mPlatformVTdSample = {\r
  { // DmarHeader\r
    { // Header\r
      EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
      sizeof(MY_VTD_INFO_PPI),\r
      EFI_ACPI_DMAR_REVISION,\r
    },\r
    0x26, // HostAddressWidth\r
  },\r
\r
  { // Drhd1\r
    { // Header\r
      EFI_ACPI_DMAR_TYPE_DRHD,\r
      sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
    },\r
    0, // Flags\r
    0, // Reserved\r
    0, // SegmentNumber\r
    0xFED90000 // RegisterBaseAddress -- TO BE PATCHED\r
  },\r
  { // Drhd11\r
    EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
    sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
      sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
    0, // Reserved2\r
    0, // EnumerationId\r
    0  // StartBusNumber\r
  },\r
  { // Drhd111\r
    2,  // Device\r
    0   // Function\r
  },\r
\r
  { // Drhd2\r
    { // Header\r
      EFI_ACPI_DMAR_TYPE_DRHD,\r
      sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
    },\r
    EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
    0, // Reserved\r
    0, // SegmentNumber\r
    0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
  },\r
\r
  { // Rmrr1\r
    { // Header\r
      EFI_ACPI_DMAR_TYPE_RMRR,\r
      sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
    },\r
    {0}, // Reserved\r
    0, // SegmentNumber\r
    0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED\r
    0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED\r
  },\r
  { // Rmrr11\r
    EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
    sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
      sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
    0, // Reserved2\r
    0, // EnumerationId\r
    0  // StartBusNumber\r
  },\r
  { // Rmrr111\r
    2,  // Device\r
    0   // Function\r
  },\r
};\r
\r
EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {\r
  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
  &gEdkiiVTdInfoPpiGuid,\r
  &mPlatformVTdSample\r
};\r
\r
typedef struct {\r
  EFI_ACPI_DMAR_HEADER                         DmarHeader;\r
  //\r
  // VTd engine 2 - all rest\r
  //\r
  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd2;\r
} MY_VTD_INFO_NO_IGD_PPI;\r
\r
MY_VTD_INFO_NO_IGD_PPI  mPlatformVTdNoIgdSample = {\r
  { // DmarHeader\r
    { // Header\r
      EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
      sizeof(MY_VTD_INFO_NO_IGD_PPI),\r
      EFI_ACPI_DMAR_REVISION,\r
    },\r
    0x26, // HostAddressWidth\r
  },\r
\r
  { // Drhd2\r
    { // Header\r
      EFI_ACPI_DMAR_TYPE_DRHD,\r
      sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
    },\r
    EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
    0, // Reserved\r
    0, // SegmentNumber\r
    0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
  },\r
};\r
\r
EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {\r
  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
  &gEdkiiVTdInfoPpiGuid,\r
  &mPlatformVTdNoIgdSample\r
};\r
\r
/**\r
  Initialize VTd register.\r
**/\r
VOID\r
InitDmar (\r
  VOID\r
  )\r
{\r
  UINT32              MchBar;\r
\r
  DEBUG ((DEBUG_INFO, "InitDmar\n"));\r
\r
  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
  PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0);\r
  DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));\r
\r
  MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress | 1);\r
  DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
}\r
\r
/**\r
  Patch Graphic UMA address in RMRR and base address.\r
**/\r
EFI_PEI_PPI_DESCRIPTOR *\r
PatchDmar (\r
  VOID\r
  )\r
{\r
  UINT32                  MchBar;\r
  UINT16                  IgdMode;\r
  UINT16                  GttMode;\r
  UINT32                  IgdMemSize;\r
  UINT32                  GttMemSize;\r
  MY_VTD_INFO_PPI         *PlatformVTdSample;\r
  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdInfoSampleDesc;\r
  MY_VTD_INFO_NO_IGD_PPI  *PlatformVTdNoIgdSample;\r
  EFI_PEI_PPI_DESCRIPTOR  *PlatformVTdNoIgdInfoSampleDesc;\r
\r
  DEBUG ((DEBUG_INFO, "PatchDmar\n"));\r
\r
  if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0xFFFF) {\r
    PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), &mPlatformVTdSample);\r
    ASSERT(PlatformVTdSample != NULL);\r
    PlatformVTdInfoSampleDesc = AllocateCopyPool (sizeof(EFI_PEI_PPI_DESCRIPTOR), &mPlatformVTdInfoSampleDesc);\r
    ASSERT(PlatformVTdInfoSampleDesc != NULL);\r
    PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;\r
\r
    ///\r
    /// Calculate IGD memsize\r
    ///\r
    IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;\r
    if (IgdMode < 0xF0) {\r
      IgdMemSize = IgdMode * 32 * (1024) * (1024);\r
    } else {\r
      IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);\r
    }\r
\r
    ///\r
    /// Calculate GTT mem size\r
    ///\r
    GttMemSize = 0;\r
    GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;\r
    if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {\r
      GttMemSize = (1 << GttMode) * (1024) * (1024);\r
    }\r
\r
    PlatformVTdSample->Rmrr1.ReservedMemoryRegionBaseAddress  = (PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSize;\r
    PlatformVTdSample->Rmrr1.ReservedMemoryRegionLimitAddress = PlatformVTdSample->Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;\r
\r
    ///\r
    /// Update DRHD structures of DmarTable\r
    ///\r
    MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
\r
    if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1) != 0) {\r
      PlatformVTdSample->Drhd1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);\r
    } else {\r
      MmioWrite32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET, (UINT32)PlatformVTdSample->Drhd1.RegisterBaseAddress | 1);\r
    }\r
    DEBUG ((DEBUG_INFO, "VTd1 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET))));\r
\r
    if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) != 0) {\r
      PlatformVTdSample->Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
    } else {\r
      MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdSample->Drhd2.RegisterBaseAddress | 1);\r
    }\r
    DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
\r
    return PlatformVTdInfoSampleDesc;\r
  } else {\r
    PlatformVTdNoIgdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_NO_IGD_PPI), &mPlatformVTdNoIgdSample);\r
    ASSERT(PlatformVTdNoIgdSample != NULL);\r
    PlatformVTdNoIgdInfoSampleDesc = AllocateCopyPool (sizeof(EFI_PEI_PPI_DESCRIPTOR), &mPlatformVTdNoIgdInfoSampleDesc);\r
    ASSERT(PlatformVTdNoIgdInfoSampleDesc != NULL);\r
    PlatformVTdNoIgdInfoSampleDesc->Ppi = PlatformVTdNoIgdSample;\r
\r
    ///\r
    /// Update DRHD structures of DmarTable\r
    ///\r
    MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
\r
    if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) != 0) {\r
      PlatformVTdNoIgdSample->Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
    } else {\r
      MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdNoIgdSample->Drhd2.RegisterBaseAddress | 1);\r
    }\r
    DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
\r
    return PlatformVTdNoIgdInfoSampleDesc;\r
  }\r
}\r
\r
/**\r
  The callback function for SiliconInitializedPpi.\r
  It reinstalls VTD_INFO_PPI.\r
\r
  @param[in]  PeiServices       General purpose services available to every PEIM.\r
  @param[in]  NotifyDescriptor  Notify that this module published.\r
  @param[in]  Ppi               PPI that was installed.\r
\r
  @retval     EFI_SUCCESS       The function completed successfully.\r
**/\r
EFI_STATUS\r
EFIAPI\r
SiliconInitializedPpiNotifyCallback (\r
  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  )\r
{\r
  EFI_STATUS               Status;\r
  EFI_PEI_PPI_DESCRIPTOR   *PpiDesc;\r
\r
  PpiDesc = PatchDmar ();\r
\r
  Status = PeiServicesReInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc, PpiDesc);\r
  ASSERT_EFI_ERROR (Status);\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_PEI_NOTIFY_DESCRIPTOR mSiliconInitializedNotifyList = {\r
  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
  &gEdkiiSiliconInitializedPpiGuid,\r
  (EFI_PEIM_NOTIFY_ENTRY_POINT) SiliconInitializedPpiNotifyCallback\r
};\r
\r
/**\r
  Platform VTd Info sample driver.\r
\r
  @param[in] FileHandle  Handle of the file being invoked.\r
  @param[in] PeiServices Describes the list of possible PEI Services.\r
\r
  @retval EFI_SUCCESS if it completed successfully.\r
**/\r
EFI_STATUS\r
EFIAPI\r
PlatformVTdInfoSampleInitialize (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  EFI_STATUS               Status;\r
  BOOLEAN                  SiliconInitialized;\r
  VOID                     *SiliconInitializedPpi;\r
  EFI_PEI_PPI_DESCRIPTOR   *PpiDesc;\r
\r
  SiliconInitialized = FALSE;\r
  //\r
  // Check if silicon is initialized.\r
  //\r
  Status = PeiServicesLocatePpi (\r
             &gEdkiiSiliconInitializedPpiGuid,\r
             0,\r
             NULL,\r
             &SiliconInitializedPpi\r
             );\r
  if (!EFI_ERROR(Status)) {\r
    SiliconInitialized = TRUE;\r
  }\r
  DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized));\r
  if (!SiliconInitialized) {\r
    Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList);\r
    InitDmar ();\r
\r
    Status = PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc);\r
    ASSERT_EFI_ERROR (Status);\r
  } else {\r
    PpiDesc = PatchDmar ();\r
\r
    Status = PeiServicesInstallPpi (PpiDesc);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  return Status;\r
}\r
Commit	Line	Data
53269009 JY	1	/** @file\r
	2	Platform VTd Info Sample PEI driver.\r
	3	\r
	4	Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
8f7a05e1	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
53269009 JY	6	\r
	7	**/\r
	8	\r
	9	#include <PiPei.h>\r
	10	\r
4084ccfa	11	#include <Ppi/VtdInfo.h>\r
53269009 JY	12	\r
	13	#include <Library/PeiServicesLib.h>\r
	14	#include <Library/DebugLib.h>\r
70dc3ec5 JY	15	#include <Library/PciLib.h>\r
70dc3ec5 JY	16	#include <Library/IoLib.h>\r
af807bb9	17	#include <Library/MemoryAllocationLib.h>\r
70dc3ec5 JY	18	\r
	19	#define R_SA_MCHBAR (0x48)\r
	20	#define R_SA_GGC (0x50)\r
	21	#define N_SKL_SA_GGC_GGMS_OFFSET (0x6)\r
	22	#define B_SKL_SA_GGC_GGMS_MASK (0xc0)\r
	23	#define N_SKL_SA_GGC_GMS_OFFSET (0x8)\r
	24	#define B_SKL_SA_GGC_GMS_MASK (0xff00)\r
	25	#define V_SKL_SA_GGC_GGMS_8MB 3\r
	26	#define R_SA_TOLUD (0xbc)\r
	27	\r
	28	#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT for IGD\r
	29	#define R_SA_MCHBAR_VTD2_OFFSET 0x5410 ///< HW UNIT for all other - PEG, USB, SATA etc\r
53269009	30	\r
af807bb9 JY	31	EFI_GUID gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}};\r
af807bb9 JY	32	\r
53269009	33	typedef struct {\r
70dc3ec5 JY	34	EFI_ACPI_DMAR_HEADER DmarHeader;\r
	35	//\r
	36	// VTd engine 1 - integrated graphic\r
	37	//\r
	38	EFI_ACPI_DMAR_DRHD_HEADER Drhd1;\r
	39	EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Drhd11;\r
	40	EFI_ACPI_DMAR_PCI_PATH Drhd111;\r
	41	//\r
	42	// VTd engine 2 - all rest\r
	43	//\r
	44	EFI_ACPI_DMAR_DRHD_HEADER Drhd2;\r
	45	//\r
	46	// RMRR 1 - integrated graphic\r
	47	//\r
	48	EFI_ACPI_DMAR_RMRR_HEADER Rmrr1;\r
	49	EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Rmrr11;\r
	50	EFI_ACPI_DMAR_PCI_PATH Rmrr111;\r
53269009 JY	51	} MY_VTD_INFO_PPI;\r
	52	\r
	53	MY_VTD_INFO_PPI mPlatformVTdSample = {\r
70dc3ec5 JY	54	{ // DmarHeader\r
	55	{ // Header\r
	56	EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
	57	sizeof(MY_VTD_INFO_PPI),\r
	58	EFI_ACPI_DMAR_REVISION,\r
	59	},\r
	60	0x26, // HostAddressWidth\r
	61	},\r
	62	\r
	63	{ // Drhd1\r
	64	{ // Header\r
	65	EFI_ACPI_DMAR_TYPE_DRHD,\r
	66	sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +\r
	67	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	68	sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
	69	},\r
	70	0, // Flags\r
	71	0, // Reserved\r
	72	0, // SegmentNumber\r
	73	0xFED90000 // RegisterBaseAddress -- TO BE PATCHED\r
	74	},\r
	75	{ // Drhd11\r
	76	EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
	77	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	78	sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
	79	0, // Reserved2\r
	80	0, // EnumerationId\r
	81	0 // StartBusNumber\r
	82	},\r
	83	{ // Drhd111\r
	84	2, // Device\r
	85	0 // Function\r
	86	},\r
	87	\r
	88	{ // Drhd2\r
	89	{ // Header\r
	90	EFI_ACPI_DMAR_TYPE_DRHD,\r
	91	sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
	92	},\r
	93	EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
	94	0, // Reserved\r
	95	0, // SegmentNumber\r
	96	0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
	97	},\r
	98	\r
	99	{ // Rmrr1\r
	100	{ // Header\r
	101	EFI_ACPI_DMAR_TYPE_RMRR,\r
	102	sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +\r
	103	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	104	sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
	105	},\r
	106	{0}, // Reserved\r
	107	0, // SegmentNumber\r
	108	0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED\r
	109	0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED\r
	110	},\r
	111	{ // Rmrr11\r
	112	EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
	113	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	114	sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
	115	0, // Reserved2\r
	116	0, // EnumerationId\r
	117	0 // StartBusNumber\r
118	},\r
119	{ // Rmrr111\r
120	2, // Device\r
121	0 // Function\r
122	},\r
53269009 JY	123	};\r
	124	\r
	125	EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {\r
	126	(EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
	127	&gEdkiiVTdInfoPpiGuid,\r
	128	&mPlatformVTdSample\r
	129	};\r
	130	\r
af807bb9 JY	131	typedef struct {\r
	132	EFI_ACPI_DMAR_HEADER DmarHeader;\r
	133	//\r
	134	// VTd engine 2 - all rest\r
	135	//\r
	136	EFI_ACPI_DMAR_DRHD_HEADER Drhd2;\r
	137	} MY_VTD_INFO_NO_IGD_PPI;\r
	138	\r
	139	MY_VTD_INFO_NO_IGD_PPI mPlatformVTdNoIgdSample = {\r
	140	{ // DmarHeader\r
	141	{ // Header\r
	142	EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
	143	sizeof(MY_VTD_INFO_NO_IGD_PPI),\r
	144	EFI_ACPI_DMAR_REVISION,\r
	145	},\r
	146	0x26, // HostAddressWidth\r
	147	},\r
	148	\r
	149	{ // Drhd2\r
	150	{ // Header\r
	151	EFI_ACPI_DMAR_TYPE_DRHD,\r
	152	sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
	153	},\r
	154	EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
	155	0, // Reserved\r
	156	0, // SegmentNumber\r
	157	0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
	158	},\r
	159	};\r
	160	\r
	161	EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {\r
	162	(EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
	163	&gEdkiiVTdInfoPpiGuid,\r
	164	&mPlatformVTdNoIgdSample\r
	165	};\r
	166	\r
70dc3ec5	167	/**\r
af807bb9	168	Initialize VTd register.\r
70dc3ec5 JY	169	**/\r
70dc3ec5 JY	170	VOID\r
af807bb9	171	InitDmar (\r
70dc3ec5 JY	172	VOID\r
	173	)\r
	174	{\r
	175	UINT32 MchBar;\r
af807bb9 JY	176	\r
	177	DEBUG ((DEBUG_INFO, "InitDmar\n"));\r
	178	\r
	179	MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
	180	PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 \| BIT0);\r
	181	DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar));\r
	182	\r
	183	MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)mPlatformVTdSample.Drhd2.RegisterBaseAddress \| 1);\r
	184	DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
	185	}\r
	186	\r
	187	/**\r
	188	Patch Graphic UMA address in RMRR and base address.\r
	189	**/\r
	190	EFI_PEI_PPI_DESCRIPTOR *\r
	191	PatchDmar (\r
	192	VOID\r
	193	)\r
	194	{\r
	195	UINT32 MchBar;\r
	196	UINT16 IgdMode;\r
	197	UINT16 GttMode;\r
	198	UINT32 IgdMemSize;\r
	199	UINT32 GttMemSize;\r
	200	MY_VTD_INFO_PPI *PlatformVTdSample;\r
	201	EFI_PEI_PPI_DESCRIPTOR *PlatformVTdInfoSampleDesc;\r
	202	MY_VTD_INFO_NO_IGD_PPI *PlatformVTdNoIgdSample;\r
	203	EFI_PEI_PPI_DESCRIPTOR *PlatformVTdNoIgdInfoSampleDesc;\r
	204	\r
	205	DEBUG ((DEBUG_INFO, "PatchDmar\n"));\r
	206	\r
	207	if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) != 0xFFFF) {\r
	208	PlatformVTdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), &mPlatformVTdSample);\r
	209	ASSERT(PlatformVTdSample != NULL);\r
	210	PlatformVTdInfoSampleDesc = AllocateCopyPool (sizeof(EFI_PEI_PPI_DESCRIPTOR), &mPlatformVTdInfoSampleDesc);\r
	211	ASSERT(PlatformVTdInfoSampleDesc != NULL);\r
	212	PlatformVTdInfoSampleDesc->Ppi = PlatformVTdSample;\r
	213	\r
	214	///\r
	215	/// Calculate IGD memsize\r
	216	///\r
	217	IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;\r
	218	if (IgdMode < 0xF0) {\r
	219	IgdMemSize = IgdMode * 32 * (1024) * (1024);\r
	220	} else {\r
	221	IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);\r
	222	}\r
	223	\r
	224	///\r
	225	/// Calculate GTT mem size\r
	226	///\r
	227	GttMemSize = 0;\r
	228	GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;\r
	229	if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {\r
	230	GttMemSize = (1 << GttMode) * (1024) * (1024);\r
	231	}\r
	232	\r
	233	PlatformVTdSample->Rmrr1.ReservedMemoryRegionBaseAddress = (PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSize;\r
	234	PlatformVTdSample->Rmrr1.ReservedMemoryRegionLimitAddress = PlatformVTdSample->Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;\r
	235	\r
	236	///\r
	237	/// Update DRHD structures of DmarTable\r
	238	///\r
	239	MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
240	\r
241	if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1) != 0) {\r
242	PlatformVTdSample->Drhd1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);\r
243	} else {\r
244	MmioWrite32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET, (UINT32)PlatformVTdSample->Drhd1.RegisterBaseAddress \| 1);\r
245	}\r
246	DEBUG ((DEBUG_INFO, "VTd1 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET))));\r
247	\r
248	if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) != 0) {\r
249	PlatformVTdSample->Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
250	} else {\r
251	MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdSample->Drhd2.RegisterBaseAddress \| 1);\r
252	}\r
253	DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
254	\r
255	return PlatformVTdInfoSampleDesc;\r
70dc3ec5	256	} else {\r
af807bb9 JY	257	PlatformVTdNoIgdSample = AllocateCopyPool (sizeof(MY_VTD_INFO_NO_IGD_PPI), &mPlatformVTdNoIgdSample);\r
	258	ASSERT(PlatformVTdNoIgdSample != NULL);\r
	259	PlatformVTdNoIgdInfoSampleDesc = AllocateCopyPool (sizeof(EFI_PEI_PPI_DESCRIPTOR), &mPlatformVTdNoIgdInfoSampleDesc);\r
	260	ASSERT(PlatformVTdNoIgdInfoSampleDesc != NULL);\r
	261	PlatformVTdNoIgdInfoSampleDesc->Ppi = PlatformVTdNoIgdSample;\r
	262	\r
	263	///\r
	264	/// Update DRHD structures of DmarTable\r
	265	///\r
	266	MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
70dc3ec5	267	\r
af807bb9 JY	268	if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) != 0) {\r
	269	PlatformVTdNoIgdSample->Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
	270	} else {\r
	271	MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdNoIgdSample->Drhd2.RegisterBaseAddress \| 1);\r
	272	}\r
	273	DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET))));\r
	274	\r
	275	return PlatformVTdNoIgdInfoSampleDesc;\r
70dc3ec5	276	}\r
af807bb9	277	}\r
70dc3ec5	278	\r
af807bb9 JY	279	/**\r
	280	The callback function for SiliconInitializedPpi.\r
	281	It reinstalls VTD_INFO_PPI.\r
70dc3ec5	282	\r
af807bb9 JY	283	@param[in] PeiServices General purpose services available to every PEIM.\r
	284	@param[in] NotifyDescriptor Notify that this module published.\r
	285	@param[in] Ppi PPI that was installed.\r
	286	\r
	287	@retval EFI_SUCCESS The function completed successfully.\r
	288	**/\r
	289	EFI_STATUS\r
	290	EFIAPI\r
	291	SiliconInitializedPpiNotifyCallback (\r
	292	IN CONST EFI_PEI_SERVICES **PeiServices,\r
	293	IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
	294	IN VOID *Ppi\r
	295	)\r
	296	{\r
	297	EFI_STATUS Status;\r
	298	EFI_PEI_PPI_DESCRIPTOR *PpiDesc;\r
	299	\r
	300	PpiDesc = PatchDmar ();\r
	301	\r
	302	Status = PeiServicesReInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc, PpiDesc);\r
	303	ASSERT_EFI_ERROR (Status);\r
	304	return EFI_SUCCESS;\r
70dc3ec5 JY	305	}\r
70dc3ec5 JY	306	\r
af807bb9 JY	307	EFI_PEI_NOTIFY_DESCRIPTOR mSiliconInitializedNotifyList = {\r
	308	(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
	309	&gEdkiiSiliconInitializedPpiGuid,\r
	310	(EFI_PEIM_NOTIFY_ENTRY_POINT) SiliconInitializedPpiNotifyCallback\r
	311	};\r
	312	\r
53269009 JY	313	/**\r
	314	Platform VTd Info sample driver.\r
	315	\r
	316	@param[in] FileHandle Handle of the file being invoked.\r
	317	@param[in] PeiServices Describes the list of possible PEI Services.\r
	318	\r
	319	@retval EFI_SUCCESS if it completed successfully.\r
	320	**/\r
	321	EFI_STATUS\r
	322	EFIAPI\r
	323	PlatformVTdInfoSampleInitialize (\r
	324	IN EFI_PEI_FILE_HANDLE FileHandle,\r
	325	IN CONST EFI_PEI_SERVICES **PeiServices\r
	326	)\r
	327	{\r
af807bb9 JY	328	EFI_STATUS Status;\r
	329	BOOLEAN SiliconInitialized;\r
	330	VOID *SiliconInitializedPpi;\r
	331	EFI_PEI_PPI_DESCRIPTOR *PpiDesc;\r
	332	\r
	333	SiliconInitialized = FALSE;\r
	334	//\r
	335	// Check if silicon is initialized.\r
	336	//\r
	337	Status = PeiServicesLocatePpi (\r
	338	&gEdkiiSiliconInitializedPpiGuid,\r
	339	0,\r
	340	NULL,\r
	341	&SiliconInitializedPpi\r
	342	);\r
	343	if (!EFI_ERROR(Status)) {\r
	344	SiliconInitialized = TRUE;\r
	345	}\r
	346	DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized));\r
	347	if (!SiliconInitialized) {\r
	348	Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList);\r
	349	InitDmar ();\r
53269009	350	\r
af807bb9 JY	351	Status = PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc);\r
	352	ASSERT_EFI_ERROR (Status);\r
	353	} else {\r
	354	PpiDesc = PatchDmar ();\r
70dc3ec5	355	\r
af807bb9 JY	356	Status = PeiServicesInstallPpi (PpiDesc);\r
	357	ASSERT_EFI_ERROR (Status);\r
	358	}\r
53269009 JY	359	\r
	360	return Status;\r
	361	}\r