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[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / IdeMode.c
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a41b5272 1/** @file\r
2 Header file for AHCI mode of ATA host controller.\r
1aff716a 3\r
73a9e822 4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
1aff716a 5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
a41b5272 9\r
1aff716a 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
a41b5272 12\r
13**/\r
14\r
15#include "AtaAtapiPassThru.h"\r
16\r
17/**\r
18 read a one-byte data from a IDE port.\r
19\r
8536cc4b 20 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
1aff716a 21 @param Port The IDE Port number\r
a41b5272 22\r
23 @return the one-byte data read from IDE port\r
24**/\r
25UINT8\r
26EFIAPI\r
27IdeReadPortB (\r
28 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
29 IN UINT16 Port\r
30 )\r
31{\r
32 UINT8 Data;\r
33\r
34 ASSERT (PciIo != NULL);\r
35\r
36 Data = 0;\r
37 //\r
38 // perform 1-byte data read from register\r
39 //\r
40 PciIo->Io.Read (\r
41 PciIo,\r
42 EfiPciIoWidthUint8,\r
43 EFI_PCI_IO_PASS_THROUGH_BAR,\r
44 (UINT64) Port,\r
45 1,\r
46 &Data\r
47 );\r
48 return Data;\r
49}\r
50\r
51/**\r
52 write a 1-byte data to a specific IDE port.\r
53\r
8536cc4b 54 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
a41b5272 55 @param Port The IDE port to be writen\r
56 @param Data The data to write to the port\r
57**/\r
58VOID\r
59EFIAPI\r
60IdeWritePortB (\r
61 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
62 IN UINT16 Port,\r
63 IN UINT8 Data\r
64 )\r
65{\r
66 ASSERT (PciIo != NULL);\r
67\r
68 //\r
69 // perform 1-byte data write to register\r
70 //\r
71 PciIo->Io.Write (\r
72 PciIo,\r
73 EfiPciIoWidthUint8,\r
74 EFI_PCI_IO_PASS_THROUGH_BAR,\r
75 (UINT64) Port,\r
76 1,\r
77 &Data\r
78 );\r
79}\r
80\r
81/**\r
82 write a 1-word data to a specific IDE port.\r
83\r
8536cc4b 84 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
a41b5272 85 @param Port The IDE port to be writen\r
86 @param Data The data to write to the port\r
87**/\r
88VOID\r
89EFIAPI\r
90IdeWritePortW (\r
91 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
92 IN UINT16 Port,\r
93 IN UINT16 Data\r
94 )\r
95{\r
96 ASSERT (PciIo != NULL);\r
97\r
98 //\r
99 // perform 1-word data write to register\r
100 //\r
101 PciIo->Io.Write (\r
102 PciIo,\r
103 EfiPciIoWidthUint16,\r
104 EFI_PCI_IO_PASS_THROUGH_BAR,\r
105 (UINT64) Port,\r
106 1,\r
107 &Data\r
108 );\r
109}\r
110\r
111/**\r
112 write a 2-word data to a specific IDE port.\r
113\r
8536cc4b 114 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
a41b5272 115 @param Port The IDE port to be writen\r
116 @param Data The data to write to the port\r
117**/\r
118VOID\r
119EFIAPI\r
120IdeWritePortDW (\r
121 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
122 IN UINT16 Port,\r
123 IN UINT32 Data\r
124 )\r
125{\r
126 ASSERT (PciIo != NULL);\r
127\r
128 //\r
129 // perform 2-word data write to register\r
130 //\r
131 PciIo->Io.Write (\r
132 PciIo,\r
133 EfiPciIoWidthUint32,\r
134 EFI_PCI_IO_PASS_THROUGH_BAR,\r
135 (UINT64) Port,\r
136 1,\r
137 &Data\r
138 );\r
139}\r
140\r
141/**\r
142 Write multiple words of data to the IDE data port.\r
143 Call the IO abstraction once to do the complete read,\r
144 not one word at a time\r
145\r
8536cc4b 146 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
a41b5272 147 @param Port IO port to read\r
148 @param Count No. of UINT16's to read\r
149 @param Buffer Pointer to the data buffer for read\r
150\r
151**/\r
152VOID\r
153EFIAPI\r
154IdeWritePortWMultiple (\r
155 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
156 IN UINT16 Port,\r
157 IN UINTN Count,\r
158 IN VOID *Buffer\r
159 )\r
160{\r
161 ASSERT (PciIo != NULL);\r
162 ASSERT (Buffer != NULL);\r
163\r
164 //\r
165 // perform UINT16 data write to the FIFO\r
166 //\r
167 PciIo->Io.Write (\r
168 PciIo,\r
169 EfiPciIoWidthFifoUint16,\r
170 EFI_PCI_IO_PASS_THROUGH_BAR,\r
171 (UINT64) Port,\r
172 Count,\r
173 (UINT16 *) Buffer\r
174 );\r
175\r
176}\r
177\r
178/**\r
179 Reads multiple words of data from the IDE data port.\r
180 Call the IO abstraction once to do the complete read,\r
181 not one word at a time\r
182\r
8536cc4b 183 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
a41b5272 184 @param Port IO port to read\r
185 @param Count Number of UINT16's to read\r
186 @param Buffer Pointer to the data buffer for read\r
187\r
188**/\r
189VOID\r
190EFIAPI\r
191IdeReadPortWMultiple (\r
192 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
193 IN UINT16 Port,\r
194 IN UINTN Count,\r
195 IN VOID *Buffer\r
196 )\r
197{\r
198 ASSERT (PciIo != NULL);\r
199 ASSERT (Buffer != NULL);\r
200\r
201 //\r
202 // Perform UINT16 data read from FIFO\r
203 //\r
204 PciIo->Io.Read (\r
205 PciIo,\r
206 EfiPciIoWidthFifoUint16,\r
207 EFI_PCI_IO_PASS_THROUGH_BAR,\r
208 (UINT64) Port,\r
209 Count,\r
210 (UINT16 *) Buffer\r
211 );\r
212\r
213}\r
214\r
215/**\r
216 This function is used to analyze the Status Register and print out\r
217 some debug information and if there is ERR bit set in the Status\r
218 Register, the Error Register's value is also be parsed and print out.\r
219\r
8536cc4b 220 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 221 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
222 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
223\r
224**/\r
225VOID\r
226EFIAPI\r
227DumpAllIdeRegisters (\r
228 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
229 IN EFI_IDE_REGISTERS *IdeRegisters,\r
230 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
231 )\r
232{\r
233 EFI_ATA_STATUS_BLOCK StatusBlock;\r
234\r
235 ASSERT (PciIo != NULL);\r
236 ASSERT (IdeRegisters != NULL);\r
237\r
238 ZeroMem (&StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
239\r
240 StatusBlock.AtaStatus = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
241 StatusBlock.AtaError = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
242 StatusBlock.AtaSectorCount = IdeReadPortB (PciIo, IdeRegisters->SectorCount);\r
243 StatusBlock.AtaSectorCountExp = IdeReadPortB (PciIo, IdeRegisters->SectorCount);\r
244 StatusBlock.AtaSectorNumber = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);\r
245 StatusBlock.AtaSectorNumberExp = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);\r
246 StatusBlock.AtaCylinderLow = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);\r
247 StatusBlock.AtaCylinderLowExp = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);\r
248 StatusBlock.AtaCylinderHigh = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);\r
249 StatusBlock.AtaCylinderHighExp = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);\r
250 StatusBlock.AtaDeviceHead = IdeReadPortB (PciIo, IdeRegisters->Head);\r
251\r
252 if (AtaStatusBlock != NULL) {\r
253 //\r
254 // Dump the content of all ATA registers.\r
255 //\r
256 CopyMem (AtaStatusBlock, &StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
257 }\r
258\r
259 DEBUG_CODE_BEGIN ();\r
260 if ((StatusBlock.AtaStatus & ATA_STSREG_DWF) != 0) {\r
261 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Write Fault\n", StatusBlock.AtaStatus));\r
262 }\r
263\r
264 if ((StatusBlock.AtaStatus & ATA_STSREG_CORR) != 0) {\r
265 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Corrected Data\n", StatusBlock.AtaStatus));\r
266 }\r
267\r
268 if ((StatusBlock.AtaStatus & ATA_STSREG_ERR) != 0) {\r
269 if ((StatusBlock.AtaError & ATA_ERRREG_BBK) != 0) {\r
270 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Bad Block Detected\n", StatusBlock.AtaError));\r
271 }\r
272\r
273 if ((StatusBlock.AtaError & ATA_ERRREG_UNC) != 0) {\r
274 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Uncorrectable Data\n", StatusBlock.AtaError));\r
275 }\r
276\r
277 if ((StatusBlock.AtaError & ATA_ERRREG_MC) != 0) {\r
278 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Media Change\n", StatusBlock.AtaError));\r
279 }\r
280\r
281 if ((StatusBlock.AtaError & ATA_ERRREG_ABRT) != 0) {\r
282 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Abort\n", StatusBlock.AtaError));\r
283 }\r
284\r
285 if ((StatusBlock.AtaError & ATA_ERRREG_TK0NF) != 0) {\r
286 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Track 0 Not Found\n", StatusBlock.AtaError));\r
287 }\r
288\r
289 if ((StatusBlock.AtaError & ATA_ERRREG_AMNF) != 0) {\r
290 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Address Mark Not Found\n", StatusBlock.AtaError));\r
291 }\r
292 }\r
293 DEBUG_CODE_END ();\r
294}\r
295\r
296/**\r
8536cc4b 297 This function is used to analyze the Status Register at the condition that BSY is zero.\r
298 if there is ERR bit set in the Status Register, then return error.\r
a41b5272 299\r
8536cc4b 300 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 301 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
302\r
303 @retval EFI_SUCCESS No err information in the Status Register.\r
304 @retval EFI_DEVICE_ERROR Any err information in the Status Register.\r
305\r
306**/\r
307EFI_STATUS\r
308EFIAPI\r
309CheckStatusRegister (\r
310 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
311 IN EFI_IDE_REGISTERS *IdeRegisters\r
312 )\r
313{\r
a41b5272 314 UINT8 StatusRegister;\r
315\r
316 ASSERT (PciIo != NULL);\r
317 ASSERT (IdeRegisters != NULL);\r
318\r
319 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
320\r
8536cc4b 321 if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
322 if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {\r
323 return EFI_SUCCESS;\r
324 } else {\r
325 return EFI_DEVICE_ERROR;\r
326 }\r
a41b5272 327 }\r
8536cc4b 328 return EFI_SUCCESS;\r
a41b5272 329}\r
330\r
331/**\r
332 This function is used to poll for the DRQ bit clear in the Status\r
333 Register. DRQ is cleared when the device is finished transferring data.\r
334 So this function is called after data transfer is finished.\r
335\r
8536cc4b 336 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 337 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 338 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 339\r
340 @retval EFI_SUCCESS DRQ bit clear within the time out.\r
341\r
342 @retval EFI_TIMEOUT DRQ bit not clear within the time out.\r
343\r
344 @note\r
345 Read Status Register will clear interrupt status.\r
346\r
347**/\r
348EFI_STATUS\r
349EFIAPI\r
350DRQClear (\r
351 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
352 IN EFI_IDE_REGISTERS *IdeRegisters,\r
353 IN UINT64 Timeout\r
354 )\r
355{\r
ab82122d 356 UINT64 Delay;\r
a41b5272 357 UINT8 StatusRegister;\r
ab82122d 358 BOOLEAN InfiniteWait;\r
a41b5272 359\r
360 ASSERT (PciIo != NULL);\r
361 ASSERT (IdeRegisters != NULL);\r
362\r
ab82122d
TF		 363 if (Timeout == 0) {\r
364 InfiniteWait = TRUE;\r
365 } else {\r
366 InfiniteWait = FALSE;\r
367 }\r
368\r
369 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 370 do {\r
371 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
372\r
373 //\r
8536cc4b 374 // Wait for BSY == 0, then judge if DRQ is clear\r
a41b5272 375 //\r
8536cc4b 376 if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
377 if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
378 return EFI_DEVICE_ERROR;\r
379 } else {\r
380 return EFI_SUCCESS;\r
a41b5272 381 }\r
382 }\r
383\r
384 //\r
8536cc4b 385 // Stall for 100 microseconds.\r
a41b5272 386 //\r
387 MicroSecondDelay (100);\r
388\r
389 Delay--;\r
390\r
ab82122d 391 } while (InfiniteWait || (Delay > 0));\r
a41b5272 392\r
8536cc4b 393 return EFI_TIMEOUT;\r
a41b5272 394}\r
395/**\r
396 This function is used to poll for the DRQ bit clear in the Alternate\r
397 Status Register. DRQ is cleared when the device is finished\r
398 transferring data. So this function is called after data transfer\r
399 is finished.\r
400\r
8536cc4b 401 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 402 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 403 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 404\r
405 @retval EFI_SUCCESS DRQ bit clear within the time out.\r
406\r
407 @retval EFI_TIMEOUT DRQ bit not clear within the time out.\r
408 @note Read Alternate Status Register will not clear interrupt status.\r
409\r
410**/\r
411EFI_STATUS\r
412EFIAPI\r
413DRQClear2 (\r
414 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
415 IN EFI_IDE_REGISTERS *IdeRegisters,\r
416 IN UINT64 Timeout\r
417 )\r
418{\r
ab82122d 419 UINT64 Delay;\r
a41b5272 420 UINT8 AltRegister;\r
ab82122d 421 BOOLEAN InfiniteWait;\r
a41b5272 422\r
423 ASSERT (PciIo != NULL);\r
424 ASSERT (IdeRegisters != NULL);\r
425\r
ab82122d
TF		 426 if (Timeout == 0) {\r
427 InfiniteWait = TRUE;\r
428 } else {\r
429 InfiniteWait = FALSE;\r
430 }\r
431\r
432 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 433 do {\r
434 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
435\r
436 //\r
8536cc4b 437 // Wait for BSY == 0, then judge if DRQ is clear\r
a41b5272 438 //\r
8536cc4b 439 if ((AltRegister & ATA_STSREG_BSY) == 0) {\r
440 if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
441 return EFI_DEVICE_ERROR;\r
442 } else {\r
443 return EFI_SUCCESS;\r
a41b5272 444 }\r
445 }\r
446\r
447 //\r
448 // Stall for 100 microseconds.\r
449 //\r
450 MicroSecondDelay (100);\r
451\r
452 Delay--;\r
453\r
ab82122d 454 } while (InfiniteWait || (Delay > 0));\r
a41b5272 455\r
8536cc4b 456 return EFI_TIMEOUT;\r
a41b5272 457}\r
458\r
459/**\r
460 This function is used to poll for the DRQ bit set in the\r
461 Status Register.\r
462 DRQ is set when the device is ready to transfer data. So this function\r
463 is called after the command is sent to the device and before required\r
464 data is transferred.\r
465\r
8536cc4b 466 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 467 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 468 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 469\r
470 @retval EFI_SUCCESS DRQ bit set within the time out.\r
471 @retval EFI_TIMEOUT DRQ bit not set within the time out.\r
472 @retval EFI_ABORTED DRQ bit not set caused by the command abort.\r
473\r
474 @note Read Status Register will clear interrupt status.\r
475\r
476**/\r
477EFI_STATUS\r
478EFIAPI\r
479DRQReady (\r
480 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
481 IN EFI_IDE_REGISTERS *IdeRegisters,\r
482 IN UINT64 Timeout\r
483 )\r
484{\r
ab82122d 485 UINT64 Delay;\r
a41b5272 486 UINT8 StatusRegister;\r
487 UINT8 ErrorRegister;\r
ab82122d 488 BOOLEAN InfiniteWait;\r
a41b5272 489\r
490 ASSERT (PciIo != NULL);\r
491 ASSERT (IdeRegisters != NULL);\r
492\r
ab82122d
TF		 493 if (Timeout == 0) {\r
494 InfiniteWait = TRUE;\r
495 } else {\r
496 InfiniteWait = FALSE;\r
497 }\r
498\r
499 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 500 do {\r
501 //\r
8536cc4b 502 // Read Status Register will clear interrupt\r
a41b5272 503 //\r
504 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
505\r
506 //\r
8536cc4b 507 // Wait for BSY == 0, then judge if DRQ is clear or ERR is set\r
a41b5272 508 //\r
8536cc4b 509 if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
510 if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
511 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
a41b5272 512\r
8536cc4b 513 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
514 return EFI_ABORTED;\r
515 }\r
516 return EFI_DEVICE_ERROR;\r
517 }\r
a41b5272 518\r
8536cc4b 519 if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
520 return EFI_SUCCESS;\r
521 } else {\r
522 return EFI_NOT_READY;\r
a41b5272 523 }\r
524 }\r
525\r
526 //\r
527 // Stall for 100 microseconds.\r
528 //\r
529 MicroSecondDelay (100);\r
530\r
531 Delay--;\r
ab82122d 532 } while (InfiniteWait || (Delay > 0));\r
a41b5272 533\r
8536cc4b 534 return EFI_TIMEOUT;\r
a41b5272 535}\r
536/**\r
537 This function is used to poll for the DRQ bit set in the Alternate Status Register.\r
1aff716a 538 DRQ is set when the device is ready to transfer data. So this function is called after\r
a41b5272 539 the command is sent to the device and before required data is transferred.\r
540\r
8536cc4b 541 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 542 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 543 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 544\r
545 @retval EFI_SUCCESS DRQ bit set within the time out.\r
546 @retval EFI_TIMEOUT DRQ bit not set within the time out.\r
547 @retval EFI_ABORTED DRQ bit not set caused by the command abort.\r
548 @note Read Alternate Status Register will not clear interrupt status.\r
549\r
550**/\r
551EFI_STATUS\r
552EFIAPI\r
553DRQReady2 (\r
554 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
555 IN EFI_IDE_REGISTERS *IdeRegisters,\r
556 IN UINT64 Timeout\r
557 )\r
558{\r
ab82122d 559 UINT64 Delay;\r
a41b5272 560 UINT8 AltRegister;\r
561 UINT8 ErrorRegister;\r
ab82122d 562 BOOLEAN InfiniteWait;\r
a41b5272 563\r
564 ASSERT (PciIo != NULL);\r
565 ASSERT (IdeRegisters != NULL);\r
566\r
ab82122d
TF		 567 if (Timeout == 0) {\r
568 InfiniteWait = TRUE;\r
569 } else {\r
570 InfiniteWait = FALSE;\r
571 }\r
572\r
573 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 574\r
575 do {\r
576 //\r
8536cc4b 577 // Read Alternate Status Register will not clear interrupt status\r
a41b5272 578 //\r
579 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
580 //\r
8536cc4b 581 // Wait for BSY == 0, then judge if DRQ is clear or ERR is set\r
a41b5272 582 //\r
8536cc4b 583 if ((AltRegister & ATA_STSREG_BSY) == 0) {\r
584 if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
585 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
a41b5272 586\r
8536cc4b 587 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
588 return EFI_ABORTED;\r
589 }\r
590 return EFI_DEVICE_ERROR;\r
591 }\r
a41b5272 592\r
8536cc4b 593 if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
594 return EFI_SUCCESS;\r
595 } else {\r
596 return EFI_NOT_READY;\r
a41b5272 597 }\r
598 }\r
599\r
600 //\r
601 // Stall for 100 microseconds.\r
602 //\r
603 MicroSecondDelay (100);\r
604\r
605 Delay--;\r
ab82122d 606 } while (InfiniteWait || (Delay > 0));\r
a41b5272 607\r
8536cc4b 608 return EFI_TIMEOUT;\r
a41b5272 609}\r
610\r
611/**\r
612 This function is used to poll for the DRDY bit set in the Status Register. DRDY\r
1aff716a 613 bit is set when the device is ready to accept command. Most ATA commands must be\r
a41b5272 614 sent after DRDY set except the ATAPI Packet Command.\r
615\r
8536cc4b 616 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 617 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 618 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 619\r
620 @retval EFI_SUCCESS DRDY bit set within the time out.\r
621 @retval EFI_TIMEOUT DRDY bit not set within the time out.\r
622\r
623 @note Read Status Register will clear interrupt status.\r
624**/\r
625EFI_STATUS\r
626EFIAPI\r
627DRDYReady (\r
628 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
629 IN EFI_IDE_REGISTERS *IdeRegisters,\r
630 IN UINT64 Timeout\r
631 )\r
632{\r
ab82122d 633 UINT64 Delay;\r
a41b5272 634 UINT8 StatusRegister;\r
635 UINT8 ErrorRegister;\r
ab82122d 636 BOOLEAN InfiniteWait;\r
a41b5272 637\r
638 ASSERT (PciIo != NULL);\r
639 ASSERT (IdeRegisters != NULL);\r
640\r
ab82122d
TF		 641 if (Timeout == 0) {\r
642 InfiniteWait = TRUE;\r
643 } else {\r
644 InfiniteWait = FALSE;\r
645 }\r
646\r
647 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 648 do {\r
649 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
650 //\r
8536cc4b 651 // Wait for BSY == 0, then judge if DRDY is set or ERR is set\r
a41b5272 652 //\r
8536cc4b 653 if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
654 if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
655 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
a41b5272 656\r
8536cc4b 657 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
658 return EFI_ABORTED;\r
659 }\r
660 return EFI_DEVICE_ERROR;\r
661 }\r
a41b5272 662\r
8536cc4b 663 if ((StatusRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {\r
664 return EFI_SUCCESS;\r
665 } else {\r
666 return EFI_DEVICE_ERROR;\r
a41b5272 667 }\r
668 }\r
669\r
670 //\r
671 // Stall for 100 microseconds.\r
672 //\r
673 MicroSecondDelay (100);\r
674\r
675 Delay--;\r
ab82122d 676 } while (InfiniteWait || (Delay > 0));\r
a41b5272 677\r
8536cc4b 678 return EFI_TIMEOUT;\r
a41b5272 679}\r
680\r
681/**\r
1aff716a 682 This function is used to poll for the DRDY bit set in the Alternate Status Register.\r
683 DRDY bit is set when the device is ready to accept command. Most ATA commands must\r
a41b5272 684 be sent after DRDY set except the ATAPI Packet Command.\r
685\r
8536cc4b 686 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
a41b5272 687 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 688 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 689\r
690 @retval EFI_SUCCESS DRDY bit set within the time out.\r
691 @retval EFI_TIMEOUT DRDY bit not set within the time out.\r
692\r
693 @note Read Alternate Status Register will clear interrupt status.\r
694\r
695**/\r
696EFI_STATUS\r
697EFIAPI\r
698DRDYReady2 (\r
699 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
700 IN EFI_IDE_REGISTERS *IdeRegisters,\r
701 IN UINT64 Timeout\r
702 )\r
703{\r
ab82122d 704 UINT64 Delay;\r
a41b5272 705 UINT8 AltRegister;\r
706 UINT8 ErrorRegister;\r
ab82122d 707 BOOLEAN InfiniteWait;\r
a41b5272 708\r
709 ASSERT (PciIo != NULL);\r
710 ASSERT (IdeRegisters != NULL);\r
711\r
ab82122d
TF		 712 if (Timeout == 0) {\r
713 InfiniteWait = TRUE;\r
714 } else {\r
715 InfiniteWait = FALSE;\r
716 }\r
717\r
718 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 719 do {\r
720 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
721 //\r
8536cc4b 722 // Wait for BSY == 0, then judge if DRDY is set or ERR is set\r
a41b5272 723 //\r
8536cc4b 724 if ((AltRegister & ATA_STSREG_BSY) == 0) {\r
725 if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
726 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
a41b5272 727\r
8536cc4b 728 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
729 return EFI_ABORTED;\r
730 }\r
731 return EFI_DEVICE_ERROR;\r
732 }\r
a41b5272 733\r
8536cc4b 734 if ((AltRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {\r
735 return EFI_SUCCESS;\r
736 } else {\r
737 return EFI_DEVICE_ERROR;\r
a41b5272 738 }\r
739 }\r
740\r
741 //\r
742 // Stall for 100 microseconds.\r
743 //\r
744 MicroSecondDelay (100);\r
745\r
746 Delay--;\r
ab82122d 747 } while (InfiniteWait || (Delay > 0));\r
a41b5272 748\r
8536cc4b 749 return EFI_TIMEOUT;\r
a41b5272 750}\r
751\r
752/**\r
753 This function is used to poll for the BSY bit clear in the Status Register. BSY\r
754 is clear when the device is not busy. Every command must be sent after device is not busy.\r
755\r
756 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
757 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 758 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 759\r
760 @retval EFI_SUCCESS BSY bit clear within the time out.\r
761 @retval EFI_TIMEOUT BSY bit not clear within the time out.\r
762\r
763 @note Read Status Register will clear interrupt status.\r
764**/\r
765EFI_STATUS\r
766EFIAPI\r
767WaitForBSYClear (\r
768 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
769 IN EFI_IDE_REGISTERS *IdeRegisters,\r
770 IN UINT64 Timeout\r
771 )\r
772{\r
ab82122d 773 UINT64 Delay;\r
a41b5272 774 UINT8 StatusRegister;\r
ab82122d 775 BOOLEAN InfiniteWait;\r
a41b5272 776\r
777 ASSERT (PciIo != NULL);\r
778 ASSERT (IdeRegisters != NULL);\r
779\r
ab82122d
TF		 780 if (Timeout == 0) {\r
781 InfiniteWait = TRUE;\r
782 } else {\r
783 InfiniteWait = FALSE;\r
784 }\r
785\r
786 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 787 do {\r
788 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
789\r
790 if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {\r
8536cc4b 791 return EFI_SUCCESS;\r
a41b5272 792 }\r
793\r
794 //\r
795 // Stall for 100 microseconds.\r
796 //\r
797 MicroSecondDelay (100);\r
798\r
799 Delay--;\r
800\r
ab82122d 801 } while (InfiniteWait || (Delay > 0));\r
a41b5272 802\r
8536cc4b 803 return EFI_TIMEOUT;\r
a41b5272 804}\r
805\r
806/**\r
807 This function is used to poll for the BSY bit clear in the Status Register. BSY\r
808 is clear when the device is not busy. Every command must be sent after device is not busy.\r
809\r
810 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
811 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 812 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 813\r
814 @retval EFI_SUCCESS BSY bit clear within the time out.\r
815 @retval EFI_TIMEOUT BSY bit not clear within the time out.\r
816\r
817 @note Read Status Register will clear interrupt status.\r
818**/\r
819EFI_STATUS\r
820EFIAPI\r
821WaitForBSYClear2 (\r
822 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
823 IN EFI_IDE_REGISTERS *IdeRegisters,\r
824 IN UINT64 Timeout\r
825 )\r
826{\r
ab82122d 827 UINT64 Delay;\r
a41b5272 828 UINT8 AltStatusRegister;\r
ab82122d 829 BOOLEAN InfiniteWait;\r
a41b5272 830\r
831 ASSERT (PciIo != NULL);\r
832 ASSERT (IdeRegisters != NULL);\r
833\r
ab82122d
TF		 834 if (Timeout == 0) {\r
835 InfiniteWait = TRUE;\r
836 } else {\r
837 InfiniteWait = FALSE;\r
838 }\r
839\r
840 Delay = DivU64x32(Timeout, 1000) + 1;\r
a41b5272 841 do {\r
842 AltStatusRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
843\r
844 if ((AltStatusRegister & ATA_STSREG_BSY) == 0x00) {\r
8536cc4b 845 return EFI_SUCCESS;\r
a41b5272 846 }\r
847\r
848 //\r
849 // Stall for 100 microseconds.\r
850 //\r
851 MicroSecondDelay (100);\r
852\r
853 Delay--;\r
854\r
ab82122d 855 } while (InfiniteWait || (Delay > 0));\r
a41b5272 856\r
8536cc4b 857 return EFI_TIMEOUT;\r
a41b5272 858}\r
859\r
860/**\r
1aff716a 861 Get IDE i/o port registers' base addresses by mode.\r
a41b5272 862\r
863 In 'Compatibility' mode, use fixed addresses.\r
864 In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's\r
865 Configuration Space.\r
866\r
867 The steps to get IDE i/o port registers' base addresses for each channel\r
868 as follows:\r
869\r
870 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE\r
871 controller's Configuration Space to determine the operating mode.\r
872\r
873 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.\r
874 ___________________________________________\r
875 | | Command Block | Control Block |\r
876 | Channel | Registers | Registers |\r
877 |___________|_______________|_______________|\r
878 | Primary | 1F0h - 1F7h | 3F6h - 3F7h |\r
879 |___________|_______________|_______________|\r
880 | Secondary | 170h - 177h | 376h - 377h |\r
881 |___________|_______________|_______________|\r
882\r
883 Table 1. Compatibility resource mappings\r
1aff716a 884\r
a41b5272 885 b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs\r
886 in IDE controller's PCI Configuration Space, shown in the Table 2 below.\r
887 ___________________________________________________\r
888 | | Command Block | Control Block |\r
889 | Channel | Registers | Registers |\r
890 |___________|___________________|___________________|\r
891 | Primary | BAR at offset 0x10| BAR at offset 0x14|\r
892 |___________|___________________|___________________|\r
893 | Secondary | BAR at offset 0x18| BAR at offset 0x1C|\r
894 |___________|___________________|___________________|\r
895\r
896 Table 2. BARs for Register Mapping\r
897\r
898 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r
899 @param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to\r
900 store the IDE i/o port registers' base addresses\r
1aff716a 901\r
a41b5272 902 @retval EFI_UNSUPPORTED Return this value when the BARs is not IO type\r
903 @retval EFI_SUCCESS Get the Base address successfully\r
904 @retval Other Read the pci configureation data error\r
905\r
906**/\r
907EFI_STATUS\r
908EFIAPI\r
909GetIdeRegisterIoAddr (\r
910 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
911 IN OUT EFI_IDE_REGISTERS *IdeRegisters\r
912 )\r
913{\r
914 EFI_STATUS Status;\r
915 PCI_TYPE00 PciData;\r
916 UINT16 CommandBlockBaseAddr;\r
917 UINT16 ControlBlockBaseAddr;\r
918 UINT16 BusMasterBaseAddr;\r
919\r
920 if ((PciIo == NULL) || (IdeRegisters == NULL)) {\r
921 return EFI_INVALID_PARAMETER;\r
922 }\r
923\r
924 Status = PciIo->Pci.Read (\r
925 PciIo,\r
926 EfiPciIoWidthUint8,\r
927 0,\r
928 sizeof (PciData),\r
929 &PciData\r
930 );\r
931\r
932 if (EFI_ERROR (Status)) {\r
933 return Status;\r
934 }\r
935\r
936 BusMasterBaseAddr = (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));\r
937\r
938 if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {\r
939 CommandBlockBaseAddr = 0x1f0;\r
940 ControlBlockBaseAddr = 0x3f6;\r
941 } else {\r
942 //\r
943 // The BARs should be of IO type\r
944 //\r
945 if ((PciData.Device.Bar[0] & BIT0) == 0 ||\r
946 (PciData.Device.Bar[1] & BIT0) == 0) {\r
947 return EFI_UNSUPPORTED;\r
948 }\r
949\r
950 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);\r
951 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);\r
952 }\r
953\r
954 //\r
955 // Calculate IDE primary channel I/O register base address.\r
956 //\r
957 IdeRegisters[EfiIdePrimary].Data = CommandBlockBaseAddr;\r
958 IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);\r
959 IdeRegisters[EfiIdePrimary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);\r
960 IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);\r
961 IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);\r
962 IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);\r
963 IdeRegisters[EfiIdePrimary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);\r
964 IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);\r
965 IdeRegisters[EfiIdePrimary].AltOrDev = ControlBlockBaseAddr;\r
966 IdeRegisters[EfiIdePrimary].BusMasterBaseAddr = BusMasterBaseAddr;\r
967\r
968 if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {\r
969 CommandBlockBaseAddr = 0x170;\r
970 ControlBlockBaseAddr = 0x376;\r
971 } else {\r
972 //\r
973 // The BARs should be of IO type\r
974 //\r
975 if ((PciData.Device.Bar[2] & BIT0) == 0 ||\r
976 (PciData.Device.Bar[3] & BIT0) == 0) {\r
977 return EFI_UNSUPPORTED;\r
978 }\r
979\r
980 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);\r
981 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);\r
982 }\r
983\r
984 //\r
985 // Calculate IDE secondary channel I/O register base address.\r
986 //\r
987 IdeRegisters[EfiIdeSecondary].Data = CommandBlockBaseAddr;\r
988 IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);\r
989 IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);\r
990 IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);\r
991 IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);\r
992 IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);\r
993 IdeRegisters[EfiIdeSecondary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);\r
994 IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);\r
995 IdeRegisters[EfiIdeSecondary].AltOrDev = ControlBlockBaseAddr;\r
aca84419 996 IdeRegisters[EfiIdeSecondary].BusMasterBaseAddr = (UINT16) (BusMasterBaseAddr + 0x8);\r
a41b5272 997\r
998 return EFI_SUCCESS;\r
999}\r
1000\r
1001/**\r
1002 This function is used to implement the Soft Reset on the specified device. But,\r
1aff716a 1003 the ATA Soft Reset mechanism is so strong a reset method that it will force\r
a41b5272 1004 resetting on both devices connected to the same cable.\r
1005\r
1006 It is called by IdeBlkIoReset(), a interface function of Block\r
1007 I/O protocol.\r
1008\r
1009 This function can also be used by the ATAPI device to perform reset when\r
1010 ATAPI Reset command is failed.\r
1011\r
1012 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
1013 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
8536cc4b 1014 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 1015\r
1016 @retval EFI_SUCCESS Soft reset completes successfully.\r
1017 @retval EFI_DEVICE_ERROR Any step during the reset process is failed.\r
1018\r
1019 @note The registers initial values after ATA soft reset are different\r
1020 to the ATA device and ATAPI device.\r
1021**/\r
1022EFI_STATUS\r
1023EFIAPI\r
1024AtaSoftReset (\r
1025 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1026 IN EFI_IDE_REGISTERS *IdeRegisters,\r
1027 IN UINT64 Timeout\r
1028 )\r
1029{\r
1030 UINT8 DeviceControl;\r
1031\r
1032 DeviceControl = 0;\r
1033 //\r
1034 // disable Interrupt and set SRST bit to initiate soft reset\r
1035 //\r
1036 DeviceControl = ATA_CTLREG_SRST | ATA_CTLREG_IEN_L;\r
1037\r
1038 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);\r
1039\r
1040 //\r
1041 // SRST should assert for at least 5 us, we use 10 us for\r
1042 // better compatibility\r
1043 //\r
1044 MicroSecondDelay (10);\r
1045\r
1046 //\r
1047 // Enable interrupt to support UDMA, and clear SRST bit\r
1048 //\r
1049 DeviceControl = 0;\r
1050 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);\r
1051\r
1052 //\r
1053 // Wait for at least 10 ms to check BSY status, we use 10 ms\r
1054 // for better compatibility\r
1aff716a 1055 //\r
a41b5272 1056 MicroSecondDelay (10000);\r
1057\r
1058 //\r
1059 // slave device needs at most 31ms to clear BSY\r
1060 //\r
1061 if (WaitForBSYClear (PciIo, IdeRegisters, Timeout) == EFI_TIMEOUT) {\r
1062 return EFI_DEVICE_ERROR;\r
1063 }\r
1064\r
1065 return EFI_SUCCESS;\r
1066}\r
1067\r
1068/**\r
1069 Send ATA Ext command into device with NON_DATA protocol.\r
1070\r
1071 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
1072 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
1073 @param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.\r
8536cc4b 1074 @param Timeout The time to complete the command, uses 100ns as a unit.\r
a41b5272 1075\r
1076 @retval EFI_SUCCESS Reading succeed\r
1077 @retval EFI_DEVICE_ERROR Error executing commands on this device.\r
1078\r
1079**/\r
1080EFI_STATUS\r
1081EFIAPI\r
1082AtaIssueCommand (\r
1083 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1084 IN EFI_IDE_REGISTERS *IdeRegisters,\r
1085 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
1086 IN UINT64 Timeout\r
1087 )\r
1088{\r
1089 EFI_STATUS Status;\r
1090 UINT8 DeviceHead;\r
1091 UINT8 AtaCommand;\r
1092\r
1093 ASSERT (PciIo != NULL);\r
1094 ASSERT (IdeRegisters != NULL);\r
1095 ASSERT (AtaCommandBlock != NULL);\r
1096\r
1097 DeviceHead = AtaCommandBlock->AtaDeviceHead;\r
1098 AtaCommand = AtaCommandBlock->AtaCommand;\r
1099\r
1100 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);\r
1101 if (EFI_ERROR (Status)) {\r
1102 return EFI_DEVICE_ERROR;\r
1103 }\r
1104\r
1105 //\r
1106 // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)\r
1107 //\r
1108 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8) (0xe0 | DeviceHead));\r
1109\r
1110 //\r
1111 // set all the command parameters\r
1112 // Before write to all the following registers, BSY and DRQ must be 0.\r
1113 //\r
1114 Status = DRQClear2 (PciIo, IdeRegisters, Timeout);\r
1115 if (EFI_ERROR (Status)) {\r
1116 return EFI_DEVICE_ERROR;\r
1117 }\r
1118\r
1119 //\r
1120 // Fill the feature register, which is a two-byte FIFO. Need write twice.\r
1121 //\r
1122 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeaturesExp);\r
1123 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeatures);\r
1124\r
1125 //\r
1126 // Fill the sector count register, which is a two-byte FIFO. Need write twice.\r
1127 //\r
1128 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCountExp);\r
1129 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCount);\r
1130\r
1131 //\r
1132 // Fill the start LBA registers, which are also two-byte FIFO\r
1133 //\r
1134 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumberExp);\r
1135 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumber);\r
1136\r
1137 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLowExp);\r
1138 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLow);\r
1139\r
1140 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHighExp);\r
1141 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHigh);\r
1142\r
1143 //\r
1144 // Send command via Command Register\r
1145 //\r
1146 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, AtaCommand);\r
1147\r
1148 //\r
1149 // Stall at least 400 microseconds.\r
1150 //\r
1151 MicroSecondDelay (400);\r
1152\r
1153 return EFI_SUCCESS;\r
1154}\r
1155\r
1156/**\r
1157 This function is used to send out ATA commands conforms to the PIO Data In Protocol.\r
1158\r
490b5ea1 1159 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data\r
1160 structure.\r
1161 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
1162 @param[in, out] Buffer A pointer to the source buffer for the data.\r
1163 @param[in] ByteCount The length of the data.\r
86d8e199 1164 @param[in] Read Flag used to determine the data transfer direction.\r
490b5ea1 1165 Read equals 1, means data transferred from device\r
1166 to host;Read equals 0, means data transferred\r
1167 from host to device.\r
1168 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.\r
86d8e199 1169 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
8536cc4b 1170 @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
490b5ea1 1171 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
1172 used by non-blocking mode.\r
1aff716a 1173\r
a41b5272 1174 @retval EFI_SUCCESS send out the ATA command and device send required data successfully.\r
1175 @retval EFI_DEVICE_ERROR command sent failed.\r
1176\r
1177**/\r
1178EFI_STATUS\r
1179EFIAPI\r
1aff716a 1180AtaPioDataInOut (\r
a41b5272 1181 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1182 IN EFI_IDE_REGISTERS *IdeRegisters,\r
1183 IN OUT VOID *Buffer,\r
1184 IN UINT64 ByteCount,\r
1185 IN BOOLEAN Read,\r
1186 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
1187 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
490b5ea1 1188 IN UINT64 Timeout,\r
1189 IN ATA_NONBLOCK_TASK *Task\r
a41b5272 1190 )\r
1191{\r
1192 UINTN WordCount;\r
1193 UINTN Increment;\r
1194 UINT16 *Buffer16;\r
1195 EFI_STATUS Status;\r
1196\r
1197 if ((PciIo == NULL) || (IdeRegisters == NULL) || (Buffer == NULL) || (AtaCommandBlock == NULL)) {\r
1198 return EFI_INVALID_PARAMETER;\r
1199 }\r
1200\r
1201 //\r
1202 // Issue ATA command\r
1203 //\r
1204 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);\r
1205 if (EFI_ERROR (Status)) {\r
1206 Status = EFI_DEVICE_ERROR;\r
1207 goto Exit;\r
1208 }\r
1209\r
1210 Buffer16 = (UINT16 *) Buffer;\r
1211\r
1212 //\r
1213 // According to PIO data in protocol, host can perform a series of reads to\r
1214 // the data register after each time device set DRQ ready;\r
1215 // The data size of "a series of read" is command specific.\r
1216 // For most ATA command, data size received from device will not exceed\r
1217 // 1 sector, hence the data size for "a series of read" can be the whole data\r
1218 // size of one command request.\r
1219 // For ATA command such as Read Sector command, the data size of one ATA\r
1220 // command request is often larger than 1 sector, according to the\r
1221 // Read Sector command, the data size of "a series of read" is exactly 1\r
1222 // sector.\r
1223 // Here for simplification reason, we specify the data size for\r
1224 // "a series of read" to 1 sector (256 words) if data size of one ATA command\r
1225 // request is larger than 256 words.\r
1226 //\r
1227 Increment = 256;\r
1228\r
1229 //\r
1230 // used to record bytes of currently transfered data\r
1231 //\r
1232 WordCount = 0;\r
1233\r
1234 while (WordCount < RShiftU64(ByteCount, 1)) {\r
1235 //\r
1236 // Poll DRQ bit set, data transfer can be performed only when DRQ is ready\r
1237 //\r
1238 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);\r
1aff716a 1239 if (EFI_ERROR (Status)) {\r
a41b5272 1240 Status = EFI_DEVICE_ERROR;\r
1241 goto Exit;\r
1242 }\r
1243\r
1244 //\r
1245 // Get the byte count for one series of read\r
1246 //\r
1247 if ((WordCount + Increment) > RShiftU64(ByteCount, 1)) {\r
1248 Increment = (UINTN)(RShiftU64(ByteCount, 1) - WordCount);\r
1249 }\r
1250\r
1251 if (Read) {\r
1252 IdeReadPortWMultiple (\r
1253 PciIo,\r
1254 IdeRegisters->Data,\r
1255 Increment,\r
1256 Buffer16\r
1257 );\r
1258 } else {\r
1259 IdeWritePortWMultiple (\r
1260 PciIo,\r
1261 IdeRegisters->Data,\r
1262 Increment,\r
1263 Buffer16\r
1264 );\r
1265 }\r
1266\r
1267 Status = CheckStatusRegister (PciIo, IdeRegisters);\r
1268 if (EFI_ERROR (Status)) {\r
1269 Status = EFI_DEVICE_ERROR;\r
1270 goto Exit;\r
1271 }\r
1272\r
1273 WordCount += Increment;\r
1274 Buffer16 += Increment;\r
1275 }\r
1276\r
1277 Status = DRQClear (PciIo, IdeRegisters, Timeout);\r
1278 if (EFI_ERROR (Status)) {\r
1279 Status = EFI_DEVICE_ERROR;\r
1280 goto Exit;\r
1281 }\r
1282\r
1283Exit:\r
1284 //\r
1285 // Dump All Ide registers to ATA_STATUS_BLOCK\r
1286 //\r
1287 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);\r
1288\r
490b5ea1 1289 //\r
1290 // Not support the Non-blocking now,just do the blocking process.\r
1291 //\r
a41b5272 1292 return Status;\r
1293}\r
1294\r
1295/**\r
1296 Send ATA command into device with NON_DATA protocol\r
1297\r
490b5ea1 1298 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE\r
1299 data structure.\r
1300 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
1301 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data\r
1302 structure.\r
1303 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
8536cc4b 1304 @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
490b5ea1 1305 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
1306 used by non-blocking mode.\r
a41b5272 1307\r
1308 @retval EFI_SUCCESS Reading succeed\r
1309 @retval EFI_ABORTED Command failed\r
1310 @retval EFI_DEVICE_ERROR Device status error.\r
1311\r
1312**/\r
1313EFI_STATUS\r
1314EFIAPI\r
1aff716a 1315AtaNonDataCommandIn (\r
a41b5272 1316 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1317 IN EFI_IDE_REGISTERS *IdeRegisters,\r
1318 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
1319 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
490b5ea1 1320 IN UINT64 Timeout,\r
1321 IN ATA_NONBLOCK_TASK *Task\r
a41b5272 1322 )\r
1323{\r
1324 EFI_STATUS Status;\r
1325\r
1326 if ((PciIo == NULL) || (IdeRegisters == NULL) || (AtaCommandBlock == NULL)) {\r
1327 return EFI_INVALID_PARAMETER;\r
1328 }\r
1329\r
1330 //\r
1331 // Issue ATA command\r
1332 //\r
1333 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);\r
1334 if (EFI_ERROR (Status)) {\r
1335 Status = EFI_DEVICE_ERROR;\r
1336 goto Exit;\r
1337 }\r
1338\r
1339 //\r
1340 // Wait for command completion\r
1341 //\r
1342 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);\r
1343 if (EFI_ERROR (Status)) {\r
1344 Status = EFI_DEVICE_ERROR;\r
1345 goto Exit;\r
1346 }\r
1aff716a 1347\r
a41b5272 1348 Status = CheckStatusRegister (PciIo, IdeRegisters);\r
1349 if (EFI_ERROR (Status)) {\r
1350 Status = EFI_DEVICE_ERROR;\r
1351 goto Exit;\r
1352 }\r
1353\r
1354Exit:\r
1355 //\r
1356 // Dump All Ide registers to ATA_STATUS_BLOCK\r
1357 //\r
1358 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);\r
1aff716a 1359\r
490b5ea1 1360 //\r
1361 // Not support the Non-blocking now,just do the blocking process.\r
1362 //\r
1363 return Status;\r
1364}\r
1365\r
1366/**\r
1367 Wait for memory to be set.\r
1aff716a 1368\r
490b5ea1 1369 @param[in] PciIo The PCI IO protocol instance.\r
8536cc4b 1370 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
ab82122d 1371 @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
490b5ea1 1372\r
1373 @retval EFI_DEVICE_ERROR The memory is not set.\r
1374 @retval EFI_TIMEOUT The memory setting is time out.\r
1375 @retval EFI_SUCCESS The memory is correct set.\r
1376\r
1377**/\r
1378EFI_STATUS\r
1379AtaUdmStatusWait (\r
ab82122d
TF		 1380 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1381 IN EFI_IDE_REGISTERS *IdeRegisters,\r
1382 IN UINT64 Timeout\r
1aff716a 1383 )\r
490b5ea1 1384{\r
1385 UINT8 RegisterValue;\r
1386 EFI_STATUS Status;\r
8536cc4b 1387 UINT16 IoPortForBmis;\r
ab82122d
TF		 1388 UINT64 Delay;\r
1389 BOOLEAN InfiniteWait;\r
1390\r
1391 if (Timeout == 0) {\r
1392 InfiniteWait = TRUE;\r
1393 } else {\r
1394 InfiniteWait = FALSE;\r
1395 }\r
490b5ea1 1396\r
ab82122d 1397 Delay = DivU64x32 (Timeout, 1000) + 1;\r
490b5ea1 1398\r
ab82122d 1399 do {\r
8536cc4b 1400 Status = CheckStatusRegister (PciIo, IdeRegisters);\r
1401 if (EFI_ERROR (Status)) {\r
1402 Status = EFI_DEVICE_ERROR;\r
1403 break;\r
1404 }\r
490b5ea1 1405\r
8536cc4b 1406 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
1407 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
490b5ea1 1408 if (((RegisterValue & BMIS_ERROR) != 0) || (Timeout == 0)) {\r
1409 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));\r
1410 Status = EFI_DEVICE_ERROR;\r
1411 break;\r
1412 }\r
1413\r
1414 if ((RegisterValue & BMIS_INTERRUPT) != 0) {\r
1415 Status = EFI_SUCCESS;\r
490b5ea1 1416 break;\r
1417 }\r
1418 //\r
ab82122d 1419 // Stall for 100 microseconds.\r
490b5ea1 1420 //\r
ab82122d
TF		 1421 MicroSecondDelay (100);\r
1422 Delay--;\r
1423 } while (InfiniteWait || (Delay > 0));\r
a41b5272 1424\r
1425 return Status;\r
1426}\r
1427\r
490b5ea1 1428/**\r
1429 Check if the memory to be set.\r
1aff716a 1430\r
490b5ea1 1431 @param[in] PciIo The PCI IO protocol instance.\r
1432 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
1433 used by non-blocking mode.\r
8536cc4b 1434 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
490b5ea1 1435\r
1436 @retval EFI_DEVICE_ERROR The memory setting met a issue.\r
1437 @retval EFI_NOT_READY The memory is not set.\r
1438 @retval EFI_TIMEOUT The memory setting is time out.\r
1439 @retval EFI_SUCCESS The memory is correct set.\r
1440\r
1441**/\r
1442EFI_STATUS\r
1443AtaUdmStatusCheck (\r
1444 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1445 IN ATA_NONBLOCK_TASK *Task,\r
8536cc4b 1446 IN EFI_IDE_REGISTERS *IdeRegisters\r
490b5ea1 1447 )\r
1448{\r
8536cc4b 1449 UINT8 RegisterValue;\r
1450 UINT16 IoPortForBmis;\r
1451 EFI_STATUS Status;\r
490b5ea1 1452\r
1453 Task->RetryTimes--;\r
8536cc4b 1454\r
1455 Status = CheckStatusRegister (PciIo, IdeRegisters);\r
1456 if (EFI_ERROR (Status)) {\r
1457 return EFI_DEVICE_ERROR;\r
1458 }\r
1459\r
1460 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
1461 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
490b5ea1 1462\r
1463 if ((RegisterValue & BMIS_ERROR) != 0) {\r
1464 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));\r
1465 return EFI_DEVICE_ERROR;\r
1466 }\r
1467\r
1468 if ((RegisterValue & BMIS_INTERRUPT) != 0) {\r
490b5ea1 1469 return EFI_SUCCESS;\r
1470 }\r
1471\r
ab82122d 1472 if (!Task->InfiniteWait && (Task->RetryTimes == 0)) {\r
490b5ea1 1473 return EFI_TIMEOUT;\r
1474 } else {\r
1475 //\r
1476 // The memory is not set.\r
1477 //\r
1478 return EFI_NOT_READY;\r
1479 }\r
1480}\r
a41b5272 1481\r
1482/**\r
1483 Perform an ATA Udma operation (Read, ReadExt, Write, WriteExt).\r
1484\r
490b5ea1 1485 @param[in] Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data\r
1486 structure.\r
1487 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
1488 @param[in] Read Flag used to determine the data transfer\r
1489 direction. Read equals 1, means data transferred\r
1490 from device to host;Read equals 0, means data\r
1491 transferred from host to device.\r
1492 @param[in] DataBuffer A pointer to the source buffer for the data.\r
1493 @param[in] DataLength The length of the data.\r
1494 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.\r
1495 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
8536cc4b 1496 @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
490b5ea1 1497 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
1498 used by non-blocking mode.\r
a41b5272 1499\r
1500 @retval EFI_SUCCESS the operation is successful.\r
1501 @retval EFI_OUT_OF_RESOURCES Build PRD table failed\r
1502 @retval EFI_UNSUPPORTED Unknown channel or operations command\r
1503 @retval EFI_DEVICE_ERROR Ata command execute failed\r
1504\r
1505**/\r
1506EFI_STATUS\r
1507EFIAPI\r
1508AtaUdmaInOut (\r
490b5ea1 1509 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
1510 IN EFI_IDE_REGISTERS *IdeRegisters,\r
1511 IN BOOLEAN Read,\r
1512 IN VOID *DataBuffer,\r
1513 IN UINT64 DataLength,\r
1514 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
1515 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
1516 IN UINT64 Timeout,\r
1517 IN ATA_NONBLOCK_TASK *Task\r
a41b5272 1518 )\r
1519{\r
1520 EFI_STATUS Status;\r
1521 UINT16 IoPortForBmic;\r
1522 UINT16 IoPortForBmis;\r
1523 UINT16 IoPortForBmid;\r
1524\r
a41b5272 1525 UINTN PrdTableSize;\r
1526 EFI_PHYSICAL_ADDRESS PrdTableMapAddr;\r
1527 VOID *PrdTableMap;\r
490b5ea1 1528 EFI_ATA_DMA_PRD *PrdBaseAddr;\r
2525e221 1529 EFI_ATA_DMA_PRD *TempPrdBaseAddr;\r
490b5ea1 1530 UINTN PrdTableNum;\r
a41b5272 1531\r
490b5ea1 1532 UINT8 RegisterValue;\r
a41b5272 1533 UINTN PageCount;\r
1534 UINTN ByteCount;\r
1535 UINTN ByteRemaining;\r
a41b5272 1536 UINT8 DeviceControl;\r
1537\r
1538 VOID *BufferMap;\r
1539 EFI_PHYSICAL_ADDRESS BufferMapAddress;\r
1540 EFI_PCI_IO_PROTOCOL_OPERATION PciIoOperation;\r
1541\r
1542 UINT8 DeviceHead;\r
490b5ea1 1543 EFI_PCI_IO_PROTOCOL *PciIo;\r
1544 EFI_TPL OldTpl;\r
a41b5272 1545\r
490b5ea1 1546\r
1547 Status = EFI_SUCCESS;\r
1548 PrdBaseAddr = NULL;\r
1549 PrdTableMap = NULL;\r
1550 BufferMap = NULL;\r
1551 PageCount = 0;\r
1552 PciIo = Instance->PciIo;\r
a41b5272 1553\r
1554 if ((PciIo == NULL) || (IdeRegisters == NULL) || (DataBuffer == NULL) || (AtaCommandBlock == NULL)) {\r
1555 return EFI_INVALID_PARAMETER;\r
1556 }\r
1557\r
490b5ea1 1558 //\r
1559 // Before starting the Blocking BlockIO operation, push to finish all non-blocking\r
1560 // BlockIO tasks.\r
1561 // Delay 1ms to simulate the blocking time out checking.\r
1562 //\r
1aff716a 1563 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
490b5ea1 1564 while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {\r
490b5ea1 1565 AsyncNonBlockingTransferRoutine (NULL, Instance);\r
490b5ea1 1566 //\r
1567 // Stall for 1 milliseconds.\r
1568 //\r
1569 MicroSecondDelay (1000);\r
1aff716a 1570 }\r
1571 gBS->RestoreTPL (OldTpl);\r
490b5ea1 1572\r
a41b5272 1573 //\r
1574 // The data buffer should be even alignment\r
1575 //\r
1576 if (((UINTN)DataBuffer & 0x1) != 0) {\r
1577 return EFI_INVALID_PARAMETER;\r
1578 }\r
1579\r
1580 //\r
490b5ea1 1581 // Set relevant IO Port address.\r
a41b5272 1582 //\r
490b5ea1 1583 IoPortForBmic = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIC_OFFSET);\r
1584 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
1585 IoPortForBmid = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);\r
a41b5272 1586\r
1587 //\r
1aff716a 1588 // For Blocking mode, start the command.\r
490b5ea1 1589 // For non-blocking mode, when the command is not started, start it, otherwise\r
1590 // go to check the status.\r
1aff716a 1591 //\r
490b5ea1 1592 if (((Task != NULL) && (!Task->IsStart)) || (Task == NULL)) {\r
1593 //\r
1594 // Calculate the number of PRD entry.\r
1595 // Every entry in PRD table can specify a 64K memory region.\r
1596 //\r
1597 PrdTableNum = (UINTN)(RShiftU64(DataLength, 16) + 1);\r
a41b5272 1598\r
490b5ea1 1599 //\r
1600 // Make sure that the memory region of PRD table is not cross 64K boundary\r
1601 //\r
1602 PrdTableSize = PrdTableNum * sizeof (EFI_ATA_DMA_PRD);\r
1603 if (PrdTableSize > 0x10000) {\r
1604 return EFI_INVALID_PARAMETER;\r
1605 }\r
a41b5272 1606\r
490b5ea1 1607 //\r
1608 // Allocate buffer for PRD table initialization.\r
1609 //\r
1610 PageCount = EFI_SIZE_TO_PAGES (PrdTableSize);\r
1611 Status = PciIo->AllocateBuffer (\r
1612 PciIo,\r
1613 AllocateAnyPages,\r
1614 EfiBootServicesData,\r
1615 PageCount,\r
1616 (VOID **)&PrdBaseAddr,\r
1617 0\r
1618 );\r
1619 if (EFI_ERROR (Status)) {\r
1620 return EFI_OUT_OF_RESOURCES;\r
1621 }\r
a41b5272 1622\r
490b5ea1 1623 ByteCount = EFI_PAGES_TO_SIZE (PageCount);\r
1624 Status = PciIo->Map (\r
1625 PciIo,\r
1626 EfiPciIoOperationBusMasterCommonBuffer,\r
1627 PrdBaseAddr,\r
1628 &ByteCount,\r
1629 &PrdTableMapAddr,\r
1630 &PrdTableMap\r
1631 );\r
1632 if (EFI_ERROR (Status) || (ByteCount != EFI_PAGES_TO_SIZE (PageCount))) {\r
1633 //\r
1634 // If the data length actually mapped is not equal to the requested amount,\r
1635 // it means the DMA operation may be broken into several discontinuous smaller chunks.\r
1636 // Can't handle this case.\r
1637 //\r
1638 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);\r
1639 return EFI_OUT_OF_RESOURCES;\r
1640 }\r
a41b5272 1641\r
490b5ea1 1642 ZeroMem ((VOID *) ((UINTN) PrdBaseAddr), ByteCount);\r
a41b5272 1643\r
490b5ea1 1644 //\r
1645 // Map the host address of DataBuffer to DMA master address.\r
1646 //\r
1647 if (Read) {\r
1648 PciIoOperation = EfiPciIoOperationBusMasterWrite;\r
1649 } else {\r
1650 PciIoOperation = EfiPciIoOperationBusMasterRead;\r
1651 }\r
a41b5272 1652\r
490b5ea1 1653 ByteCount = (UINTN)DataLength;\r
1654 Status = PciIo->Map (\r
1655 PciIo,\r
1656 PciIoOperation,\r
1657 DataBuffer,\r
1658 &ByteCount,\r
1659 &BufferMapAddress,\r
1660 &BufferMap\r
1661 );\r
1662 if (EFI_ERROR (Status) || (ByteCount != DataLength)) {\r
1663 PciIo->Unmap (PciIo, PrdTableMap);\r
1664 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);\r
1665 return EFI_OUT_OF_RESOURCES;\r
1666 }\r
1667\r
1668 //\r
1669 // According to Ata spec, it requires the buffer address and size to be even.\r
1670 //\r
1671 ASSERT ((BufferMapAddress & 0x1) == 0);\r
1672 ASSERT ((ByteCount & 0x1) == 0);\r
1673\r
1674 //\r
1675 // Fill the PRD table with appropriate bus master address of data buffer and data length.\r
1676 //\r
2525e221 1677 ByteRemaining = ByteCount;\r
1678 TempPrdBaseAddr = PrdBaseAddr;\r
490b5ea1 1679 while (ByteRemaining != 0) {\r
1680 if (ByteRemaining <= 0x10000) {\r
2525e221 1681 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);\r
1682 TempPrdBaseAddr->ByteCount = (UINT16) ByteRemaining;\r
1683 TempPrdBaseAddr->EndOfTable = 0x8000;\r
490b5ea1 1684 break;\r
1685 }\r
a41b5272 1686\r
2525e221 1687 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);\r
1688 TempPrdBaseAddr->ByteCount = (UINT16) 0x0;\r
a41b5272 1689\r
490b5ea1 1690 ByteRemaining -= 0x10000;\r
1691 BufferMapAddress += 0x10000;\r
2525e221 1692 TempPrdBaseAddr++;\r
490b5ea1 1693 }\r
a41b5272 1694\r
490b5ea1 1695 //\r
1696 // Start to enable the DMA operation\r
1697 //\r
1698 DeviceHead = AtaCommandBlock->AtaDeviceHead;\r
a41b5272 1699\r
490b5ea1 1700 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | DeviceHead));\r
a41b5272 1701\r
490b5ea1 1702 //\r
1703 // Enable interrupt to support UDMA\r
1704 //\r
1705 DeviceControl = 0;\r
1706 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);\r
a41b5272 1707\r
490b5ea1 1708 //\r
1709 // Read BMIS register and clear ERROR and INTR bit\r
1710 //\r
1711 RegisterValue = IdeReadPortB(PciIo, IoPortForBmis);\r
1712 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);\r
8536cc4b 1713 IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);\r
a41b5272 1714\r
490b5ea1 1715 //\r
1716 // Set the base address to BMID register\r
1717 //\r
1718 IdeWritePortDW (PciIo, IoPortForBmid, (UINT32)PrdTableMapAddr);\r
a41b5272 1719\r
490b5ea1 1720 //\r
1721 // Set BMIC register to identify the operation direction\r
1722 //\r
1723 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);\r
1724 if (Read) {\r
1725 RegisterValue |= BMIC_NREAD;\r
1726 } else {\r
1727 RegisterValue &= ~((UINT8) BMIC_NREAD);\r
1728 }\r
1729 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
a41b5272 1730\r
1aff716a 1731 if (Task != NULL) {\r
1aff716a 1732 Task->Map = BufferMap;\r
1733 Task->TableMap = PrdTableMap;\r
1734 Task->MapBaseAddress = PrdBaseAddr;\r
1735 Task->PageCount = PageCount;\r
1736 Task->IsStart = TRUE;\r
1737 }\r
1738\r
490b5ea1 1739 //\r
1740 // Issue ATA command\r
1741 //\r
1742 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);\r
a41b5272 1743\r
490b5ea1 1744 if (EFI_ERROR (Status)) {\r
1745 Status = EFI_DEVICE_ERROR;\r
1746 goto Exit;\r
1747 }\r
a41b5272 1748\r
8536cc4b 1749 Status = CheckStatusRegister (PciIo, IdeRegisters);\r
1750 if (EFI_ERROR (Status)) {\r
1751 Status = EFI_DEVICE_ERROR;\r
1752 goto Exit;\r
1753 }\r
490b5ea1 1754 //\r
1755 // Set START bit of BMIC register\r
1756 //\r
1757 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);\r
1758 RegisterValue |= BMIC_START;\r
1759 IdeWritePortB(PciIo, IoPortForBmic, RegisterValue);\r
a41b5272 1760\r
a41b5272 1761 }\r
1762\r
a41b5272 1763 //\r
1764 // Check the INTERRUPT and ERROR bit of BMIS\r
a41b5272 1765 //\r
490b5ea1 1766 if (Task != NULL) {\r
8536cc4b 1767 Status = AtaUdmStatusCheck (PciIo, Task, IdeRegisters);\r
490b5ea1 1768 } else {\r
ab82122d 1769 Status = AtaUdmStatusWait (PciIo, IdeRegisters, Timeout);\r
a41b5272 1770 }\r
1771\r
1772 //\r
490b5ea1 1773 // For blocking mode, clear registers and free buffers.\r
1774 // For non blocking mode, when the related registers have been set or time\r
1775 // out, or a error has been happened, it needs to clear the register and free\r
1776 // buffer.\r
a41b5272 1777 //\r
490b5ea1 1778 if ((Task == NULL) || Status != EFI_NOT_READY) {\r
1779 //\r
1780 // Read BMIS register and clear ERROR and INTR bit\r
1781 //\r
1782 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
1783 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);\r
1784 IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);\r
a41b5272 1785\r
490b5ea1 1786 //\r
1787 // Read Status Register of IDE device to clear interrupt\r
1788 //\r
1789 RegisterValue = IdeReadPortB(PciIo, IdeRegisters->CmdOrStatus);\r
a41b5272 1790\r
490b5ea1 1791 //\r
1792 // Clear START bit of BMIC register\r
1793 //\r
1794 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);\r
1795 RegisterValue &= ~((UINT8) BMIC_START);\r
1796 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
a41b5272 1797\r
490b5ea1 1798 //\r
1799 // Disable interrupt of Select device\r
1800 //\r
1801 DeviceControl = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
1802 DeviceControl |= ATA_CTLREG_IEN_L;\r
1803 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);\r
1804 //\r
1805 // Stall for 10 milliseconds.\r
1806 //\r
1807 MicroSecondDelay (10000);\r
1808\r
1809 }\r
a41b5272 1810\r
1811Exit:\r
1812 //\r
1813 // Free all allocated resource\r
1814 //\r
490b5ea1 1815 if ((Task == NULL) || Status != EFI_NOT_READY) {\r
1816 if (Task != NULL) {\r
1817 PciIo->Unmap (PciIo, Task->TableMap);\r
1818 PciIo->FreeBuffer (PciIo, Task->PageCount, Task->MapBaseAddress);\r
1819 PciIo->Unmap (PciIo, Task->Map);\r
1820 } else {\r
1821 PciIo->Unmap (PciIo, PrdTableMap);\r
1822 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);\r
1823 PciIo->Unmap (PciIo, BufferMap);\r
1824 }\r
a41b5272 1825\r
490b5ea1 1826 //\r
1827 // Dump All Ide registers to ATA_STATUS_BLOCK\r
1828 //\r
1829 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);\r
1830 }\r
1aff716a 1831\r
a41b5272 1832 return Status;\r
1833}\r
1834\r
1835/**\r
1836 This function reads the pending data in the device.\r
1837\r
1838 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
1839 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
1840\r
1841 @retval EFI_SUCCESS Successfully read.\r
1842 @retval EFI_NOT_READY The BSY is set avoiding reading.\r
1843\r
1844**/\r
1845EFI_STATUS\r
1846EFIAPI\r
1847AtaPacketReadPendingData (\r
1848 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1849 IN EFI_IDE_REGISTERS *IdeRegisters\r
1850 )\r
1851{\r
1852 UINT8 AltRegister;\r
1853 UINT16 TempWordBuffer;\r
1854\r
1855 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
1856 if ((AltRegister & ATA_STSREG_BSY) == ATA_STSREG_BSY) {\r
1857 return EFI_NOT_READY;\r
1858 }\r
1859\r
1860 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {\r
1861 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
1862 while ((TempWordBuffer & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {\r
1863 IdeReadPortWMultiple (\r
1864 PciIo,\r
1aff716a 1865 IdeRegisters->Data,\r
1866 1,\r
a41b5272 1867 &TempWordBuffer\r
1868 );\r
1869 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
1870 }\r
1871 }\r
1872 return EFI_SUCCESS;\r
1873}\r
1874\r
1875/**\r
1aff716a 1876 This function is called by AtaPacketCommandExecute().\r
a41b5272 1877 It is used to transfer data between host and device. The data direction is specified\r
1878 by the fourth parameter.\r
1879\r
1880 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
1881 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
1882 @param Buffer Buffer contained data transferred between host and device.\r
1883 @param ByteCount Data size in byte unit of the buffer.\r
1884 @param Read Flag used to determine the data transfer direction.\r
1885 Read equals 1, means data transferred from device to host;\r
1886 Read equals 0, means data transferred from host to device.\r
8536cc4b 1887 @param Timeout Timeout value for wait DRQ ready before each data stream's transfer\r
1888 , uses 100ns as a unit.\r
a41b5272 1889\r
1890 @retval EFI_SUCCESS data is transferred successfully.\r
1891 @retval EFI_DEVICE_ERROR the device failed to transfer data.\r
1892**/\r
1893EFI_STATUS\r
1894EFIAPI\r
1895AtaPacketReadWrite (\r
1896 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
1897 IN EFI_IDE_REGISTERS *IdeRegisters,\r
1898 IN OUT VOID *Buffer,\r
1899 IN UINT64 ByteCount,\r
1900 IN BOOLEAN Read,\r
1901 IN UINT64 Timeout\r
1902 )\r
1903{\r
1904 UINT32 RequiredWordCount;\r
1905 UINT32 ActualWordCount;\r
1906 UINT32 WordCount;\r
1907 EFI_STATUS Status;\r
1908 UINT16 *PtrBuffer;\r
1909\r
1910 //\r
1911 // No data transfer is premitted.\r
1912 //\r
1913 if (ByteCount == 0) {\r
1914 return EFI_SUCCESS;\r
1915 }\r
1aff716a 1916\r
a41b5272 1917 PtrBuffer = Buffer;\r
1918 RequiredWordCount = (UINT32)RShiftU64(ByteCount, 1);\r
1919 //\r
1920 // ActuralWordCount means the word count of data really transferred.\r
1921 //\r
1922 ActualWordCount = 0;\r
1923\r
1924 while (ActualWordCount < RequiredWordCount) {\r
1925 //\r
1926 // before each data transfer stream, the host should poll DRQ bit ready,\r
1927 // to see whether indicates device is ready to transfer data.\r
1928 //\r
1929 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);\r
1930 if (EFI_ERROR (Status)) {\r
aca84419 1931 return CheckStatusRegister (PciIo, IdeRegisters);\r
a41b5272 1932 }\r
1933\r
1934 //\r
1935 // get current data transfer size from Cylinder Registers.\r
1936 //\r
1937 WordCount = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb) << 8;\r
1938 WordCount = WordCount | IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);\r
1939 WordCount = WordCount & 0xffff;\r
1940 WordCount /= 2;\r
1941\r
1942 WordCount = MIN (WordCount, (RequiredWordCount - ActualWordCount));\r
1943\r
1944 if (Read) {\r
1945 IdeReadPortWMultiple (\r
1946 PciIo,\r
1947 IdeRegisters->Data,\r
1948 WordCount,\r
1949 PtrBuffer\r
1950 );\r
1951 } else {\r
1952 IdeWritePortWMultiple (\r
1953 PciIo,\r
1954 IdeRegisters->Data,\r
1955 WordCount,\r
1956 PtrBuffer\r
1957 );\r
1958 }\r
1959\r
1960 //\r
1961 // read status register to check whether error happens.\r
1962 //\r
1963 Status = CheckStatusRegister (PciIo, IdeRegisters);\r
1964 if (EFI_ERROR (Status)) {\r
1965 return EFI_DEVICE_ERROR;\r
1966 }\r
1967\r
1968 PtrBuffer += WordCount;\r
1969 ActualWordCount += WordCount;\r
1970 }\r
1aff716a 1971\r
a41b5272 1972 if (Read) {\r
1973 //\r
1974 // In the case where the drive wants to send more data than we need to read,\r
1975 // the DRQ bit will be set and cause delays from DRQClear2().\r
1976 // We need to read data from the drive until it clears DRQ so we can move on.\r
1977 //\r
1978 AtaPacketReadPendingData (PciIo, IdeRegisters);\r
1979 }\r
1980\r
1981 //\r
1982 // read status register to check whether error happens.\r
1983 //\r
1984 Status = CheckStatusRegister (PciIo, IdeRegisters);\r
1985 if (EFI_ERROR (Status)) {\r
1986 return EFI_DEVICE_ERROR;\r
1987 }\r
1988\r
1989 //\r
1990 // After data transfer is completed, normally, DRQ bit should clear.\r
1991 //\r
8536cc4b 1992 Status = DRQClear (PciIo, IdeRegisters, Timeout);\r
a41b5272 1993 if (EFI_ERROR (Status)) {\r
1994 return EFI_DEVICE_ERROR;\r
1995 }\r
1aff716a 1996\r
a41b5272 1997 return Status;\r
1998}\r
1999\r
a41b5272 2000/**\r
1aff716a 2001 This function is used to send out ATAPI commands conforms to the Packet Command\r
a41b5272 2002 with PIO Data In Protocol.\r
2003\r
2004 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r
2005 @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to\r
2006 store the IDE i/o port registers' base addresses\r
2007 @param[in] Channel The channel number of device.\r
2008 @param[in] Device The device number of device.\r
2009 @param[in] Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.\r
2010\r
2011 @retval EFI_SUCCESS send out the ATAPI packet command successfully\r
2012 and device sends data successfully.\r
2013 @retval EFI_DEVICE_ERROR the device failed to send data.\r
2014\r
2015**/\r
2016EFI_STATUS\r
2017EFIAPI\r
2018AtaPacketCommandExecute (\r
2019 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
2020 IN EFI_IDE_REGISTERS *IdeRegisters,\r
2021 IN UINT8 Channel,\r
2022 IN UINT8 Device,\r
2023 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r
2024 )\r
2025{\r
a41b5272 2026 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
2027 EFI_STATUS Status;\r
2028 UINT8 Count;\r
2029 UINT8 PacketCommand[12];\r
2030\r
2031 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
2032\r
2033 //\r
2034 // Fill ATAPI Command Packet according to CDB.\r
2035 // For Atapi cmd, its length should be less than or equal to 12 bytes.\r
2036 //\r
2037 if (Packet->CdbLength > 12) {\r
2038 return EFI_INVALID_PARAMETER;\r
2039 }\r
2040\r
2041 ZeroMem (PacketCommand, 12);\r
2042 CopyMem (PacketCommand, Packet->Cdb, Packet->CdbLength);\r
2043\r
2044 //\r
2045 // No OVL; No DMA\r
2046 //\r
2047 AtaCommandBlock.AtaFeatures = 0x00;\r
2048 //\r
2049 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device\r
2050 // determine how many data should be transferred.\r
2051 //\r
2052 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);\r
2053 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);\r
aca84419 2054 AtaCommandBlock.AtaDeviceHead = (UINT8) (Device << 0x4);\r
a41b5272 2055 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;\r
2056\r
2057 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | (Device << 0x4)));\r
2058 //\r
2059 // Disable interrupt\r
2060 //\r
2061 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, ATA_DEFAULT_CTL);\r
2062\r
2063 //\r
2064 // Issue ATA PACKET command firstly\r
2065 //\r
2066 Status = AtaIssueCommand (PciIo, IdeRegisters, &AtaCommandBlock, Packet->Timeout);\r
2067 if (EFI_ERROR (Status)) {\r
2068 return Status;\r
2069 }\r
2070\r
2071 Status = DRQReady (PciIo, IdeRegisters, Packet->Timeout);\r
2072 if (EFI_ERROR (Status)) {\r
2073 return Status;\r
2074 }\r
2075\r
2076 //\r
2077 // Send out ATAPI command packet\r
2078 //\r
2079 for (Count = 0; Count < 6; Count++) {\r
1aff716a 2080 IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count));\r
a41b5272 2081 //\r
2082 // Stall for 10 microseconds.\r
2083 //\r
2084 MicroSecondDelay (10);\r
2085 }\r
2086\r
2087 //\r
2088 // Read/Write the data of ATAPI Command\r
2089 //\r
2090 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {\r
73a9e822
TF		 2091 Status = AtaPacketReadWrite (\r
2092 PciIo,\r
2093 IdeRegisters,\r
2094 Packet->InDataBuffer,\r
2095 Packet->InTransferLength,\r
2096 TRUE,\r
2097 Packet->Timeout\r
2098 );\r
a41b5272 2099 } else {\r
73a9e822
TF		 2100 Status = AtaPacketReadWrite (\r
2101 PciIo,\r
2102 IdeRegisters,\r
2103 Packet->OutDataBuffer,\r
2104 Packet->OutTransferLength,\r
2105 FALSE,\r
2106 Packet->Timeout\r
2107 );\r
a41b5272 2108 }\r
2109\r
73a9e822 2110 return Status;\r
a41b5272 2111}\r
2112\r
2113\r
2114/**\r
2115 Set the calculated Best transfer mode to a detected device.\r
2116\r
2117 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
2118 @param Channel The channel number of device.\r
2119 @param Device The device number of device.\r
2120 @param TransferMode A pointer to EFI_ATA_TRANSFER_MODE data structure.\r
2121 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
2122\r
2123 @retval EFI_SUCCESS Set transfer mode successfully.\r
2124 @retval EFI_DEVICE_ERROR Set transfer mode failed.\r
2125 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.\r
2126\r
2127**/\r
2128EFI_STATUS\r
2129EFIAPI\r
2130SetDeviceTransferMode (\r
2131 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
2132 IN UINT8 Channel,\r
2133 IN UINT8 Device,\r
2134 IN EFI_ATA_TRANSFER_MODE *TransferMode,\r
2135 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
2136 )\r
2137{\r
2138 EFI_STATUS Status;\r
2139 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
2140\r
2141 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
2142\r
2143 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;\r
2144 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);\r
2145 AtaCommandBlock.AtaFeatures = 0x03;\r
2146 AtaCommandBlock.AtaSectorCount = *((UINT8 *)TransferMode);\r
2147\r
2148 //\r
2149 // Send SET FEATURE command (sub command 0x03) to set pio mode.\r
2150 //\r
2151 Status = AtaNonDataCommandIn (\r
2152 Instance->PciIo,\r
2153 &Instance->IdeRegisters[Channel],\r
2154 &AtaCommandBlock,\r
2155 AtaStatusBlock,\r
490b5ea1 2156 ATA_ATAPI_TIMEOUT,\r
2157 NULL\r
a41b5272 2158 );\r
2159\r
2160 return Status;\r
2161}\r
2162\r
2163/**\r
2164 Set drive parameters for devices not support PACKETS command.\r
2165\r
2166 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
2167 @param Channel The channel number of device.\r
2168 @param Device The device number of device.\r
2169 @param DriveParameters A pointer to EFI_ATA_DRIVE_PARMS data structure.\r
2170 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
2171\r
2172 @retval EFI_SUCCESS Set drive parameter successfully.\r
2173 @retval EFI_DEVICE_ERROR Set drive parameter failed.\r
2174 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.\r
2175\r
2176**/\r
2177EFI_STATUS\r
2178EFIAPI\r
2179SetDriveParameters (\r
2180 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
2181 IN UINT8 Channel,\r
2182 IN UINT8 Device,\r
2183 IN EFI_ATA_DRIVE_PARMS *DriveParameters,\r
2184 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
a41b5272 2185 )\r
2186{\r
2187 EFI_STATUS Status;\r
2188 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
2189\r
2190 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1aff716a 2191\r
a41b5272 2192 AtaCommandBlock.AtaCommand = ATA_CMD_INIT_DRIVE_PARAM;\r
2193 AtaCommandBlock.AtaSectorCount = DriveParameters->Sector;\r
2194 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) + DriveParameters->Heads);\r
2195\r
2196 //\r
2197 // Send Init drive parameters\r
2198 //\r
2199 Status = AtaNonDataCommandIn (\r
2200 Instance->PciIo,\r
2201 &Instance->IdeRegisters[Channel],\r
2202 &AtaCommandBlock,\r
2203 AtaStatusBlock,\r
1aff716a 2204 ATA_ATAPI_TIMEOUT,\r
490b5ea1 2205 NULL\r
a41b5272 2206 );\r
2207\r
2208 //\r
2209 // Send Set Multiple parameters\r
2210 //\r
2211 AtaCommandBlock.AtaCommand = ATA_CMD_SET_MULTIPLE_MODE;\r
2212 AtaCommandBlock.AtaSectorCount = DriveParameters->MultipleSector;\r
2213 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);\r
2214\r
2215 Status = AtaNonDataCommandIn (\r
2216 Instance->PciIo,\r
2217 &Instance->IdeRegisters[Channel],\r
2218 &AtaCommandBlock,\r
2219 AtaStatusBlock,\r
1aff716a 2220 ATA_ATAPI_TIMEOUT,\r
490b5ea1 2221 NULL\r
a41b5272 2222 );\r
2223\r
2224 return Status;\r
2225}\r
2226\r
12873d57 2227/**\r
2228 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.\r
2229\r
2230 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
2231 @param Channel The channel number of device.\r
2232 @param Device The device number of device.\r
2233 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
2234\r
2235 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.\r
2236 @retval Others Fail to get return status data.\r
2237\r
2238**/\r
2239EFI_STATUS\r
2240EFIAPI\r
2241IdeAtaSmartReturnStatusCheck (\r
2242 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
2243 IN UINT8 Channel,\r
2244 IN UINT8 Device,\r
2245 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
2246 )\r
2247{\r
2248 EFI_STATUS Status;\r
2249 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
2250 UINT8 LBAMid;\r
2251 UINT8 LBAHigh;\r
2252\r
2253 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
2254\r
2255 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;\r
2256 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;\r
2257 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
2258 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
2259 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);\r
2260\r
2261 //\r
2262 // Send S.M.A.R.T Read Return Status command to device\r
2263 //\r
2264 Status = AtaNonDataCommandIn (\r
2265 Instance->PciIo,\r
2266 &Instance->IdeRegisters[Channel],\r
2267 &AtaCommandBlock,\r
2268 AtaStatusBlock,\r
490b5ea1 2269 ATA_ATAPI_TIMEOUT,\r
2270 NULL\r
12873d57 2271 );\r
2272\r
2273 if (EFI_ERROR (Status)) {\r
cffd2171
EL		 2274 REPORT_STATUS_CODE (\r
2275 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
2276 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)\r
2277 );\r
12873d57 2278 return EFI_DEVICE_ERROR;\r
2279 }\r
2280\r
cffd2171
EL		 2281 REPORT_STATUS_CODE (\r
2282 EFI_PROGRESS_CODE,\r
2283 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)\r
2284 );\r
2285\r
12873d57 2286 LBAMid = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderLsb);\r
2287 LBAHigh = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderMsb);\r
2288\r
2289 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {\r
2290 //\r
2291 // The threshold exceeded condition is not detected by the device\r
2292 //\r
2293 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));\r
cffd2171
EL		 2294 REPORT_STATUS_CODE (\r
2295 EFI_PROGRESS_CODE,\r
2296 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)\r
2297 );\r
12873d57 2298 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {\r
2299 //\r
2300 // The threshold exceeded condition is detected by the device\r
2301 //\r
2302 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));\r
cffd2171
EL		 2303 REPORT_STATUS_CODE (\r
2304 EFI_PROGRESS_CODE,\r
2305 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)\r
2306 );\r
12873d57 2307 }\r
2308\r
2309 return EFI_SUCCESS;\r
2310}\r
2311\r
2312/**\r
2313 Enable SMART command of the disk if supported.\r
2314\r
2315 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
2316 @param Channel The channel number of device.\r
2317 @param Device The device number of device.\r
2318 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.\r
2319 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
2320\r
2321**/\r
2322VOID\r
2323EFIAPI\r
2324IdeAtaSmartSupport (\r
2325 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
2326 IN UINT8 Channel,\r
2327 IN UINT8 Device,\r
2328 IN EFI_IDENTIFY_DATA *IdentifyData,\r
2329 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
2330 )\r
2331{\r
2332 EFI_STATUS Status;\r
2333 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
2334\r
2335 //\r
2336 // Detect if the device supports S.M.A.R.T.\r
2337 //\r
2338 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {\r
2339 //\r
2340 // S.M.A.R.T is not supported by the device\r
2341 //\r
1aff716a 2342 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",\r
12873d57 2343 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));\r
cffd2171
EL		 2344 REPORT_STATUS_CODE (\r
2345 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
2346 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)\r
2347 );\r
12873d57 2348 } else {\r
2349 //\r
2350 // Check if the feature is enabled. If not, then enable S.M.A.R.T.\r
2351 //\r
2352 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {\r
2353\r
cffd2171
EL		 2354 REPORT_STATUS_CODE (\r
2355 EFI_PROGRESS_CODE,\r
2356 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)\r
2357 );\r
2358\r
12873d57 2359 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
2360\r
2361 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;\r
2362 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;\r
2363 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
2364 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
2365 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);\r
2366\r
2367 //\r
2368 // Send S.M.A.R.T Enable command to device\r
2369 //\r
2370 Status = AtaNonDataCommandIn (\r
2371 Instance->PciIo,\r
2372 &Instance->IdeRegisters[Channel],\r
2373 &AtaCommandBlock,\r
2374 AtaStatusBlock,\r
490b5ea1 2375 ATA_ATAPI_TIMEOUT,\r
2376 NULL\r
12873d57 2377 );\r
2378\r
2379 if (!EFI_ERROR (Status)) {\r
2380 //\r
2381 // Send S.M.A.R.T AutoSave command to device\r
2382 //\r
2383 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
2384\r
2385 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;\r
2386 AtaCommandBlock.AtaFeatures = 0xD2;\r
2387 AtaCommandBlock.AtaSectorCount = 0xF1;\r
2388 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;\r
2389 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;\r
2390 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);\r
2391\r
2392 Status = AtaNonDataCommandIn (\r
2393 Instance->PciIo,\r
2394 &Instance->IdeRegisters[Channel],\r
2395 &AtaCommandBlock,\r
2396 AtaStatusBlock,\r
490b5ea1 2397 ATA_ATAPI_TIMEOUT,\r
2398 NULL\r
12873d57 2399 );\r
2400 if (!EFI_ERROR (Status)) {\r
2401 Status = IdeAtaSmartReturnStatusCheck (\r
2402 Instance,\r
2403 Channel,\r
2404 Device,\r
2405 AtaStatusBlock\r
2406 );\r
2407 }\r
2408 }\r
2409 }\r
2410\r
1aff716a 2411 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",\r
12873d57 2412 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));\r
2413\r
2414 }\r
2415\r
2416 return ;\r
2417}\r
2418\r
490b5ea1 2419\r
a41b5272 2420/**\r
2421 Sends out an ATA Identify Command to the specified device.\r
2422\r
2423 This function is called by DiscoverIdeDevice() during its device\r
2424 identification. It sends out the ATA Identify Command to the\r
2425 specified device. Only ATA device responses to this command. If\r
2426 the command succeeds, it returns the Identify data structure which\r
2427 contains information about the device. This function extracts the\r
2428 information it needs to fill the IDE_BLK_IO_DEV data structure,\r
2429 including device type, media block size, media capacity, and etc.\r
2430\r
2431 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
2432 @param Channel The channel number of device.\r
2433 @param Device The device number of device.\r
2434 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.\r
2435 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
2436\r
2437 @retval EFI_SUCCESS Identify ATA device successfully.\r
2438 @retval EFI_DEVICE_ERROR ATA Identify Device Command failed or device is not ATA device.\r
2439 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.\r
490b5ea1 2440\r
a41b5272 2441**/\r
2442EFI_STATUS\r
2443EFIAPI\r
2444AtaIdentify (\r
2445 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
2446 IN UINT8 Channel,\r
2447 IN UINT8 Device,\r
2448 IN OUT EFI_IDENTIFY_DATA *Buffer,\r
2449 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
2450 )\r
2451{\r
2452 EFI_STATUS Status;\r
490b5ea1 2453 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
a41b5272 2454\r
2455 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
490b5ea1 2456\r
a41b5272 2457 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;\r
2458 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);\r
2459\r
2460 Status = AtaPioDataInOut (\r
2461 Instance->PciIo,\r
2462 &Instance->IdeRegisters[Channel],\r
2463 Buffer,\r
2464 sizeof (EFI_IDENTIFY_DATA),\r
2465 TRUE,\r
2466 &AtaCommandBlock,\r
2467 AtaStatusBlock,\r
490b5ea1 2468 ATA_ATAPI_TIMEOUT,\r
2469 NULL\r
a41b5272 2470 );\r
2471\r
2472 return Status;\r
2473}\r
2474\r
2475/**\r
2476 This function is called by DiscoverIdeDevice() during its device\r
2477 identification.\r
2478 Its main purpose is to get enough information for the device media\r
2479 to fill in the Media data structure of the Block I/O Protocol interface.\r
2480\r
2481 There are 5 steps to reach such objective:\r
1aff716a 2482 1. Sends out the ATAPI Identify Command to the specified device.\r
a41b5272 2483 Only ATAPI device responses to this command. If the command succeeds,\r
1aff716a 2484 it returns the Identify data structure which filled with information\r
2485 about the device. Since the ATAPI device contains removable media,\r
a41b5272 2486 the only meaningful information is the device module name.\r
2487 2. Sends out ATAPI Inquiry Packet Command to the specified device.\r
2488 This command will return inquiry data of the device, which contains\r
2489 the device type information.\r
2490 3. Allocate sense data space for future use. We don't detect the media\r
1aff716a 2491 presence here to improvement boot performance, especially when CD\r
a41b5272 2492 media is present. The media detection will be performed just before\r
2493 each BLK_IO read/write\r
1aff716a 2494\r
a41b5272 2495 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
2496 @param Channel The channel number of device.\r
2497 @param Device The device number of device.\r
2498 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.\r
2499 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
2500\r
2501 @retval EFI_SUCCESS Identify ATAPI device successfully.\r
2502 @retval EFI_DEVICE_ERROR ATA Identify Packet Device Command failed or device type\r
2503 is not supported by this IDE driver.\r
2504 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.\r
2505\r
2506**/\r
2507EFI_STATUS\r
2508EFIAPI\r
2509AtaIdentifyPacket (\r
2510 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
2511 IN UINT8 Channel,\r
2512 IN UINT8 Device,\r
2513 IN OUT EFI_IDENTIFY_DATA *Buffer,\r
2514 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
2515 )\r
2516{\r
2517 EFI_STATUS Status;\r
2518 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;\r
2519\r
2520 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));\r
1aff716a 2521\r
a41b5272 2522 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;\r
2523 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);\r
2524\r
2525 //\r
2526 // Send ATAPI Identify Command to get IDENTIFY data.\r
2527 //\r
2528 Status = AtaPioDataInOut (\r
2529 Instance->PciIo,\r
2530 &Instance->IdeRegisters[Channel],\r
2531 (VOID *) Buffer,\r
2532 sizeof (EFI_IDENTIFY_DATA),\r
2533 TRUE,\r
2534 &AtaCommandBlock,\r
2535 AtaStatusBlock,\r
490b5ea1 2536 ATA_ATAPI_TIMEOUT,\r
2537 NULL\r
a41b5272 2538 );\r
2539\r
2540 return Status;\r
2541}\r
2542\r
2543\r
2544/**\r
2545 This function is used for detect whether the IDE device exists in the\r
2546 specified Channel as the specified Device Number.\r
2547\r
2548 There is two IDE channels: one is Primary Channel, the other is\r
2549 Secondary Channel.(Channel is the logical name for the physical "Cable".)\r
2550 Different channel has different register group.\r
2551\r
2552 On each IDE channel, at most two IDE devices attach,\r
2553 one is called Device 0 (Master device), the other is called Device 1\r
2554 (Slave device). The devices on the same channel co-use the same register\r
2555 group, so before sending out a command for a specified device via command\r
2556 register, it is a must to select the current device to accept the command\r
2557 by set the device number in the Head/Device Register.\r
2558\r
2559 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
2560 @param IdeChannel The channel number of device.\r
2561\r
2562 @retval EFI_SUCCESS successfully detects device.\r
2563 @retval other any failure during detection process will return this value.\r
2564\r
2565**/\r
2566EFI_STATUS\r
2567EFIAPI\r
2568DetectAndConfigIdeDevice (\r
2569 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,\r
2570 IN UINT8 IdeChannel\r
2571 )\r
2572{\r
2573 EFI_STATUS Status;\r
2574 UINT8 SectorCountReg;\r
2575 UINT8 LBALowReg;\r
2576 UINT8 LBAMidReg;\r
2577 UINT8 LBAHighReg;\r
2578 EFI_ATA_DEVICE_TYPE DeviceType;\r
aca84419 2579 UINT8 IdeDevice;\r
a41b5272 2580 EFI_IDE_REGISTERS *IdeRegisters;\r
2581 EFI_IDENTIFY_DATA Buffer;\r
2582\r
2583 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;\r
2584 EFI_PCI_IO_PROTOCOL *PciIo;\r
2585\r
2586 EFI_ATA_COLLECTIVE_MODE *SupportedModes;\r
2587 EFI_ATA_TRANSFER_MODE TransferMode;\r
2588 EFI_ATA_DRIVE_PARMS DriveParameters;\r
2589\r
2590 IdeRegisters = &Instance->IdeRegisters[IdeChannel];\r
2591 IdeInit = Instance->IdeControllerInit;\r
2592 PciIo = Instance->PciIo;\r
2593\r
490b5ea1 2594 for (IdeDevice = 0; IdeDevice < EfiIdeMaxDevice; IdeDevice++) {\r
a41b5272 2595 //\r
2596 // Send ATA Device Execut Diagnostic command.\r
2597 // This command should work no matter DRDY is ready or not\r
2598 //\r
2599 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, ATA_CMD_EXEC_DRIVE_DIAG);\r
1aff716a 2600\r
a41b5272 2601 Status = WaitForBSYClear (PciIo, IdeRegisters, 350000000);\r
2602 if (EFI_ERROR (Status)) {\r
2603 DEBUG((EFI_D_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));\r
2604 continue;\r
2605 }\r
2606\r
2607 //\r
2608 // Select Master or Slave device to get the return signature for ATA DEVICE DIAGNOSTIC cmd.\r
2609 //\r
2610 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)((IdeDevice << 4) | 0xe0));\r
2611 //\r
2612 // Stall for 1 milliseconds.\r
2613 //\r
2614 MicroSecondDelay (1000);\r
2615\r
2616 SectorCountReg = IdeReadPortB (PciIo, IdeRegisters->SectorCount);\r
2617 LBALowReg = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);\r
2618 LBAMidReg = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);\r
2619 LBAHighReg = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);\r
2620\r
2621 //\r
2622 // Refer to ATA/ATAPI 4 Spec, section 9.1\r
2623 //\r
2624 if ((SectorCountReg == 0x1) && (LBALowReg == 0x1) && (LBAMidReg == 0x0) && (LBAHighReg == 0x0)) {\r
2625 DeviceType = EfiIdeHarddisk;\r
2626 } else if ((LBAMidReg == 0x14) && (LBAHighReg == 0xeb)) {\r
2627 DeviceType = EfiIdeCdrom;\r
2628 } else {\r
2629 continue;\r
2630 }\r
2631\r
2632 //\r
2633 // Send IDENTIFY cmd to the device to test if it is really attached.\r
2634 //\r
2635 if (DeviceType == EfiIdeHarddisk) {\r
2636 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);\r
2637 //\r
2638 // if identifying ata device is failure, then try to send identify packet cmd.\r
2639 //\r
2640 if (EFI_ERROR (Status)) {\r
3d0a2385 2641 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));\r
2642\r
a41b5272 2643 DeviceType = EfiIdeCdrom;\r
2644 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);\r
2645 }\r
2646 } else {\r
2647 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);\r
2648 //\r
2649 // if identifying atapi device is failure, then try to send identify cmd.\r
2650 //\r
2651 if (EFI_ERROR (Status)) {\r
2652 DeviceType = EfiIdeHarddisk;\r
2653 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);\r
490b5ea1 2654 }\r
a41b5272 2655 }\r
2656\r
2657 if (EFI_ERROR (Status)) {\r
2658 //\r
2659 // No device is found at this port\r
2660 //\r
2661 continue;\r
490b5ea1 2662 }\r
2663\r
1aff716a 2664 DEBUG ((EFI_D_INFO, "[%a] channel [%a] [%a] device\n",\r
a41b5272 2665 (IdeChannel == 1) ? "secondary" : "primary ", (IdeDevice == 1) ? "slave " : "master",\r
2666 DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"));\r
12873d57 2667 //\r
2668 // If the device is a hard disk, then try to enable S.M.A.R.T feature\r
2669 //\r
fc80ee69 2670 if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {\r
12873d57 2671 IdeAtaSmartSupport (\r
2672 Instance,\r
2673 IdeChannel,\r
2674 IdeDevice,\r
2675 &Buffer,\r
2676 NULL\r
2677 );\r
2678 }\r
2679\r
a41b5272 2680 //\r
2681 // Submit identify data to IDE controller init driver\r
2682 //\r
2683 IdeInit->SubmitData (IdeInit, IdeChannel, IdeDevice, &Buffer);\r
2684\r
2685 //\r
2686 // Now start to config ide device parameter and transfer mode.\r
2687 //\r
2688 Status = IdeInit->CalculateMode (\r
2689 IdeInit,\r
2690 IdeChannel,\r
2691 IdeDevice,\r
2692 &SupportedModes\r
2693 );\r
2694 if (EFI_ERROR (Status)) {\r
2695 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));\r
2696 continue;\r
2697 }\r
2698\r
2699 //\r
2700 // Set best supported PIO mode on this IDE device\r
2701 //\r
2702 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {\r
2703 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;\r
2704 } else {\r
2705 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;\r
2706 }\r
2707\r
2708 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);\r
2709\r
2710 if (SupportedModes->ExtModeCount == 0){\r
2711 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
2712\r
2713 if (EFI_ERROR (Status)) {\r
2714 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));\r
2715 continue;\r
2716 }\r
2717 }\r
490b5ea1 2718\r
a41b5272 2719 //\r
2720 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't\r
2721 // be set together. Only one DMA mode can be set to a device. If setting\r
2722 // DMA mode operation fails, we can continue moving on because we only use\r
2723 // PIO mode at boot time. DMA modes are used by certain kind of OS booting\r
2724 //\r
2725 if (SupportedModes->UdmaMode.Valid) {\r
2726 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;\r
2727 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);\r
2728 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
490b5ea1 2729\r
a41b5272 2730 if (EFI_ERROR (Status)) {\r
2731 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));\r
2732 continue;\r
2733 }\r
2734 } else if (SupportedModes->MultiWordDmaMode.Valid) {\r
2735 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;\r
2736 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;\r
2737 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);\r
490b5ea1 2738\r
a41b5272 2739 if (EFI_ERROR (Status)) {\r
2740 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));\r
2741 continue;\r
2742 }\r
2743 }\r
490b5ea1 2744\r
a41b5272 2745 //\r
2746 // Set Parameters for the device:\r
2747 // 1) Init\r
2748 // 2) Establish the block count for READ/WRITE MULTIPLE (EXT) command\r
2749 //\r
2750 if (DeviceType == EfiIdeHarddisk) {\r
2751 //\r
2752 // Init driver parameters\r
2753 //\r
2754 DriveParameters.Sector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->sectors_per_track;\r
aca84419 2755 DriveParameters.Heads = (UINT8) (((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->heads - 1);\r
a41b5272 2756 DriveParameters.MultipleSector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->multi_sector_cmd_max_sct_cnt;\r
490b5ea1 2757\r
a41b5272 2758 Status = SetDriveParameters (Instance, IdeChannel, IdeDevice, &DriveParameters, NULL);\r
2759 }\r
490b5ea1 2760\r
a41b5272 2761 //\r
2762 // Set IDE controller Timing Blocks in the PCI Configuration Space\r
2763 //\r
2764 IdeInit->SetTiming (IdeInit, IdeChannel, IdeDevice, SupportedModes);\r
2765\r
2766 //\r
2767 // IDE controller and IDE device timing is configured successfully.\r
2768 // Now insert the device into device list.\r
2769 //\r
2770 Status = CreateNewDeviceInfo (Instance, IdeChannel, IdeDevice, DeviceType, &Buffer);\r
2771 if (EFI_ERROR (Status)) {\r
2772 continue;\r
2773 }\r
3d0a2385 2774\r
2775 if (DeviceType == EfiIdeHarddisk) {\r
2776 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));\r
2777 }\r
a41b5272 2778 }\r
2779 return EFI_SUCCESS;\r
2780}\r
2781\r
2782\r
2783/**\r
2784 Initialize ATA host controller at IDE mode.\r
1aff716a 2785\r
2786 The function is designed to initialize ATA host controller.\r
2787\r
a41b5272 2788 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.\r
2789\r
2790**/\r
2791EFI_STATUS\r
2792EFIAPI\r
2793IdeModeInitialization (\r
2794 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance\r
2795 )\r
2796{\r
a41b5272 2797 EFI_STATUS Status;\r
2798 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;\r
2799 EFI_PCI_IO_PROTOCOL *PciIo;\r
2800 UINT8 Channel;\r
2801 UINT8 IdeChannel;\r
2802 BOOLEAN ChannelEnabled;\r
2803 UINT8 MaxDevices;\r
2804\r
2805 IdeInit = Instance->IdeControllerInit;\r
2806 PciIo = Instance->PciIo;\r
a41b5272 2807 Channel = IdeInit->ChannelCount;\r
2808\r
2809 //\r
2810 // Obtain IDE IO port registers' base addresses\r
2811 //\r
2812 Status = GetIdeRegisterIoAddr (PciIo, Instance->IdeRegisters);\r
2813 if (EFI_ERROR (Status)) {\r
2814 goto ErrorExit;\r
2815 }\r
2816\r
2817 for (IdeChannel = 0; IdeChannel < Channel; IdeChannel++) {\r
2818 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, IdeChannel);\r
2819\r
2820 //\r
2821 // now obtain channel information fron IdeControllerInit protocol.\r
2822 //\r
2823 Status = IdeInit->GetChannelInfo (\r
2824 IdeInit,\r
2825 IdeChannel,\r
2826 &ChannelEnabled,\r
2827 &MaxDevices\r
2828 );\r
2829 if (EFI_ERROR (Status)) {\r
2830 DEBUG ((EFI_D_ERROR, "[GetChannel, Status=%x]", Status));\r
2831 continue;\r
2832 }\r
2833\r
2834 if (!ChannelEnabled) {\r
2835 continue;\r
2836 }\r
2837\r
2838 ASSERT (MaxDevices <= 2);\r
2839 //\r
2840 // Now inform the IDE Controller Init Module.\r
2841 //\r
2842 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelReset, IdeChannel);\r
2843\r
2844 //\r
2845 // No reset channel function implemented.\r
2846 //\r
2847 IdeInit->NotifyPhase (IdeInit, EfiIdeAfterChannelReset, IdeChannel);\r
2848\r
2849 //\r
2850 // Now inform the IDE Controller Init Module.\r
2851 //\r
2852 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, IdeChannel);\r
2853\r
2854 //\r
2855 // Detect all attached ATA devices and set the transfer mode for each device.\r
2856 //\r
2857 DetectAndConfigIdeDevice (Instance, IdeChannel);\r
2858 }\r
2859\r
2860 //\r
2861 // All configurations done! Notify IdeController to do post initialization\r
2862 // work such as saving IDE controller PCI settings for S3 resume\r
2863 //\r
2864 IdeInit->NotifyPhase (IdeInit, EfiIdeBusPhaseMaximum, 0);\r
2865\r
2866ErrorExit:\r
2867 return Status;\r
2868}\r
2869\r
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