Remove some useless EDK_RELEASE_VERSION, EFI_SPECIFICATION_VERSION ,and review VALID_...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.c

/** @file\r
\r
  The EHCI register operation routines.\r
\r
Copyright (c) 2007, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#include "Ehci.h"\r
\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       Capability register address.\r
\r
  @return The register content read.\r
  @retval If err, return 0xffff.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  )\r
{\r
  UINT32                  Data;\r
  EFI_STATUS              Status;\r
\r
  Status = Ehc->PciIo->Mem.Read (\r
                             Ehc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             EHC_BAR_INDEX,\r
                             (UINT64) Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EhcReadCapRegister: Pci Io read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The operation register offset.\r
\r
  @return The register content read.\r
  @retval If err, return 0xffff.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  )\r
{\r
  UINT32                  Data;\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Ehc->CapLen != 0);\r
\r
  Status = Ehc->PciIo->Mem.Read (\r
                             Ehc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             EHC_BAR_INDEX,\r
                             (UINT64) (Ehc->CapLen + Offset),\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       EHCI operation register offset.\r
  @param  Data         The data to write.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Ehc->CapLen != 0);\r
\r
  Status = Ehc->PciIo->Mem.Write (\r
                             Ehc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             EHC_BAR_INDEX,\r
                             (UINT64) (Ehc->CapLen + Offset),\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcSetOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  )\r
{\r
  UINT32                  Data;\r
\r
  Data  = EhcReadOpReg (Ehc, Offset);\r
  Data |= Bit;\r
  EhcWriteOpReg (Ehc, Offset, Data);\r
}\r
\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcClearOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  )\r
{\r
  UINT32                  Data;\r
\r
  Data  = EhcReadOpReg (Ehc, Offset);\r
  Data &= ~Bit;\r
  EhcWriteOpReg (Ehc, Offset, Data);\r
}\r
\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to become set (or clear).\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operation register.\r
  @param  Bit          The bit of the register to wait for.\r
  @param  WaitToSet    Wait the bit to set or clear.\r
  @param  Timeout      The time to wait before abort (in millisecond).\r
\r
  @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT  The time out occurred.\r
\r
**/\r
EFI_STATUS\r
EhcWaitOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit,\r
  IN BOOLEAN              WaitToSet,\r
  IN UINT32               Timeout\r
  )\r
{\r
  UINT32                  Index;\r
\r
  for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {\r
    if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {\r
      return EFI_SUCCESS;\r
    }\r
\r
    gBS->Stall (EHC_SYNC_POLL_INTERVAL);\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  UINT32                    ExtendCap;\r
  EFI_PCI_IO_PROTOCOL       *PciIo;\r
  UINT32                    Value;\r
  UINT32                    TimeOut;\r
\r
  DEBUG ((EFI_D_INFO, "EhcClearLegacySupport: called to clear legacy support\n"));\r
\r
  PciIo     = Ehc->PciIo;\r
  ExtendCap = (Ehc->HcCapParams >> 8) & 0xFF;\r
\r
  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);\r
  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value);\r
\r
  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);\r
  Value |= (0x1 << 24);\r
  PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);\r
\r
  TimeOut = 40;\r
  while (TimeOut-- != 0) {\r
    gBS->Stall (500);\r
\r
    PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);\r
\r
    if ((Value & 0x01010000) == 0x01000000) {\r
      break;\r
    }\r
  }\r
\r
  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);\r
  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value);\r
}\r
\r
\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
  UINT32                  Data;\r
\r
  EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);\r
\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_IAA, TRUE, Timeout);\r
\r
  //\r
  // ACK the IAA bit in USBSTS register. Make sure other\r
  // interrupt bits are not ACKed. These bits are WC (Write Clean).\r
  //\r
  Data  = EhcReadOpReg (Ehc, EHC_USBSTS_OFFSET);\r
  Data &= ~USBSTS_INTACK_MASK;\r
  Data |= USBSTS_IAA;\r
\r
  EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, Data);\r
\r
  return Status;\r
}\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits\r
  are Write-Clean.\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV         *Ehc\r
  )\r
{\r
  EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);\r
}\r
\r
\r
/**\r
  Enable the periodic schedule then wait EHC to\r
  actually enable it.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The periodical schedule is enabled.\r
  @retval EFI_TIMEOUT  Time out happened while enabling periodic schedule.\r
\r
**/\r
EFI_STATUS\r
EhcEnablePeriodSchd (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);\r
\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_PERIOD_ENABLED, TRUE, Timeout);\r
  return Status;\r
}\r
\r
\r
/**\r
  Disable periodic schedule.\r
\r
  @param  Ehc               The EHCI device.\r
  @param  Timeout           Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS       Periodic schedule is disabled.\r
  @retval EFI_DEVICE_ERROR  Fail to disable periodic schedule.\r
\r
**/\r
EFI_STATUS\r
EhcDisablePeriodSchd (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);\r
\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_PERIOD_ENABLED, FALSE, Timeout);\r
  return Status;\r
}\r
\r
\r
\r
/**\r
  Enable asynchrounous schedule.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @retval EFI_SUCCESS  The EHCI asynchronous schedule is enabled.\r
  @return Others       Failed to enable the asynchronous scheudle.\r
\r
**/\r
EFI_STATUS\r
EhcEnableAsyncSchd (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);\r
\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_ASYNC_ENABLED, TRUE, Timeout);\r
  return Status;\r
}\r
\r
\r
\r
/**\r
  Disable asynchrounous schedule.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The asynchronous schedule is disabled.\r
  @return Others       Failed to disable the asynchronous schedule.\r
\r
**/\r
EFI_STATUS\r
EhcDisableAsyncSchd (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);\r
\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_ASYNC_ENABLED, FALSE, Timeout);\r
  return Status;\r
}\r
\r
\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @retval TRUE         The controller is halted.\r
  @retval FALSE        It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);\r
}\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return TRUE         System error happened.\r
  @return FALSE        No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);\r
}\r
\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  //\r
  // Host can only be reset when it is halt. If not so, halt it\r
  //\r
  if (!EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT)) {\r
    Status = EhcHaltHC (Ehc, Timeout);\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RESET);\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RESET, FALSE, Timeout);\r
  return Status;\r
}\r
\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @retval EFI_SUCCESS  The EHCI is halt.\r
  @retval EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV         *Ehc,\r
  IN UINT32              Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);\r
  return Status;\r
}\r
\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @retval EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);\r
  return Status;\r
}\r
\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  ASSERT (EhcIsHalt (Ehc));\r
\r
  //\r
  // Allocate the periodic frame and associated memeory\r
  // management facilities if not already done.\r
  //\r
  if (Ehc->PeriodFrame != NULL) {\r
    EhcFreeSched (Ehc);\r
  }\r
\r
  Status = EhcInitSched (Ehc);\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // 1. Program the CTRLDSSEGMENT register with the high 32 bit addr\r
  //\r
  EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);\r
\r
  //\r
  // 2. Clear USBINTR to disable all the interrupt. UEFI works by polling\r
  //\r
  EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
\r
  //\r
  // 3. Program periodic frame list, already done in EhcInitSched\r
  // 4. Start the Host Controller\r
  //\r
  EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
\r
  //\r
  // 5. Set all ports routing to EHC\r
  //\r
  EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
\r
  //\r
  // Wait roothub port power stable\r
  //\r
  gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);\r
\r
  Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EhcInitHC: failed to enable period schedule\n"));\r
    return Status;\r
  }\r
\r
  Status = EhcEnableAsyncSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EhcInitHC: failed to enable async schedule\n"));\r
    return Status;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r