[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h

/** @file\r
\r
  This file contains the definination for host controller register operation routines.\r
\r
Copyright (c) 2007, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
\r
typedef enum {\r
  //\r
  // Capability register offset\r
  //\r
  EHC_CAPLENGTH_OFFSET    = 0,    // Capability register length offset\r
  EHC_HCSPARAMS_OFFSET    = 0x04, // Structural Parameters 04-07h\r
  EHC_HCCPARAMS_OFFSET    = 0x08, // Capability parameters offset\r
\r
  //\r
  // Capability register bit definition\r
  //\r
  HCSP_NPORTS             = 0x0F, // Number of root hub port\r
  HCCP_64BIT              = 0x01, // 64-bit addressing capability\r
\r
  //\r
  // Operational register offset\r
  //\r
  EHC_USBCMD_OFFSET       = 0x0,  // USB command register offset\r
  EHC_USBSTS_OFFSET       = 0x04, // Statue register offset\r
  EHC_USBINTR_OFFSET      = 0x08, // USB interrutp offset\r
  EHC_FRINDEX_OFFSET      = 0x0C, // Frame index offset\r
  EHC_CTRLDSSEG_OFFSET    = 0x10, // Control data structure segment offset\r
  EHC_FRAME_BASE_OFFSET   = 0x14, // Frame list base address offset\r
  EHC_ASYNC_HEAD_OFFSET   = 0x18, // Next asynchronous list address offset\r
  EHC_CONFIG_FLAG_OFFSET  = 0x40, // Configure flag register offset\r
  EHC_PORT_STAT_OFFSET    = 0x44, // Port status/control offset\r
\r
  EHC_FRAME_LEN           = 1024,\r
\r
  //\r
  // Register bit definition\r
  //\r
  CONFIGFLAG_ROUTE_EHC    = 0x01, // Route port to EHC\r
\r
  USBCMD_RUN              = 0x01,   // Run/stop\r
  USBCMD_RESET            = 0x02,   // Start the host controller reset\r
  USBCMD_ENABLE_PERIOD    = 0x10,   // Enable periodic schedule\r
  USBCMD_ENABLE_ASYNC     = 0x20,   // Enable asynchronous schedule\r
  USBCMD_IAAD             = 0x40,   // Interrupt on async advance doorbell\r
\r
  USBSTS_IAA              = 0x20,   // Interrupt on async advance\r
  USBSTS_PERIOD_ENABLED   = 0x4000, // Periodic schedule status\r
  USBSTS_ASYNC_ENABLED    = 0x8000, // Asynchronous schedule status\r
  USBSTS_HALT             = 0x1000, // Host controller halted\r
  USBSTS_SYS_ERROR        = 0x10,   // Host system error\r
  USBSTS_INTACK_MASK      = 0x003F, // Mask for the interrupt ACK, the WC\r
                                    // (write clean) bits in USBSTS register\r
\r
  PORTSC_CONN             = 0x01,   // Current Connect Status\r
  PORTSC_CONN_CHANGE      = 0x02,   // Connect Status Change\r
  PORTSC_ENABLED          = 0x04,   // Port Enable / Disable\r
  PORTSC_ENABLE_CHANGE    = 0x08,   // Port Enable / Disable Change\r
  PORTSC_OVERCUR          = 0x10,   // Over current Active\r
  PORTSC_OVERCUR_CHANGE   = 0x20,   // Over current Change\r
  PORSTSC_RESUME          = 0x40,   // Force Port Resume\r
  PORTSC_SUSPEND          = 0x80,   // Port Suspend State\r
  PORTSC_RESET            = 0x100,  // Port Reset\r
  PORTSC_LINESTATE_K      = 0x400,  // Line Status K-state\r
  PORTSC_LINESTATE_J      = 0x800,  // Line Status J-state\r
  PORTSC_POWER            = 0x1000, // Port Power\r
  PORTSC_OWNER            = 0x2000, // Port Owner\r
  PORTSC_CHANGE_MASK      = 0x2A,   // Mask of the port change bits,\r
                                    // they are WC (write clean)\r
  //\r
  // PCI Configuration Registers\r
  //\r
  EHC_PCI_CLASSC          = 0x09,\r
  EHC_PCI_CLASSC_PI       = 0x20,\r
  EHC_BAR_INDEX           = 0 /* how many bytes away from USB_BASE to 0x10 */\r
}EHCI_REGISTER_OFFSET;\r
\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32)   \\r
        ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT16                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Ehci Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   PI;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc     The EHCI device.\r
  @param  Offset  Capability register address.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   The operation register offset.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   EHCI operation register offset.\r
  @param  Data     The data to write.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits are Write-Clean.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @return None.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV         *Ehc\r
  );\r
\r
\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc     The EHCI device.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is halt.\r
  @return EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV         *Ehc,\r
  IN UINT32              Timeout\r
  );\r
\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
#endif\r
Commit	Line	Data
913cb9dc	1	/** @file\r
913cb9dc	2	\r
78c2ffb5	3	This file contains the definination for host controller register operation routines.\r
78c2ffb5	4	\r
913cb9dc	5	Copyright (c) 2007, Intel Corporation\r
	6	All rights reserved. This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
913cb9dc	14	**/\r
	15	\r
	16	#ifndef _EFI_EHCI_REG_H_\r
	17	#define _EFI_EHCI_REG_H_\r
	18	\r
	19	\r
78c2ffb5	20	typedef enum {\r
913cb9dc	21	//\r
	22	// Capability register offset\r
	23	//\r
	24	EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset\r
	25	EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h\r
	26	EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset\r
	27	\r
	28	//\r
	29	// Capability register bit definition\r
	30	//\r
	31	HCSP_NPORTS = 0x0F, // Number of root hub port\r
	32	HCCP_64BIT = 0x01, // 64-bit addressing capability\r
	33	\r
	34	//\r
	35	// Operational register offset\r
	36	//\r
	37	EHC_USBCMD_OFFSET = 0x0, // USB command register offset\r
	38	EHC_USBSTS_OFFSET = 0x04, // Statue register offset\r
	39	EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset\r
	40	EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset\r
	41	EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset\r
	42	EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset\r
	43	EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset\r
	44	EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset\r
	45	EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset\r
	46	\r
	47	EHC_FRAME_LEN = 1024,\r
	48	\r
	49	//\r
	50	// Register bit definition\r
	51	//\r
	52	CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC\r
	53	\r
	54	USBCMD_RUN = 0x01, // Run/stop\r
	55	USBCMD_RESET = 0x02, // Start the host controller reset\r
	56	USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule\r
	57	USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule\r
	58	USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell\r
	59	\r
	60	USBSTS_IAA = 0x20, // Interrupt on async advance\r
	61	USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status\r
	62	USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status\r
	63	USBSTS_HALT = 0x1000, // Host controller halted\r
	64	USBSTS_SYS_ERROR = 0x10, // Host system error\r
	65	USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC\r
	66	// (write clean) bits in USBSTS register\r
	67	\r
	68	PORTSC_CONN = 0x01, // Current Connect Status\r
	69	PORTSC_CONN_CHANGE = 0x02, // Connect Status Change\r
	70	PORTSC_ENABLED = 0x04, // Port Enable / Disable\r
	71	PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change\r
	72	PORTSC_OVERCUR = 0x10, // Over current Active\r
	73	PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change\r
	74	PORSTSC_RESUME = 0x40, // Force Port Resume\r
	75	PORTSC_SUSPEND = 0x80, // Port Suspend State\r
	76	PORTSC_RESET = 0x100, // Port Reset\r
	77	PORTSC_LINESTATE_K = 0x400, // Line Status K-state\r
	78	PORTSC_LINESTATE_J = 0x800, // Line Status J-state\r
	79	PORTSC_POWER = 0x1000, // Port Power\r
	80	PORTSC_OWNER = 0x2000, // Port Owner\r
	81	PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,\r
	82	// they are WC (write clean)\r
	83	//\r
	84	// PCI Configuration Registers\r
85	//\r
86	EHC_PCI_CLASSC = 0x09,\r
87	EHC_PCI_CLASSC_PI = 0x20,\r
c52fa98c	88	EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */\r
78c2ffb5	89	}EHCI_REGISTER_OFFSET;\r
913cb9dc	90	\r
	91	#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
	92	\r
	93	#define EHC_ADDR(High, QhHw32) \\r
	94	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))\r
	95	\r
	96	#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
	97	\r
	98	//\r
	99	// Structure to map the hardware port states to the\r
	100	// UEFI's port states.\r
	101	//\r
	102	typedef struct {\r
	103	UINT16 HwState;\r
	104	UINT16 UefiState;\r
	105	} USB_PORT_STATE_MAP;\r
	106	\r
	107	//\r
	108	// Ehci Data and Ctrl Structures\r
	109	//\r
	110	#pragma pack(1)\r
	111	typedef struct {\r
	112	UINT8 PI;\r
	113	UINT8 SubClassCode;\r
	114	UINT8 BaseCode;\r
	115	} USB_CLASSC;\r
	116	#pragma pack()\r
	117	\r
78c2ffb5	118	/**\r
	119	Read EHCI capability register.\r
	120	\r
	121	@param Ehc The EHCI device.\r
	122	@param Offset Capability register address.\r
	123	\r
	124	@return The register content.\r
913cb9dc	125	\r
78c2ffb5	126	**/\r
913cb9dc	127	UINT32\r
	128	EhcReadCapRegister (\r
	129	IN USB2_HC_DEV *Ehc,\r
	130	IN UINT32 Offset\r
ed66e1bc	131	);\r
913cb9dc	132	\r
	133	\r
	134	/**\r
78c2ffb5	135	Read EHCI Operation register.\r
913cb9dc	136	\r
78c2ffb5	137	@param Ehc The EHCI device.\r
78c2ffb5	138	@param Offset The operation register offset.\r
913cb9dc	139	\r
78c2ffb5	140	@return The register content.\r
913cb9dc	141	\r
	142	**/\r
	143	UINT32\r
	144	EhcReadOpReg (\r
	145	IN USB2_HC_DEV *Ehc,\r
	146	IN UINT32 Offset\r
ed66e1bc	147	);\r
913cb9dc	148	\r
	149	\r
	150	/**\r
78c2ffb5	151	Write the data to the EHCI operation register.\r
913cb9dc	152	\r
78c2ffb5	153	@param Ehc The EHCI device.\r
	154	@param Offset EHCI operation register offset.\r
	155	@param Data The data to write.\r
913cb9dc	156	\r
78c2ffb5	157	@return None.\r
913cb9dc	158	\r
	159	**/\r
	160	VOID\r
	161	EhcWriteOpReg (\r
	162	IN USB2_HC_DEV *Ehc,\r
	163	IN UINT32 Offset,\r
	164	IN UINT32 Data\r
ed66e1bc	165	);\r
913cb9dc	166	\r
	167	\r
	168	/**\r
	169	Add support for UEFI Over Legacy (UoL) feature, stop\r
78c2ffb5	170	the legacy USB SMI support.\r
913cb9dc	171	\r
	172	@param Ehc The EHCI device.\r
	173	\r
78c2ffb5	174	@return None.\r
913cb9dc	175	\r
	176	**/\r
	177	VOID\r
	178	EhcClearLegacySupport (\r
	179	IN USB2_HC_DEV *Ehc\r
ed66e1bc	180	);\r
913cb9dc	181	\r
	182	\r
	183	\r
	184	/**\r
	185	Set door bell and wait it to be ACKed by host controller.\r
	186	This function is used to synchronize with the hardware.\r
	187	\r
78c2ffb5	188	@param Ehc The EHCI device.\r
78c2ffb5	189	@param Timeout The time to wait before abort (in millisecond, ms).\r
913cb9dc	190	\r
78c2ffb5	191	@retval EFI_SUCCESS Synchronized with the hardware.\r
78c2ffb5	192	@retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
913cb9dc	193	\r
	194	**/\r
	195	EFI_STATUS\r
	196	EhcSetAndWaitDoorBell (\r
	197	IN USB2_HC_DEV *Ehc,\r
	198	IN UINT32 Timeout\r
ed66e1bc	199	);\r
913cb9dc	200	\r
	201	\r
	202	/**\r
78c2ffb5	203	Clear all the interrutp status bits, these bits are Write-Clean.\r
913cb9dc	204	\r
78c2ffb5	205	@param Ehc The EHCI device.\r
913cb9dc	206	\r
78c2ffb5	207	@return None.\r
913cb9dc	208	\r
	209	**/\r
	210	VOID\r
	211	EhcAckAllInterrupt (\r
	212	IN USB2_HC_DEV *Ehc\r
ed66e1bc	213	);\r
913cb9dc	214	\r
	215	\r
	216	\r
	217	/**\r
78c2ffb5	218	Whether Ehc is halted.\r
913cb9dc	219	\r
78c2ffb5	220	@param Ehc The EHCI device.\r
913cb9dc	221	\r
78c2ffb5	222	@retval TRUE The controller is halted.\r
78c2ffb5	223	@retval FALSE It isn't halted.\r
913cb9dc	224	\r
	225	**/\r
	226	BOOLEAN\r
	227	EhcIsHalt (\r
	228	IN USB2_HC_DEV *Ehc\r
ed66e1bc	229	);\r
913cb9dc	230	\r
	231	\r
	232	/**\r
78c2ffb5	233	Whether system error occurred.\r
913cb9dc	234	\r
78c2ffb5	235	@param Ehc The EHCI device.\r
913cb9dc	236	\r
78c2ffb5	237	@retval TRUE System error happened.\r
78c2ffb5	238	@retval FALSE No system error.\r
913cb9dc	239	\r
	240	**/\r
	241	BOOLEAN\r
	242	EhcIsSysError (\r
	243	IN USB2_HC_DEV *Ehc\r
ed66e1bc	244	);\r
913cb9dc	245	\r
913cb9dc	246	\r
913cb9dc	247	/**\r
78c2ffb5	248	Reset the host controller.\r
913cb9dc	249	\r
78c2ffb5	250	@param Ehc The EHCI device.\r
78c2ffb5	251	@param Timeout Time to wait before abort (in millisecond, ms).\r
913cb9dc	252	\r
78c2ffb5	253	@retval EFI_SUCCESS The host controller is reset.\r
78c2ffb5	254	@return Others Failed to reset the host.\r
913cb9dc	255	\r
	256	**/\r
	257	EFI_STATUS\r
	258	EhcResetHC (\r
	259	IN USB2_HC_DEV *Ehc,\r
	260	IN UINT32 Timeout\r
ed66e1bc	261	);\r
913cb9dc	262	\r
913cb9dc	263	\r
913cb9dc	264	/**\r
78c2ffb5	265	Halt the host controller.\r
913cb9dc	266	\r
78c2ffb5	267	@param Ehc The EHCI device.\r
78c2ffb5	268	@param Timeout Time to wait before abort.\r
913cb9dc	269	\r
78c2ffb5	270	@return EFI_SUCCESS The EHCI is halt.\r
78c2ffb5	271	@return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
913cb9dc	272	\r
	273	**/\r
	274	EFI_STATUS\r
	275	EhcHaltHC (\r
	276	IN USB2_HC_DEV *Ehc,\r
	277	IN UINT32 Timeout\r
ed66e1bc	278	);\r
913cb9dc	279	\r
913cb9dc	280	\r
913cb9dc	281	/**\r
78c2ffb5	282	Set the EHCI to run.\r
913cb9dc	283	\r
78c2ffb5	284	@param Ehc The EHCI device.\r
78c2ffb5	285	@param Timeout Time to wait before abort.\r
913cb9dc	286	\r
78c2ffb5	287	@return EFI_SUCCESS The EHCI is running.\r
78c2ffb5	288	@return Others Failed to set the EHCI to run.\r
913cb9dc	289	\r
	290	**/\r
	291	EFI_STATUS\r
	292	EhcRunHC (\r
	293	IN USB2_HC_DEV *Ehc,\r
	294	IN UINT32 Timeout\r
ed66e1bc	295	);\r
913cb9dc	296	\r
	297	\r
	298	\r
	299	/**\r
	300	Initialize the HC hardware.\r
78c2ffb5	301	EHCI spec lists the five things to do to initialize the hardware:\r
913cb9dc	302	1. Program CTRLDSSEGMENT\r
	303	2. Set USBINTR to enable interrupts\r
	304	3. Set periodic list base\r
	305	4. Set USBCMD, interrupt threshold, frame list size etc\r
	306	5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
	307	\r
78c2ffb5	308	@param Ehc The EHCI device.\r
913cb9dc	309	\r
78c2ffb5	310	@return EFI_SUCCESS The EHCI has come out of halt state.\r
78c2ffb5	311	@return EFI_TIMEOUT Time out happened.\r
913cb9dc	312	\r
	313	**/\r
	314	EFI_STATUS\r
	315	EhcInitHC (\r
	316	IN USB2_HC_DEV *Ehc\r
ed66e1bc	317	);\r
913cb9dc	318	\r
913cb9dc	319	#endif\r