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modify coding style to pass ecc tool and provide comments that complied with Doxgen.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h
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913cb9dc 1/** @file\r
2\r
78c2ffb5 3 This file contains the definination for host controller register operation routines.\r
4\r
913cb9dc 5Copyright (c) 2007, Intel Corporation\r
6All rights reserved. This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
913cb9dc 14**/\r
15\r
16#ifndef _EFI_EHCI_REG_H_\r
17#define _EFI_EHCI_REG_H_\r
18\r
19\r
78c2ffb5 20typedef enum {\r
913cb9dc 21 //\r
22 // Capability register offset\r
23 //\r
24 EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset\r
25 EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h\r
26 EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset\r
27\r
28 //\r
29 // Capability register bit definition\r
30 //\r
31 HCSP_NPORTS = 0x0F, // Number of root hub port\r
32 HCCP_64BIT = 0x01, // 64-bit addressing capability\r
33\r
34 //\r
35 // Operational register offset\r
36 //\r
37 EHC_USBCMD_OFFSET = 0x0, // USB command register offset\r
38 EHC_USBSTS_OFFSET = 0x04, // Statue register offset\r
39 EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset\r
40 EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset\r
41 EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset\r
42 EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset\r
43 EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset\r
44 EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset\r
45 EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset\r
46\r
47 EHC_FRAME_LEN = 1024,\r
48\r
49 //\r
50 // Register bit definition\r
51 //\r
52 CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC\r
53\r
54 USBCMD_RUN = 0x01, // Run/stop\r
55 USBCMD_RESET = 0x02, // Start the host controller reset\r
56 USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule\r
57 USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule\r
58 USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell\r
59\r
60 USBSTS_IAA = 0x20, // Interrupt on async advance\r
61 USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status\r
62 USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status\r
63 USBSTS_HALT = 0x1000, // Host controller halted\r
64 USBSTS_SYS_ERROR = 0x10, // Host system error\r
65 USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC\r
66 // (write clean) bits in USBSTS register\r
67\r
68 PORTSC_CONN = 0x01, // Current Connect Status\r
69 PORTSC_CONN_CHANGE = 0x02, // Connect Status Change\r
70 PORTSC_ENABLED = 0x04, // Port Enable / Disable\r
71 PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change\r
72 PORTSC_OVERCUR = 0x10, // Over current Active\r
73 PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change\r
74 PORSTSC_RESUME = 0x40, // Force Port Resume\r
75 PORTSC_SUSPEND = 0x80, // Port Suspend State\r
76 PORTSC_RESET = 0x100, // Port Reset\r
77 PORTSC_LINESTATE_K = 0x400, // Line Status K-state\r
78 PORTSC_LINESTATE_J = 0x800, // Line Status J-state\r
79 PORTSC_POWER = 0x1000, // Port Power\r
80 PORTSC_OWNER = 0x2000, // Port Owner\r
81 PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,\r
82 // they are WC (write clean)\r
83 //\r
84 // PCI Configuration Registers\r
85 //\r
86 EHC_PCI_CLASSC = 0x09,\r
87 EHC_PCI_CLASSC_PI = 0x20,\r
c52fa98c 88 EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */\r
78c2ffb5 89}EHCI_REGISTER_OFFSET;\r
913cb9dc 90\r
91#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
92\r
93#define EHC_ADDR(High, QhHw32) \\r
94 ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
95\r
96#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
97\r
98//\r
99// Structure to map the hardware port states to the\r
100// UEFI's port states.\r
101//\r
102typedef struct {\r
103 UINT16 HwState;\r
104 UINT16 UefiState;\r
105} USB_PORT_STATE_MAP;\r
106\r
107//\r
108// Ehci Data and Ctrl Structures\r
109//\r
110#pragma pack(1)\r
111typedef struct {\r
112 UINT8 PI;\r
113 UINT8 SubClassCode;\r
114 UINT8 BaseCode;\r
115} USB_CLASSC;\r
116#pragma pack()\r
117\r
78c2ffb5 118/**\r
119 Read EHCI capability register.\r
120\r
121 @param Ehc The EHCI device.\r
122 @param Offset Capability register address.\r
123\r
124 @return The register content.\r
913cb9dc 125\r
78c2ffb5 126**/\r
913cb9dc 127UINT32\r
128EhcReadCapRegister (\r
129 IN USB2_HC_DEV *Ehc,\r
130 IN UINT32 Offset\r
131 )\r
913cb9dc 132;\r
133\r
134\r
135/**\r
78c2ffb5 136 Read EHCI Operation register.\r
913cb9dc 137\r
78c2ffb5 138 @param Ehc The EHCI device.\r
139 @param Offset The operation register offset.\r
913cb9dc 140\r
78c2ffb5 141 @return The register content.\r
913cb9dc 142\r
143**/\r
144UINT32\r
145EhcReadOpReg (\r
146 IN USB2_HC_DEV *Ehc,\r
147 IN UINT32 Offset\r
148 )\r
149;\r
150\r
151\r
152/**\r
78c2ffb5 153 Write the data to the EHCI operation register.\r
913cb9dc 154\r
78c2ffb5 155 @param Ehc The EHCI device.\r
156 @param Offset EHCI operation register offset.\r
157 @param Data The data to write.\r
913cb9dc 158\r
78c2ffb5 159 @return None.\r
913cb9dc 160\r
161**/\r
162VOID\r
163EhcWriteOpReg (\r
164 IN USB2_HC_DEV *Ehc,\r
165 IN UINT32 Offset,\r
166 IN UINT32 Data\r
167 )\r
168;\r
169\r
170\r
171/**\r
172 Add support for UEFI Over Legacy (UoL) feature, stop\r
78c2ffb5 173 the legacy USB SMI support.\r
913cb9dc 174\r
175 @param Ehc The EHCI device.\r
176\r
78c2ffb5 177 @return None.\r
913cb9dc 178\r
179**/\r
180VOID\r
181EhcClearLegacySupport (\r
182 IN USB2_HC_DEV *Ehc\r
183 )\r
184;\r
185\r
186\r
187\r
188/**\r
189 Set door bell and wait it to be ACKed by host controller.\r
190 This function is used to synchronize with the hardware.\r
191\r
78c2ffb5 192 @param Ehc The EHCI device.\r
193 @param Timeout The time to wait before abort (in millisecond, ms).\r
913cb9dc 194\r
78c2ffb5 195 @retval EFI_SUCCESS Synchronized with the hardware.\r
196 @retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
913cb9dc 197\r
198**/\r
199EFI_STATUS\r
200EhcSetAndWaitDoorBell (\r
201 IN USB2_HC_DEV *Ehc,\r
202 IN UINT32 Timeout\r
203 )\r
204;\r
205\r
206\r
207/**\r
78c2ffb5 208 Clear all the interrutp status bits, these bits are Write-Clean.\r
913cb9dc 209\r
78c2ffb5 210 @param Ehc The EHCI device.\r
913cb9dc 211\r
78c2ffb5 212 @return None.\r
913cb9dc 213\r
214**/\r
215VOID\r
216EhcAckAllInterrupt (\r
217 IN USB2_HC_DEV *Ehc\r
218 )\r
219;\r
220\r
221\r
222\r
223/**\r
78c2ffb5 224 Whether Ehc is halted.\r
913cb9dc 225\r
78c2ffb5 226 @param Ehc The EHCI device.\r
913cb9dc 227\r
78c2ffb5 228 @retval TRUE The controller is halted.\r
229 @retval FALSE It isn't halted.\r
913cb9dc 230\r
231**/\r
232BOOLEAN\r
233EhcIsHalt (\r
234 IN USB2_HC_DEV *Ehc\r
235 )\r
236;\r
237\r
238\r
239/**\r
78c2ffb5 240 Whether system error occurred.\r
913cb9dc 241\r
78c2ffb5 242 @param Ehc The EHCI device.\r
913cb9dc 243\r
78c2ffb5 244 @retval TRUE System error happened.\r
245 @retval FALSE No system error.\r
913cb9dc 246\r
247**/\r
248BOOLEAN\r
249EhcIsSysError (\r
250 IN USB2_HC_DEV *Ehc\r
251 )\r
252;\r
253\r
254\r
913cb9dc 255/**\r
78c2ffb5 256 Reset the host controller.\r
913cb9dc 257\r
78c2ffb5 258 @param Ehc The EHCI device.\r
259 @param Timeout Time to wait before abort (in millisecond, ms).\r
913cb9dc 260\r
78c2ffb5 261 @retval EFI_SUCCESS The host controller is reset.\r
262 @return Others Failed to reset the host.\r
913cb9dc 263\r
264**/\r
265EFI_STATUS\r
266EhcResetHC (\r
267 IN USB2_HC_DEV *Ehc,\r
268 IN UINT32 Timeout\r
269 )\r
270;\r
271\r
272\r
913cb9dc 273/**\r
78c2ffb5 274 Halt the host controller.\r
913cb9dc 275\r
78c2ffb5 276 @param Ehc The EHCI device.\r
277 @param Timeout Time to wait before abort.\r
913cb9dc 278\r
78c2ffb5 279 @return EFI_SUCCESS The EHCI is halt.\r
280 @return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
913cb9dc 281\r
282**/\r
283EFI_STATUS\r
284EhcHaltHC (\r
285 IN USB2_HC_DEV *Ehc,\r
286 IN UINT32 Timeout\r
287 )\r
288;\r
289\r
290\r
913cb9dc 291/**\r
78c2ffb5 292 Set the EHCI to run.\r
913cb9dc 293\r
78c2ffb5 294 @param Ehc The EHCI device.\r
295 @param Timeout Time to wait before abort.\r
913cb9dc 296\r
78c2ffb5 297 @return EFI_SUCCESS The EHCI is running.\r
298 @return Others Failed to set the EHCI to run.\r
913cb9dc 299\r
300**/\r
301EFI_STATUS\r
302EhcRunHC (\r
303 IN USB2_HC_DEV *Ehc,\r
304 IN UINT32 Timeout\r
305 )\r
306;\r
307\r
308\r
309\r
310/**\r
311 Initialize the HC hardware.\r
78c2ffb5 312 EHCI spec lists the five things to do to initialize the hardware:\r
913cb9dc 313 1. Program CTRLDSSEGMENT\r
314 2. Set USBINTR to enable interrupts\r
315 3. Set periodic list base\r
316 4. Set USBCMD, interrupt threshold, frame list size etc\r
317 5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
318\r
78c2ffb5 319 @param Ehc The EHCI device.\r
913cb9dc 320\r
78c2ffb5 321 @return EFI_SUCCESS The EHCI has come out of halt state.\r
322 @return EFI_TIMEOUT Time out happened.\r
913cb9dc 323\r
324**/\r
325EFI_STATUS\r
326EhcInitHC (\r
327 IN USB2_HC_DEV *Ehc\r
328 )\r
329;\r
330\r
331#endif\r
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