[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h

/** @file\r
\r
  This file contains the definination for host controller register operation routines.\r
\r
Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
//\r
// EHCI register offset\r
//\r
\r
\r
//\r
// Capability register offset\r
//\r
#define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset\r
#define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h\r
#define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset\r
\r
//\r
// Capability register bit definition\r
//\r
#define HCSP_NPORTS             0x0F // Number of root hub port\r
#define HCSP_PPC                0x10 // Port Power Control\r
#define HCCP_64BIT              0x01 // 64-bit addressing capability\r
\r
//\r
// Operational register offset\r
//\r
#define EHC_USBCMD_OFFSET       0x0  // USB command register offset\r
#define EHC_USBSTS_OFFSET       0x04 // Statue register offset\r
#define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset\r
#define EHC_FRINDEX_OFFSET      0x0C // Frame index offset\r
#define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset\r
#define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset\r
#define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset\r
#define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset\r
#define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset\r
\r
#define EHC_FRAME_LEN           1024\r
\r
//\r
// Register bit definition\r
//\r
#define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC\r
\r
#define USBCMD_RUN              0x01   // Run/stop\r
#define USBCMD_RESET            0x02   // Start the host controller reset\r
#define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule\r
#define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule\r
#define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell\r
\r
#define USBSTS_IAA              0x20   // Interrupt on async advance\r
#define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status\r
#define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status\r
#define USBSTS_HALT             0x1000 // Host controller halted\r
#define USBSTS_SYS_ERROR        0x10   // Host system error\r
#define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC\r
                                       // (write clean) bits in USBSTS register\r
\r
#define PORTSC_CONN             0x01   // Current Connect Status\r
#define PORTSC_CONN_CHANGE      0x02   // Connect Status Change\r
#define PORTSC_ENABLED          0x04   // Port Enable / Disable\r
#define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change\r
#define PORTSC_OVERCUR          0x10   // Over current Active\r
#define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change\r
#define PORSTSC_RESUME          0x40   // Force Port Resume\r
#define PORTSC_SUSPEND          0x80   // Port Suspend State\r
#define PORTSC_RESET            0x100  // Port Reset\r
#define PORTSC_LINESTATE_K      0x400  // Line Status K-state\r
#define PORTSC_LINESTATE_J      0x800  // Line Status J-state\r
#define PORTSC_POWER            0x1000 // Port Power\r
#define PORTSC_OWNER            0x2000 // Port Owner\r
#define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,\r
                                       // they are WC (write clean)\r
//\r
// PCI Configuration Registers\r
//\r
#define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10\r
\r
//\r
// Debug port capability id\r
//\r
#define EHC_DEBUG_PORT_CAP_ID   0x0A\r
\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32)   \\r
        ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT16                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Ehci Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   ProgInterface;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc     The EHCI device.\r
  @param  Offset  Capability register address.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Check whether the host controller has an in-use debug port.\r
\r
  @param[in] Ehc         The Enhanced Host Controller to query.\r
\r
  @param[in] PortNumber  If PortNumber is not NULL, then query whether\r
                         PortNumber is an in-use debug port on Ehc. (PortNumber\r
                         is taken in UEFI notation, i.e., zero-based.)\r
                         Otherwise, query whether Ehc has any in-use debug\r
                         port.\r
\r
  @retval TRUE   PortNumber is an in-use debug port on Ehc (if PortNumber is\r
                 not NULL), or some port on Ehc is an in-use debug port\r
                 (otherwise).\r
\r
  @retval FALSE  PortNumber is not an in-use debug port on Ehc (if PortNumber\r
                 is not NULL), or no port on Ehc is an in-use debug port\r
                 (otherwise).\r
**/\r
BOOLEAN\r
EhcIsDebugPortInUse (\r
  IN CONST USB2_HC_DEV *Ehc,\r
  IN CONST UINT8       *PortNumber OPTIONAL\r
  );\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   The operation register offset.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   EHCI operation register offset.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
EhcSetOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
EhcClearOpRegBit (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits are Write-Clean.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV         *Ehc\r
  );\r
\r
\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc     The EHCI device.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is halt.\r
  @return EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV         *Ehc,\r
  IN UINT32              Timeout\r
  );\r
\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
#endif\r
Commit	Line	Data
913cb9dc	1	/** @file\r
913cb9dc	2	\r
78c2ffb5	3	This file contains the definination for host controller register operation routines.\r
78c2ffb5	4	\r
09943f5e	5	Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0	6	This program and the accompanying materials\r
913cb9dc	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
913cb9dc	14	**/\r
	15	\r
	16	#ifndef _EFI_EHCI_REG_H_\r
	17	#define _EFI_EHCI_REG_H_\r
	18	\r
1ccdbf2a	19	//\r
	20	// EHCI register offset\r
	21	//\r
	22	\r
	23	\r
	24	//\r
	25	// Capability register offset\r
	26	//\r
	27	#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r
	28	#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r
	29	#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r
	30	\r
	31	//\r
	32	// Capability register bit definition\r
	33	//\r
	34	#define HCSP_NPORTS 0x0F // Number of root hub port\r
f01219e8	35	#define HCSP_PPC 0x10 // Port Power Control\r
1ccdbf2a	36	#define HCCP_64BIT 0x01 // 64-bit addressing capability\r
	37	\r
	38	//\r
	39	// Operational register offset\r
	40	//\r
	41	#define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r
	42	#define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r
	43	#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r
	44	#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r
	45	#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r
	46	#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r
	47	#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r
	48	#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r
	49	#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r
	50	\r
	51	#define EHC_FRAME_LEN 1024\r
913cb9dc	52	\r
1ccdbf2a	53	//\r
	54	// Register bit definition\r
	55	//\r
	56	#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r
	57	\r
	58	#define USBCMD_RUN 0x01 // Run/stop\r
	59	#define USBCMD_RESET 0x02 // Start the host controller reset\r
	60	#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r
	61	#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r
	62	#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r
	63	\r
	64	#define USBSTS_IAA 0x20 // Interrupt on async advance\r
	65	#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r
	66	#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r
	67	#define USBSTS_HALT 0x1000 // Host controller halted\r
	68	#define USBSTS_SYS_ERROR 0x10 // Host system error\r
	69	#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r
	70	// (write clean) bits in USBSTS register\r
	71	\r
	72	#define PORTSC_CONN 0x01 // Current Connect Status\r
	73	#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r
	74	#define PORTSC_ENABLED 0x04 // Port Enable / Disable\r
	75	#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r
	76	#define PORTSC_OVERCUR 0x10 // Over current Active\r
	77	#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r
	78	#define PORSTSC_RESUME 0x40 // Force Port Resume\r
	79	#define PORTSC_SUSPEND 0x80 // Port Suspend State\r
	80	#define PORTSC_RESET 0x100 // Port Reset\r
	81	#define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r
	82	#define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r
	83	#define PORTSC_POWER 0x1000 // Port Power\r
	84	#define PORTSC_OWNER 0x2000 // Port Owner\r
	85	#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r
	86	// they are WC (write clean)\r
	87	//\r
	88	// PCI Configuration Registers\r
	89	//\r
	90	#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r
913cb9dc	91	\r
09943f5e	92	//\r
	93	// Debug port capability id\r
	94	//\r
	95	#define EHC_DEBUG_PORT_CAP_ID 0x0A\r
	96	\r
913cb9dc	97	#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
	98	\r
	99	#define EHC_ADDR(High, QhHw32) \\r
	100	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))\r
	101	\r
	102	#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
	103	\r
	104	//\r
	105	// Structure to map the hardware port states to the\r
	106	// UEFI's port states.\r
	107	//\r
	108	typedef struct {\r
	109	UINT16 HwState;\r
	110	UINT16 UefiState;\r
	111	} USB_PORT_STATE_MAP;\r
	112	\r
	113	//\r
	114	// Ehci Data and Ctrl Structures\r
	115	//\r
	116	#pragma pack(1)\r
	117	typedef struct {\r
1ccdbf2a	118	UINT8 ProgInterface;\r
913cb9dc	119	UINT8 SubClassCode;\r
	120	UINT8 BaseCode;\r
	121	} USB_CLASSC;\r
	122	#pragma pack()\r
	123	\r
78c2ffb5	124	/**\r
	125	Read EHCI capability register.\r
	126	\r
	127	@param Ehc The EHCI device.\r
	128	@param Offset Capability register address.\r
	129	\r
	130	@return The register content.\r
913cb9dc	131	\r
78c2ffb5	132	**/\r
913cb9dc	133	UINT32\r
	134	EhcReadCapRegister (\r
	135	IN USB2_HC_DEV *Ehc,\r
	136	IN UINT32 Offset\r
ed66e1bc	137	);\r
913cb9dc	138	\r
09943f5e	139	/**\r
b48ec0e8	140	Check whether the host controller has an in-use debug port.\r
09943f5e	141	\r
b48ec0e8	142	@param[in] Ehc The Enhanced Host Controller to query.\r
09943f5e	143	\r
b48ec0e8 LE	144	@param[in] PortNumber If PortNumber is not NULL, then query whether\r
	145	PortNumber is an in-use debug port on Ehc. (PortNumber\r
	146	is taken in UEFI notation, i.e., zero-based.)\r
	147	Otherwise, query whether Ehc has any in-use debug\r
	148	port.\r
09943f5e	149	\r
b48ec0e8 LE	150	@retval TRUE PortNumber is an in-use debug port on Ehc (if PortNumber is\r
	151	not NULL), or some port on Ehc is an in-use debug port\r
	152	(otherwise).\r
	153	\r
	154	@retval FALSE PortNumber is not an in-use debug port on Ehc (if PortNumber\r
	155	is not NULL), or no port on Ehc is an in-use debug port\r
	156	(otherwise).\r
09943f5e	157	**/\r
b48ec0e8 LE	158	BOOLEAN\r
	159	EhcIsDebugPortInUse (\r
	160	IN CONST USB2_HC_DEV *Ehc,\r
	161	IN CONST UINT8 *PortNumber OPTIONAL\r
09943f5e	162	);\r
913cb9dc	163	\r
913cb9dc	164	/**\r
78c2ffb5	165	Read EHCI Operation register.\r
913cb9dc	166	\r
78c2ffb5	167	@param Ehc The EHCI device.\r
78c2ffb5	168	@param Offset The operation register offset.\r
913cb9dc	169	\r
78c2ffb5	170	@return The register content.\r
913cb9dc	171	\r
	172	**/\r
	173	UINT32\r
	174	EhcReadOpReg (\r
	175	IN USB2_HC_DEV *Ehc,\r
	176	IN UINT32 Offset\r
ed66e1bc	177	);\r
913cb9dc	178	\r
	179	\r
	180	/**\r
78c2ffb5	181	Write the data to the EHCI operation register.\r
913cb9dc	182	\r
78c2ffb5	183	@param Ehc The EHCI device.\r
	184	@param Offset EHCI operation register offset.\r
	185	@param Data The data to write.\r
913cb9dc	186	\r
913cb9dc	187	**/\r
	188	VOID\r
	189	EhcWriteOpReg (\r
	190	IN USB2_HC_DEV *Ehc,\r
	191	IN UINT32 Offset,\r
	192	IN UINT32 Data\r
ed66e1bc	193	);\r
913cb9dc	194	\r
efe9186f	195	/**\r
	196	Set one bit of the operational register while keeping other bits.\r
	197	\r
	198	@param Ehc The EHCI device.\r
	199	@param Offset The offset of the operational register.\r
	200	@param Bit The bit mask of the register to set.\r
	201	\r
	202	**/\r
	203	VOID\r
	204	EhcSetOpRegBit (\r
	205	IN USB2_HC_DEV *Ehc,\r
	206	IN UINT32 Offset,\r
	207	IN UINT32 Bit\r
	208	);\r
	209	\r
	210	/**\r
	211	Clear one bit of the operational register while keeping other bits.\r
	212	\r
	213	@param Ehc The EHCI device.\r
	214	@param Offset The offset of the operational register.\r
	215	@param Bit The bit mask of the register to clear.\r
	216	\r
	217	**/\r
	218	VOID\r
	219	EhcClearOpRegBit (\r
	220	IN USB2_HC_DEV *Ehc,\r
	221	IN UINT32 Offset,\r
	222	IN UINT32 Bit\r
	223	);\r
913cb9dc	224	\r
	225	/**\r
	226	Add support for UEFI Over Legacy (UoL) feature, stop\r
78c2ffb5	227	the legacy USB SMI support.\r
913cb9dc	228	\r
	229	@param Ehc The EHCI device.\r
	230	\r
913cb9dc	231	**/\r
	232	VOID\r
	233	EhcClearLegacySupport (\r
	234	IN USB2_HC_DEV *Ehc\r
ed66e1bc	235	);\r
913cb9dc	236	\r
	237	\r
	238	\r
	239	/**\r
	240	Set door bell and wait it to be ACKed by host controller.\r
	241	This function is used to synchronize with the hardware.\r
	242	\r
78c2ffb5	243	@param Ehc The EHCI device.\r
78c2ffb5	244	@param Timeout The time to wait before abort (in millisecond, ms).\r
913cb9dc	245	\r
78c2ffb5	246	@retval EFI_SUCCESS Synchronized with the hardware.\r
78c2ffb5	247	@retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
913cb9dc	248	\r
	249	**/\r
	250	EFI_STATUS\r
	251	EhcSetAndWaitDoorBell (\r
	252	IN USB2_HC_DEV *Ehc,\r
	253	IN UINT32 Timeout\r
ed66e1bc	254	);\r
913cb9dc	255	\r
	256	\r
	257	/**\r
78c2ffb5	258	Clear all the interrutp status bits, these bits are Write-Clean.\r
913cb9dc	259	\r
78c2ffb5	260	@param Ehc The EHCI device.\r
913cb9dc	261	\r
913cb9dc	262	**/\r
	263	VOID\r
	264	EhcAckAllInterrupt (\r
	265	IN USB2_HC_DEV *Ehc\r
ed66e1bc	266	);\r
913cb9dc	267	\r
	268	\r
	269	\r
	270	/**\r
78c2ffb5	271	Whether Ehc is halted.\r
913cb9dc	272	\r
78c2ffb5	273	@param Ehc The EHCI device.\r
913cb9dc	274	\r
78c2ffb5	275	@retval TRUE The controller is halted.\r
78c2ffb5	276	@retval FALSE It isn't halted.\r
913cb9dc	277	\r
	278	**/\r
	279	BOOLEAN\r
	280	EhcIsHalt (\r
	281	IN USB2_HC_DEV *Ehc\r
ed66e1bc	282	);\r
913cb9dc	283	\r
	284	\r
	285	/**\r
78c2ffb5	286	Whether system error occurred.\r
913cb9dc	287	\r
78c2ffb5	288	@param Ehc The EHCI device.\r
913cb9dc	289	\r
78c2ffb5	290	@retval TRUE System error happened.\r
78c2ffb5	291	@retval FALSE No system error.\r
913cb9dc	292	\r
	293	**/\r
	294	BOOLEAN\r
	295	EhcIsSysError (\r
	296	IN USB2_HC_DEV *Ehc\r
ed66e1bc	297	);\r
913cb9dc	298	\r
913cb9dc	299	\r
913cb9dc	300	/**\r
78c2ffb5	301	Reset the host controller.\r
913cb9dc	302	\r
78c2ffb5	303	@param Ehc The EHCI device.\r
78c2ffb5	304	@param Timeout Time to wait before abort (in millisecond, ms).\r
913cb9dc	305	\r
78c2ffb5	306	@retval EFI_SUCCESS The host controller is reset.\r
78c2ffb5	307	@return Others Failed to reset the host.\r
913cb9dc	308	\r
	309	**/\r
	310	EFI_STATUS\r
	311	EhcResetHC (\r
	312	IN USB2_HC_DEV *Ehc,\r
	313	IN UINT32 Timeout\r
ed66e1bc	314	);\r
913cb9dc	315	\r
913cb9dc	316	\r
913cb9dc	317	/**\r
78c2ffb5	318	Halt the host controller.\r
913cb9dc	319	\r
78c2ffb5	320	@param Ehc The EHCI device.\r
78c2ffb5	321	@param Timeout Time to wait before abort.\r
913cb9dc	322	\r
78c2ffb5	323	@return EFI_SUCCESS The EHCI is halt.\r
78c2ffb5	324	@return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
913cb9dc	325	\r
	326	**/\r
	327	EFI_STATUS\r
	328	EhcHaltHC (\r
	329	IN USB2_HC_DEV *Ehc,\r
	330	IN UINT32 Timeout\r
ed66e1bc	331	);\r
913cb9dc	332	\r
913cb9dc	333	\r
913cb9dc	334	/**\r
78c2ffb5	335	Set the EHCI to run.\r
913cb9dc	336	\r
78c2ffb5	337	@param Ehc The EHCI device.\r
78c2ffb5	338	@param Timeout Time to wait before abort.\r
913cb9dc	339	\r
78c2ffb5	340	@return EFI_SUCCESS The EHCI is running.\r
78c2ffb5	341	@return Others Failed to set the EHCI to run.\r
913cb9dc	342	\r
	343	**/\r
	344	EFI_STATUS\r
	345	EhcRunHC (\r
	346	IN USB2_HC_DEV *Ehc,\r
	347	IN UINT32 Timeout\r
ed66e1bc	348	);\r
913cb9dc	349	\r
	350	\r
	351	\r
	352	/**\r
	353	Initialize the HC hardware.\r
78c2ffb5	354	EHCI spec lists the five things to do to initialize the hardware:\r
913cb9dc	355	1. Program CTRLDSSEGMENT\r
	356	2. Set USBINTR to enable interrupts\r
	357	3. Set periodic list base\r
	358	4. Set USBCMD, interrupt threshold, frame list size etc\r
	359	5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
	360	\r
78c2ffb5	361	@param Ehc The EHCI device.\r
913cb9dc	362	\r
78c2ffb5	363	@return EFI_SUCCESS The EHCI has come out of halt state.\r
78c2ffb5	364	@return EFI_TIMEOUT Time out happened.\r
913cb9dc	365	\r
	366	**/\r
	367	EFI_STATUS\r
	368	EhcInitHC (\r
	369	IN USB2_HC_DEV *Ehc\r
ed66e1bc	370	);\r
913cb9dc	371	\r
913cb9dc	372	#endif\r