[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.h

/** @file\r
\r
  This file contains the definination for host controller register operation routines.\r
\r
Copyright (c) 2007 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_EHCI_REG_H_\r
#define _EFI_EHCI_REG_H_\r
\r
\r
typedef enum {\r
  //\r
  // Capability register offset\r
  //\r
  EHC_CAPLENGTH_OFFSET    = 0,    // Capability register length offset\r
  EHC_HCSPARAMS_OFFSET    = 0x04, // Structural Parameters 04-07h\r
  EHC_HCCPARAMS_OFFSET    = 0x08, // Capability parameters offset\r
\r
  //\r
  // Capability register bit definition\r
  //\r
  HCSP_NPORTS             = 0x0F, // Number of root hub port\r
  HCCP_64BIT              = 0x01, // 64-bit addressing capability\r
\r
  //\r
  // Operational register offset\r
  //\r
  EHC_USBCMD_OFFSET       = 0x0,  // USB command register offset\r
  EHC_USBSTS_OFFSET       = 0x04, // Statue register offset\r
  EHC_USBINTR_OFFSET      = 0x08, // USB interrutp offset\r
  EHC_FRINDEX_OFFSET      = 0x0C, // Frame index offset\r
  EHC_CTRLDSSEG_OFFSET    = 0x10, // Control data structure segment offset\r
  EHC_FRAME_BASE_OFFSET   = 0x14, // Frame list base address offset\r
  EHC_ASYNC_HEAD_OFFSET   = 0x18, // Next asynchronous list address offset\r
  EHC_CONFIG_FLAG_OFFSET  = 0x40, // Configure flag register offset\r
  EHC_PORT_STAT_OFFSET    = 0x44, // Port status/control offset\r
\r
  EHC_FRAME_LEN           = 1024,\r
\r
  //\r
  // Register bit definition\r
  //\r
  CONFIGFLAG_ROUTE_EHC    = 0x01, // Route port to EHC\r
\r
  USBCMD_RUN              = 0x01,   // Run/stop\r
  USBCMD_RESET            = 0x02,   // Start the host controller reset\r
  USBCMD_ENABLE_PERIOD    = 0x10,   // Enable periodic schedule\r
  USBCMD_ENABLE_ASYNC     = 0x20,   // Enable asynchronous schedule\r
  USBCMD_IAAD             = 0x40,   // Interrupt on async advance doorbell\r
\r
  USBSTS_IAA              = 0x20,   // Interrupt on async advance\r
  USBSTS_PERIOD_ENABLED   = 0x4000, // Periodic schedule status\r
  USBSTS_ASYNC_ENABLED    = 0x8000, // Asynchronous schedule status\r
  USBSTS_HALT             = 0x1000, // Host controller halted\r
  USBSTS_SYS_ERROR        = 0x10,   // Host system error\r
  USBSTS_INTACK_MASK      = 0x003F, // Mask for the interrupt ACK, the WC\r
                                    // (write clean) bits in USBSTS register\r
\r
  PORTSC_CONN             = 0x01,   // Current Connect Status\r
  PORTSC_CONN_CHANGE      = 0x02,   // Connect Status Change\r
  PORTSC_ENABLED          = 0x04,   // Port Enable / Disable\r
  PORTSC_ENABLE_CHANGE    = 0x08,   // Port Enable / Disable Change\r
  PORTSC_OVERCUR          = 0x10,   // Over current Active\r
  PORTSC_OVERCUR_CHANGE   = 0x20,   // Over current Change\r
  PORSTSC_RESUME          = 0x40,   // Force Port Resume\r
  PORTSC_SUSPEND          = 0x80,   // Port Suspend State\r
  PORTSC_RESET            = 0x100,  // Port Reset\r
  PORTSC_LINESTATE_K      = 0x400,  // Line Status K-state\r
  PORTSC_LINESTATE_J      = 0x800,  // Line Status J-state\r
  PORTSC_POWER            = 0x1000, // Port Power\r
  PORTSC_OWNER            = 0x2000, // Port Owner\r
  PORTSC_CHANGE_MASK      = 0x2A,   // Mask of the port change bits,\r
                                    // they are WC (write clean)\r
  //\r
  // PCI Configuration Registers\r
  //\r
  EHC_BAR_INDEX           = 0 /* how many bytes away from USB_BASE to 0x10 */\r
}EHCI_REGISTER_OFFSET;\r
\r
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
\r
#define EHC_ADDR(High, QhHw32)   \\r
        ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r
\r
#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT16                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Ehci Data and Ctrl Structures\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                   PI;\r
  UINT8                   SubClassCode;\r
  UINT8                   BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
/**\r
  Read EHCI capability register.\r
\r
  @param  Ehc     The EHCI device.\r
  @param  Offset  Capability register address.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadCapRegister (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Read EHCI Operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   The operation register offset.\r
\r
  @return The register content.\r
\r
**/\r
UINT32\r
EhcReadOpReg (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32              Offset\r
  );\r
\r
\r
/**\r
  Write  the data to the EHCI operation register.\r
\r
  @param  Ehc      The EHCI device.\r
  @param  Offset   EHCI operation register offset.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
EhcWriteOpReg (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
\r
/**\r
  Add support for UEFI Over Legacy (UoL) feature, stop\r
  the legacy USB SMI support.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcClearLegacySupport (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
\r
/**\r
  Set door bell and wait it to be ACKed by host controller.\r
  This function is used to synchronize with the hardware.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  Synchronized with the hardware.\r
  @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.\r
\r
**/\r
EFI_STATUS\r
EhcSetAndWaitDoorBell (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits are Write-Clean.\r
\r
  @param  Ehc      The EHCI device.\r
\r
**/\r
VOID\r
EhcAckAllInterrupt (\r
  IN  USB2_HC_DEV         *Ehc\r
  );\r
\r
\r
\r
/**\r
  Whether Ehc is halted.\r
\r
  @param  Ehc     The EHCI device.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
EhcIsHalt (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Ehc      The EHCI device.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
EhcIsSysError (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
\r
/**\r
  Reset the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The host controller is reset.\r
  @return Others       Failed to reset the host.\r
\r
**/\r
EFI_STATUS\r
EhcResetHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
/**\r
  Halt the host controller.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is halt.\r
  @return EFI_TIMEOUT  Failed to halt the controller before Timeout.\r
\r
**/\r
EFI_STATUS\r
EhcHaltHC (\r
  IN USB2_HC_DEV         *Ehc,\r
  IN UINT32              Timeout\r
  );\r
\r
\r
/**\r
  Set the EHCI to run.\r
\r
  @param  Ehc          The EHCI device.\r
  @param  Timeout      Time to wait before abort.\r
\r
  @return EFI_SUCCESS  The EHCI is running.\r
  @return Others       Failed to set the EHCI to run.\r
\r
**/\r
EFI_STATUS\r
EhcRunHC (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN UINT32               Timeout\r
  );\r
\r
\r
\r
/**\r
  Initialize the HC hardware.\r
  EHCI spec lists the five things to do to initialize the hardware:\r
  1. Program CTRLDSSEGMENT\r
  2. Set USBINTR to enable interrupts\r
  3. Set periodic list base\r
  4. Set USBCMD, interrupt threshold, frame list size etc\r
  5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
\r
  @param  Ehc          The EHCI device.\r
\r
  @return EFI_SUCCESS  The EHCI has come out of halt state.\r
  @return EFI_TIMEOUT  Time out happened.\r
\r
**/\r
EFI_STATUS\r
EhcInitHC (\r
  IN USB2_HC_DEV          *Ehc\r
  );\r
\r
#endif\r
Commit	Line	Data
913cb9dc	1	/** @file\r
913cb9dc	2	\r
78c2ffb5	3	This file contains the definination for host controller register operation routines.\r
78c2ffb5	4	\r
597f4ee2	5	Copyright (c) 2007 - 2009, Intel Corporation\r
913cb9dc	6	All rights reserved. This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
913cb9dc	14	**/\r
	15	\r
	16	#ifndef _EFI_EHCI_REG_H_\r
	17	#define _EFI_EHCI_REG_H_\r
	18	\r
	19	\r
78c2ffb5	20	typedef enum {\r
913cb9dc	21	//\r
	22	// Capability register offset\r
	23	//\r
	24	EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset\r
	25	EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h\r
	26	EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset\r
	27	\r
	28	//\r
	29	// Capability register bit definition\r
	30	//\r
	31	HCSP_NPORTS = 0x0F, // Number of root hub port\r
	32	HCCP_64BIT = 0x01, // 64-bit addressing capability\r
	33	\r
	34	//\r
	35	// Operational register offset\r
	36	//\r
	37	EHC_USBCMD_OFFSET = 0x0, // USB command register offset\r
	38	EHC_USBSTS_OFFSET = 0x04, // Statue register offset\r
	39	EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset\r
	40	EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset\r
	41	EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset\r
	42	EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset\r
	43	EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset\r
	44	EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset\r
	45	EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset\r
	46	\r
	47	EHC_FRAME_LEN = 1024,\r
	48	\r
	49	//\r
	50	// Register bit definition\r
	51	//\r
	52	CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC\r
	53	\r
	54	USBCMD_RUN = 0x01, // Run/stop\r
	55	USBCMD_RESET = 0x02, // Start the host controller reset\r
	56	USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule\r
	57	USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule\r
	58	USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell\r
	59	\r
	60	USBSTS_IAA = 0x20, // Interrupt on async advance\r
	61	USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status\r
	62	USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status\r
	63	USBSTS_HALT = 0x1000, // Host controller halted\r
	64	USBSTS_SYS_ERROR = 0x10, // Host system error\r
	65	USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC\r
	66	// (write clean) bits in USBSTS register\r
	67	\r
	68	PORTSC_CONN = 0x01, // Current Connect Status\r
	69	PORTSC_CONN_CHANGE = 0x02, // Connect Status Change\r
	70	PORTSC_ENABLED = 0x04, // Port Enable / Disable\r
	71	PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change\r
	72	PORTSC_OVERCUR = 0x10, // Over current Active\r
	73	PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change\r
	74	PORSTSC_RESUME = 0x40, // Force Port Resume\r
	75	PORTSC_SUSPEND = 0x80, // Port Suspend State\r
	76	PORTSC_RESET = 0x100, // Port Reset\r
	77	PORTSC_LINESTATE_K = 0x400, // Line Status K-state\r
	78	PORTSC_LINESTATE_J = 0x800, // Line Status J-state\r
	79	PORTSC_POWER = 0x1000, // Port Power\r
	80	PORTSC_OWNER = 0x2000, // Port Owner\r
	81	PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,\r
	82	// they are WC (write clean)\r
	83	//\r
	84	// PCI Configuration Registers\r
85	//\r
c52fa98c	86	EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */\r
78c2ffb5	87	}EHCI_REGISTER_OFFSET;\r
913cb9dc	88	\r
	89	#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r
	90	\r
	91	#define EHC_ADDR(High, QhHw32) \\r
	92	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))\r
	93	\r
	94	#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r
	95	\r
	96	//\r
	97	// Structure to map the hardware port states to the\r
	98	// UEFI's port states.\r
	99	//\r
	100	typedef struct {\r
	101	UINT16 HwState;\r
	102	UINT16 UefiState;\r
	103	} USB_PORT_STATE_MAP;\r
	104	\r
	105	//\r
	106	// Ehci Data and Ctrl Structures\r
	107	//\r
	108	#pragma pack(1)\r
	109	typedef struct {\r
	110	UINT8 PI;\r
	111	UINT8 SubClassCode;\r
	112	UINT8 BaseCode;\r
	113	} USB_CLASSC;\r
	114	#pragma pack()\r
	115	\r
78c2ffb5	116	/**\r
	117	Read EHCI capability register.\r
	118	\r
	119	@param Ehc The EHCI device.\r
	120	@param Offset Capability register address.\r
	121	\r
	122	@return The register content.\r
913cb9dc	123	\r
78c2ffb5	124	**/\r
913cb9dc	125	UINT32\r
	126	EhcReadCapRegister (\r
	127	IN USB2_HC_DEV *Ehc,\r
	128	IN UINT32 Offset\r
ed66e1bc	129	);\r
913cb9dc	130	\r
	131	\r
	132	/**\r
78c2ffb5	133	Read EHCI Operation register.\r
913cb9dc	134	\r
78c2ffb5	135	@param Ehc The EHCI device.\r
78c2ffb5	136	@param Offset The operation register offset.\r
913cb9dc	137	\r
78c2ffb5	138	@return The register content.\r
913cb9dc	139	\r
	140	**/\r
	141	UINT32\r
	142	EhcReadOpReg (\r
	143	IN USB2_HC_DEV *Ehc,\r
	144	IN UINT32 Offset\r
ed66e1bc	145	);\r
913cb9dc	146	\r
	147	\r
	148	/**\r
78c2ffb5	149	Write the data to the EHCI operation register.\r
913cb9dc	150	\r
78c2ffb5	151	@param Ehc The EHCI device.\r
	152	@param Offset EHCI operation register offset.\r
	153	@param Data The data to write.\r
913cb9dc	154	\r
913cb9dc	155	**/\r
	156	VOID\r
	157	EhcWriteOpReg (\r
	158	IN USB2_HC_DEV *Ehc,\r
	159	IN UINT32 Offset,\r
	160	IN UINT32 Data\r
ed66e1bc	161	);\r
913cb9dc	162	\r
	163	\r
	164	/**\r
	165	Add support for UEFI Over Legacy (UoL) feature, stop\r
78c2ffb5	166	the legacy USB SMI support.\r
913cb9dc	167	\r
	168	@param Ehc The EHCI device.\r
	169	\r
913cb9dc	170	**/\r
	171	VOID\r
	172	EhcClearLegacySupport (\r
	173	IN USB2_HC_DEV *Ehc\r
ed66e1bc	174	);\r
913cb9dc	175	\r
	176	\r
	177	\r
	178	/**\r
	179	Set door bell and wait it to be ACKed by host controller.\r
	180	This function is used to synchronize with the hardware.\r
	181	\r
78c2ffb5	182	@param Ehc The EHCI device.\r
78c2ffb5	183	@param Timeout The time to wait before abort (in millisecond, ms).\r
913cb9dc	184	\r
78c2ffb5	185	@retval EFI_SUCCESS Synchronized with the hardware.\r
78c2ffb5	186	@retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r
913cb9dc	187	\r
	188	**/\r
	189	EFI_STATUS\r
	190	EhcSetAndWaitDoorBell (\r
	191	IN USB2_HC_DEV *Ehc,\r
	192	IN UINT32 Timeout\r
ed66e1bc	193	);\r
913cb9dc	194	\r
	195	\r
	196	/**\r
78c2ffb5	197	Clear all the interrutp status bits, these bits are Write-Clean.\r
913cb9dc	198	\r
78c2ffb5	199	@param Ehc The EHCI device.\r
913cb9dc	200	\r
913cb9dc	201	**/\r
	202	VOID\r
	203	EhcAckAllInterrupt (\r
	204	IN USB2_HC_DEV *Ehc\r
ed66e1bc	205	);\r
913cb9dc	206	\r
	207	\r
	208	\r
	209	/**\r
78c2ffb5	210	Whether Ehc is halted.\r
913cb9dc	211	\r
78c2ffb5	212	@param Ehc The EHCI device.\r
913cb9dc	213	\r
78c2ffb5	214	@retval TRUE The controller is halted.\r
78c2ffb5	215	@retval FALSE It isn't halted.\r
913cb9dc	216	\r
	217	**/\r
	218	BOOLEAN\r
	219	EhcIsHalt (\r
	220	IN USB2_HC_DEV *Ehc\r
ed66e1bc	221	);\r
913cb9dc	222	\r
	223	\r
	224	/**\r
78c2ffb5	225	Whether system error occurred.\r
913cb9dc	226	\r
78c2ffb5	227	@param Ehc The EHCI device.\r
913cb9dc	228	\r
78c2ffb5	229	@retval TRUE System error happened.\r
78c2ffb5	230	@retval FALSE No system error.\r
913cb9dc	231	\r
	232	**/\r
	233	BOOLEAN\r
	234	EhcIsSysError (\r
	235	IN USB2_HC_DEV *Ehc\r
ed66e1bc	236	);\r
913cb9dc	237	\r
913cb9dc	238	\r
913cb9dc	239	/**\r
78c2ffb5	240	Reset the host controller.\r
913cb9dc	241	\r
78c2ffb5	242	@param Ehc The EHCI device.\r
78c2ffb5	243	@param Timeout Time to wait before abort (in millisecond, ms).\r
913cb9dc	244	\r
78c2ffb5	245	@retval EFI_SUCCESS The host controller is reset.\r
78c2ffb5	246	@return Others Failed to reset the host.\r
913cb9dc	247	\r
	248	**/\r
	249	EFI_STATUS\r
	250	EhcResetHC (\r
	251	IN USB2_HC_DEV *Ehc,\r
	252	IN UINT32 Timeout\r
ed66e1bc	253	);\r
913cb9dc	254	\r
913cb9dc	255	\r
913cb9dc	256	/**\r
78c2ffb5	257	Halt the host controller.\r
913cb9dc	258	\r
78c2ffb5	259	@param Ehc The EHCI device.\r
78c2ffb5	260	@param Timeout Time to wait before abort.\r
913cb9dc	261	\r
78c2ffb5	262	@return EFI_SUCCESS The EHCI is halt.\r
78c2ffb5	263	@return EFI_TIMEOUT Failed to halt the controller before Timeout.\r
913cb9dc	264	\r
	265	**/\r
	266	EFI_STATUS\r
	267	EhcHaltHC (\r
	268	IN USB2_HC_DEV *Ehc,\r
	269	IN UINT32 Timeout\r
ed66e1bc	270	);\r
913cb9dc	271	\r
913cb9dc	272	\r
913cb9dc	273	/**\r
78c2ffb5	274	Set the EHCI to run.\r
913cb9dc	275	\r
78c2ffb5	276	@param Ehc The EHCI device.\r
78c2ffb5	277	@param Timeout Time to wait before abort.\r
913cb9dc	278	\r
78c2ffb5	279	@return EFI_SUCCESS The EHCI is running.\r
78c2ffb5	280	@return Others Failed to set the EHCI to run.\r
913cb9dc	281	\r
	282	**/\r
	283	EFI_STATUS\r
	284	EhcRunHC (\r
	285	IN USB2_HC_DEV *Ehc,\r
	286	IN UINT32 Timeout\r
ed66e1bc	287	);\r
913cb9dc	288	\r
	289	\r
	290	\r
	291	/**\r
	292	Initialize the HC hardware.\r
78c2ffb5	293	EHCI spec lists the five things to do to initialize the hardware:\r
913cb9dc	294	1. Program CTRLDSSEGMENT\r
	295	2. Set USBINTR to enable interrupts\r
	296	3. Set periodic list base\r
	297	4. Set USBCMD, interrupt threshold, frame list size etc\r
	298	5. Write 1 to CONFIGFLAG to route all ports to EHCI\r
	299	\r
78c2ffb5	300	@param Ehc The EHCI device.\r
913cb9dc	301	\r
78c2ffb5	302	@return EFI_SUCCESS The EHCI has come out of halt state.\r
78c2ffb5	303	@return EFI_TIMEOUT Time out happened.\r
913cb9dc	304	\r
	305	**/\r
	306	EFI_STATUS\r
	307	EhcInitHC (\r
	308	IN USB2_HC_DEV *Ehc\r
ed66e1bc	309	);\r
913cb9dc	310	\r
913cb9dc	311	#endif\r