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4b1bf81c | 1 | /** @file\r |
2 | PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid\r | |
3 | which is used to enable recovery function from USB Drivers.\r | |
4 | \r | |
23b0b155 | 5 | Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r |
4b1bf81c | 6 | \r |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions\r | |
9 | of the BSD License which accompanies this distribution. The\r | |
10 | full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #include "EhcPeim.h"\r | |
19 | \r | |
20 | //\r | |
21 | // Two arrays used to translate the EHCI port state (change)\r | |
22 | // to the UEFI protocol's port state (change).\r | |
23 | //\r | |
24 | USB_PORT_STATE_MAP mUsbPortStateMap[] = {\r | |
25 | {PORTSC_CONN, USB_PORT_STAT_CONNECTION},\r | |
26 | {PORTSC_ENABLED, USB_PORT_STAT_ENABLE},\r | |
27 | {PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND},\r | |
28 | {PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT},\r | |
29 | {PORTSC_RESET, USB_PORT_STAT_RESET},\r | |
30 | {PORTSC_POWER, USB_PORT_STAT_POWER},\r | |
31 | {PORTSC_OWNER, USB_PORT_STAT_OWNER}\r | |
32 | };\r | |
33 | \r | |
34 | USB_PORT_STATE_MAP mUsbPortChangeMap[] = {\r | |
35 | {PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION},\r | |
36 | {PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE},\r | |
37 | {PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT}\r | |
38 | };\r | |
39 | \r | |
40 | /**\r | |
41 | Read Ehc Operation register.\r | |
42 | \r | |
43 | @param Ehc The EHCI device.\r | |
44 | @param Offset The operation register offset.\r | |
45 | \r | |
46 | @retval the register content read.\r | |
47 | \r | |
48 | **/\r | |
49 | UINT32\r | |
50 | EhcReadOpReg (\r | |
51 | IN PEI_USB2_HC_DEV *Ehc,\r | |
52 | IN UINT32 Offset\r | |
53 | )\r | |
54 | {\r | |
55 | UINT32 Data;\r | |
56 | \r | |
57 | ASSERT (Ehc->CapLen != 0);\r | |
58 | \r | |
59 | Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset);\r | |
60 | \r | |
61 | return Data;\r | |
62 | }\r | |
63 | \r | |
64 | /**\r | |
65 | Write the data to the EHCI operation register.\r | |
66 | \r | |
67 | @param Ehc The EHCI device.\r | |
68 | @param Offset EHCI operation register offset.\r | |
69 | @param Data The data to write.\r | |
70 | \r | |
71 | **/\r | |
72 | VOID\r | |
73 | EhcWriteOpReg (\r | |
74 | IN PEI_USB2_HC_DEV *Ehc,\r | |
75 | IN UINT32 Offset,\r | |
76 | IN UINT32 Data\r | |
77 | )\r | |
78 | {\r | |
79 | \r | |
80 | ASSERT (Ehc->CapLen != 0);\r | |
81 | \r | |
82 | MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);\r | |
83 | \r | |
84 | }\r | |
85 | \r | |
86 | /**\r | |
87 | Set one bit of the operational register while keeping other bits.\r | |
88 | \r | |
89 | @param Ehc The EHCI device.\r | |
90 | @param Offset The offset of the operational register.\r | |
91 | @param Bit The bit mask of the register to set.\r | |
92 | \r | |
93 | **/\r | |
94 | VOID\r | |
95 | EhcSetOpRegBit (\r | |
96 | IN PEI_USB2_HC_DEV *Ehc,\r | |
97 | IN UINT32 Offset,\r | |
98 | IN UINT32 Bit\r | |
99 | )\r | |
100 | {\r | |
101 | UINT32 Data;\r | |
102 | \r | |
103 | Data = EhcReadOpReg (Ehc, Offset);\r | |
104 | Data |= Bit;\r | |
105 | EhcWriteOpReg (Ehc, Offset, Data);\r | |
106 | }\r | |
107 | \r | |
108 | /**\r | |
109 | Clear one bit of the operational register while keeping other bits.\r | |
110 | \r | |
111 | @param Ehc The EHCI device.\r | |
112 | @param Offset The offset of the operational register.\r | |
113 | @param Bit The bit mask of the register to clear.\r | |
114 | \r | |
115 | **/\r | |
116 | VOID\r | |
117 | EhcClearOpRegBit (\r | |
118 | IN PEI_USB2_HC_DEV *Ehc,\r | |
119 | IN UINT32 Offset,\r | |
120 | IN UINT32 Bit\r | |
121 | )\r | |
122 | {\r | |
123 | UINT32 Data;\r | |
124 | \r | |
125 | Data = EhcReadOpReg (Ehc, Offset);\r | |
126 | Data &= ~Bit;\r | |
127 | EhcWriteOpReg (Ehc, Offset, Data);\r | |
128 | }\r | |
129 | \r | |
130 | /**\r | |
131 | Wait the operation register's bit as specified by Bit \r | |
132 | to become set (or clear).\r | |
133 | \r | |
134 | @param Ehc The EHCI device.\r | |
135 | @param Offset The offset of the operational register.\r | |
136 | @param Bit The bit mask of the register to wait for.\r | |
137 | @param WaitToSet Wait the bit to set or clear.\r | |
138 | @param Timeout The time to wait before abort (in millisecond).\r | |
139 | \r | |
140 | @retval EFI_SUCCESS The bit successfully changed by host controller.\r | |
141 | @retval EFI_TIMEOUT The time out occurred.\r | |
142 | \r | |
143 | **/\r | |
144 | EFI_STATUS\r | |
145 | EhcWaitOpRegBit (\r | |
146 | IN PEI_USB2_HC_DEV *Ehc,\r | |
147 | IN UINT32 Offset,\r | |
148 | IN UINT32 Bit,\r | |
149 | IN BOOLEAN WaitToSet,\r | |
150 | IN UINT32 Timeout\r | |
151 | )\r | |
152 | {\r | |
153 | UINT32 Index;\r | |
154 | \r | |
155 | for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {\r | |
156 | if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {\r | |
157 | return EFI_SUCCESS;\r | |
158 | }\r | |
159 | \r | |
160 | MicroSecondDelay (EHC_SYNC_POLL_INTERVAL);\r | |
161 | }\r | |
162 | \r | |
163 | return EFI_TIMEOUT;\r | |
164 | }\r | |
165 | \r | |
166 | /**\r | |
167 | Read EHCI capability register.\r | |
168 | \r | |
169 | @param Ehc The EHCI device.\r | |
170 | @param Offset Capability register address.\r | |
171 | \r | |
172 | @retval the register content read.\r | |
173 | \r | |
174 | **/\r | |
175 | UINT32\r | |
176 | EhcReadCapRegister (\r | |
177 | IN PEI_USB2_HC_DEV *Ehc,\r | |
178 | IN UINT32 Offset\r | |
179 | )\r | |
180 | {\r | |
181 | UINT32 Data;\r | |
182 | \r | |
183 | Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset);\r | |
184 | \r | |
185 | return Data;\r | |
186 | }\r | |
187 | \r | |
188 | /**\r | |
189 | Set door bell and wait it to be ACKed by host controller.\r | |
190 | This function is used to synchronize with the hardware.\r | |
191 | \r | |
192 | @param Ehc The EHCI device.\r | |
193 | @param Timeout The time to wait before abort (in millisecond, ms).\r | |
194 | \r | |
195 | @retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r | |
196 | @retval EFI_SUCCESS Synchronized with the hardware.\r | |
197 | \r | |
198 | **/\r | |
199 | EFI_STATUS\r | |
200 | EhcSetAndWaitDoorBell (\r | |
201 | IN PEI_USB2_HC_DEV *Ehc,\r | |
202 | IN UINT32 Timeout\r | |
203 | )\r | |
204 | {\r | |
205 | EFI_STATUS Status;\r | |
206 | UINT32 Data;\r | |
207 | \r | |
208 | EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);\r | |
209 | \r | |
210 | Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_IAA, TRUE, Timeout);\r | |
211 | \r | |
212 | //\r | |
213 | // ACK the IAA bit in USBSTS register. Make sure other\r | |
214 | // interrupt bits are not ACKed. These bits are WC (Write Clean).\r | |
215 | //\r | |
216 | Data = EhcReadOpReg (Ehc, EHC_USBSTS_OFFSET);\r | |
217 | Data &= ~USBSTS_INTACK_MASK;\r | |
218 | Data |= USBSTS_IAA;\r | |
219 | \r | |
220 | EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, Data);\r | |
221 | \r | |
222 | return Status;\r | |
223 | }\r | |
224 | \r | |
225 | /**\r | |
226 | Clear all the interrutp status bits, these bits \r | |
227 | are Write-Clean.\r | |
228 | \r | |
229 | @param Ehc The EHCI device.\r | |
230 | \r | |
231 | **/\r | |
232 | VOID\r | |
233 | EhcAckAllInterrupt (\r | |
234 | IN PEI_USB2_HC_DEV *Ehc\r | |
235 | )\r | |
236 | {\r | |
237 | EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);\r | |
238 | }\r | |
239 | \r | |
240 | /**\r | |
241 | Enable the periodic schedule then wait EHC to \r | |
242 | actually enable it.\r | |
243 | \r | |
244 | @param Ehc The EHCI device.\r | |
245 | @param Timeout The time to wait before abort (in millisecond, ms).\r | |
246 | \r | |
247 | @retval EFI_TIMEOUT Time out happened while enabling periodic schedule.\r | |
248 | @retval EFI_SUCCESS The periodical schedule is enabled.\r | |
249 | \r | |
250 | **/\r | |
251 | EFI_STATUS\r | |
252 | EhcEnablePeriodSchd (\r | |
253 | IN PEI_USB2_HC_DEV *Ehc,\r | |
254 | IN UINT32 Timeout\r | |
255 | )\r | |
256 | {\r | |
257 | EFI_STATUS Status;\r | |
258 | \r | |
259 | EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);\r | |
260 | \r | |
261 | Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_PERIOD_ENABLED, TRUE, Timeout);\r | |
262 | return Status;\r | |
263 | }\r | |
264 | \r | |
265 | /**\r | |
266 | Enable asynchrounous schedule.\r | |
267 | \r | |
268 | @param Ehc The EHCI device.\r | |
269 | @param Timeout Time to wait before abort.\r | |
270 | \r | |
271 | @retval EFI_SUCCESS The EHCI asynchronous schedule is enabled.\r | |
272 | @retval Others Failed to enable the asynchronous scheudle.\r | |
273 | \r | |
274 | **/\r | |
275 | EFI_STATUS\r | |
276 | EhcEnableAsyncSchd (\r | |
277 | IN PEI_USB2_HC_DEV *Ehc,\r | |
278 | IN UINT32 Timeout\r | |
279 | )\r | |
280 | {\r | |
281 | EFI_STATUS Status;\r | |
282 | \r | |
283 | EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);\r | |
284 | \r | |
285 | Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_ASYNC_ENABLED, TRUE, Timeout);\r | |
286 | return Status;\r | |
287 | }\r | |
288 | \r | |
289 | /**\r | |
290 | Check whether Ehc is halted.\r | |
291 | \r | |
292 | @param Ehc The EHCI device.\r | |
293 | \r | |
294 | @retval TRUE The controller is halted.\r | |
295 | @retval FALSE The controller isn't halted.\r | |
296 | \r | |
297 | **/\r | |
298 | BOOLEAN\r | |
299 | EhcIsHalt (\r | |
300 | IN PEI_USB2_HC_DEV *Ehc\r | |
301 | )\r | |
302 | {\r | |
303 | return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);\r | |
304 | }\r | |
305 | \r | |
306 | /**\r | |
307 | Check whether system error occurred.\r | |
308 | \r | |
309 | @param Ehc The EHCI device.\r | |
310 | \r | |
311 | @retval TRUE System error happened.\r | |
312 | @retval FALSE No system error.\r | |
313 | \r | |
314 | **/\r | |
315 | BOOLEAN\r | |
316 | EhcIsSysError (\r | |
317 | IN PEI_USB2_HC_DEV *Ehc\r | |
318 | )\r | |
319 | {\r | |
320 | return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);\r | |
321 | }\r | |
322 | \r | |
323 | /**\r | |
324 | Reset the host controller.\r | |
325 | \r | |
326 | @param Ehc The EHCI device.\r | |
327 | @param Timeout Time to wait before abort (in millisecond, ms).\r | |
328 | \r | |
329 | @retval EFI_TIMEOUT The transfer failed due to time out.\r | |
330 | @retval Others Failed to reset the host.\r | |
331 | \r | |
332 | **/\r | |
333 | EFI_STATUS\r | |
334 | EhcResetHC (\r | |
335 | IN PEI_USB2_HC_DEV *Ehc,\r | |
336 | IN UINT32 Timeout\r | |
337 | )\r | |
338 | {\r | |
339 | EFI_STATUS Status;\r | |
340 | \r | |
341 | //\r | |
342 | // Host can only be reset when it is halt. If not so, halt it\r | |
343 | //\r | |
344 | if (!EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT)) {\r | |
345 | Status = EhcHaltHC (Ehc, Timeout);\r | |
346 | \r | |
347 | if (EFI_ERROR (Status)) {\r | |
348 | return Status;\r | |
349 | }\r | |
350 | }\r | |
351 | \r | |
352 | EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RESET);\r | |
353 | Status = EhcWaitOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RESET, FALSE, Timeout);\r | |
354 | return Status;\r | |
355 | }\r | |
356 | \r | |
357 | /**\r | |
358 | Halt the host controller.\r | |
359 | \r | |
360 | @param Ehc The EHCI device.\r | |
361 | @param Timeout Time to wait before abort.\r | |
362 | \r | |
363 | @retval EFI_TIMEOUT Failed to halt the controller before Timeout.\r | |
364 | @retval EFI_SUCCESS The EHCI is halt.\r | |
365 | \r | |
366 | **/\r | |
367 | EFI_STATUS\r | |
368 | EhcHaltHC (\r | |
369 | IN PEI_USB2_HC_DEV *Ehc,\r | |
370 | IN UINT32 Timeout\r | |
371 | )\r | |
372 | {\r | |
373 | EFI_STATUS Status;\r | |
374 | \r | |
375 | EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r | |
376 | Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);\r | |
377 | return Status;\r | |
378 | }\r | |
379 | \r | |
380 | /**\r | |
381 | Set the EHCI to run.\r | |
382 | \r | |
383 | @param Ehc The EHCI device.\r | |
384 | @param Timeout Time to wait before abort.\r | |
385 | \r | |
386 | @retval EFI_SUCCESS The EHCI is running.\r | |
387 | @retval Others Failed to set the EHCI to run.\r | |
388 | \r | |
389 | **/\r | |
390 | EFI_STATUS\r | |
391 | EhcRunHC (\r | |
392 | IN PEI_USB2_HC_DEV *Ehc,\r | |
393 | IN UINT32 Timeout\r | |
394 | )\r | |
395 | {\r | |
396 | EFI_STATUS Status;\r | |
397 | \r | |
398 | EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r | |
399 | Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);\r | |
400 | return Status;\r | |
401 | }\r | |
402 | \r | |
23b0b155 | 403 | /**\r |
404 | Power On All EHCI Ports.\r | |
405 | \r | |
406 | @param Ehc The EHCI device.\r | |
407 | \r | |
408 | **/\r | |
409 | VOID\r | |
410 | EhcPowerOnAllPorts (\r | |
411 | IN PEI_USB2_HC_DEV *Ehc\r | |
412 | )\r | |
413 | {\r | |
414 | UINT8 PortNumber;\r | |
415 | UINT8 Index;\r | |
416 | \r | |
417 | PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);\r | |
418 | for (Index = 0; Index < PortNumber; Index++) {\r | |
419 | EhcSetOpRegBit (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index, PORTSC_POWER);\r | |
420 | }\r | |
421 | }\r | |
422 | \r | |
4b1bf81c | 423 | /**\r |
424 | Initialize the HC hardware. \r | |
425 | EHCI spec lists the five things to do to initialize the hardware.\r | |
426 | 1. Program CTRLDSSEGMENT.\r | |
427 | 2. Set USBINTR to enable interrupts.\r | |
428 | 3. Set periodic list base.\r | |
429 | 4. Set USBCMD, interrupt threshold, frame list size etc.\r | |
430 | 5. Write 1 to CONFIGFLAG to route all ports to EHCI.\r | |
431 | \r | |
432 | @param Ehc The EHCI device.\r | |
433 | \r | |
434 | @retval EFI_SUCCESS The EHCI has come out of halt state.\r | |
435 | @retval EFI_TIMEOUT Time out happened.\r | |
436 | \r | |
437 | **/\r | |
438 | EFI_STATUS\r | |
439 | EhcInitHC (\r | |
440 | IN PEI_USB2_HC_DEV *Ehc\r | |
441 | )\r | |
442 | {\r | |
443 | EFI_STATUS Status;\r | |
444 | EFI_PHYSICAL_ADDRESS TempPtr;\r | |
445 | UINTN PageNumber;\r | |
446 | \r | |
447 | ASSERT (EhcIsHalt (Ehc));\r | |
448 | \r | |
449 | //\r | |
450 | // Allocate the periodic frame and associated memeory\r | |
451 | // management facilities if not already done.\r | |
452 | //\r | |
453 | if (Ehc->PeriodFrame != NULL) {\r | |
454 | EhcFreeSched (Ehc);\r | |
455 | }\r | |
456 | PageNumber = sizeof(PEI_URB)/PAGESIZE +1;\r | |
457 | Status = PeiServicesAllocatePages (\r | |
458 | EfiBootServicesCode,\r | |
459 | PageNumber,\r | |
460 | &TempPtr\r | |
461 | );\r | |
462 | Ehc->Urb = (PEI_URB *) ((UINTN) TempPtr);\r | |
463 | if (Ehc->Urb == NULL) {\r | |
464 | return Status;\r | |
465 | }\r | |
23b0b155 | 466 | \r |
467 | EhcPowerOnAllPorts (Ehc); \r | |
468 | MicroSecondDelay (EHC_ROOT_PORT_RECOVERY_STALL);\r | |
4b1bf81c | 469 | \r |
470 | Status = EhcInitSched (Ehc);\r | |
471 | \r | |
472 | if (EFI_ERROR (Status)) {\r | |
473 | return Status;\r | |
474 | }\r | |
475 | //\r | |
476 | // 1. Program the CTRLDSSEGMENT register with the high 32 bit addr\r | |
477 | //\r | |
478 | EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);\r | |
479 | \r | |
480 | //\r | |
481 | // 2. Clear USBINTR to disable all the interrupt. UEFI works by polling\r | |
482 | //\r | |
483 | EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r | |
484 | \r | |
485 | //\r | |
486 | // 3. Program periodic frame list, already done in EhcInitSched\r | |
487 | // 4. Start the Host Controller\r | |
488 | //\r | |
489 | EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r | |
490 | \r | |
491 | //\r | |
492 | // 5. Set all ports routing to EHC\r | |
493 | //\r | |
494 | EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r | |
495 | \r | |
496 | //\r | |
497 | // Wait roothub port power stable\r | |
498 | //\r | |
499 | MicroSecondDelay (EHC_ROOT_PORT_RECOVERY_STALL);\r | |
500 | \r | |
501 | Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r | |
502 | \r | |
503 | if (EFI_ERROR (Status)) {\r | |
504 | return Status;\r | |
505 | }\r | |
506 | \r | |
507 | Status = EhcEnableAsyncSchd (Ehc, EHC_GENERIC_TIMEOUT);\r | |
508 | \r | |
509 | if (EFI_ERROR (Status)) {\r | |
510 | return Status;\r | |
511 | }\r | |
512 | \r | |
513 | return EFI_SUCCESS;\r | |
514 | }\r | |
515 | \r | |
516 | /**\r | |
517 | Submits bulk transfer to a bulk endpoint of a USB device.\r | |
518 | \r | |
519 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
520 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
521 | @param DeviceAddress Target device address.\r | |
522 | @param EndPointAddress Endpoint number and its direction in bit 7.\r | |
523 | @param DeviceSpeed Device speed, Low speed device doesn't support \r | |
524 | bulk transfer.\r | |
525 | @param MaximumPacketLength Maximum packet size the endpoint is capable of \r | |
526 | sending or receiving.\r | |
527 | @param Data Array of pointers to the buffers of data to transmit \r | |
528 | from or receive into.\r | |
529 | @param DataLength The lenght of the data buffer.\r | |
530 | @param DataToggle On input, the initial data toggle for the transfer;\r | |
531 | On output, it is updated to to next data toggle to use of \r | |
532 | the subsequent bulk transfer.\r | |
533 | @param TimeOut Indicates the maximum time, in millisecond, which the\r | |
534 | transfer is allowed to complete.\r | |
535 | @param Translator A pointr to the transaction translator data. \r | |
536 | @param TransferResult A pointer to the detailed result information of the\r | |
537 | bulk transfer.\r | |
538 | \r | |
539 | @retval EFI_SUCCESS The transfer was completed successfully.\r | |
540 | @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r | |
541 | @retval EFI_INVALID_PARAMETER Parameters are invalid.\r | |
542 | @retval EFI_TIMEOUT The transfer failed due to timeout.\r | |
543 | @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r | |
544 | \r | |
545 | **/\r | |
546 | EFI_STATUS\r | |
547 | EFIAPI\r | |
548 | EhcBulkTransfer (\r | |
549 | IN EFI_PEI_SERVICES **PeiServices,\r | |
550 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
551 | IN UINT8 DeviceAddress,\r | |
552 | IN UINT8 EndPointAddress,\r | |
553 | IN UINT8 DeviceSpeed,\r | |
554 | IN UINTN MaximumPacketLength,\r | |
555 | IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],\r | |
556 | IN OUT UINTN *DataLength,\r | |
557 | IN OUT UINT8 *DataToggle,\r | |
558 | IN UINTN TimeOut,\r | |
559 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
560 | OUT UINT32 *TransferResult\r | |
561 | )\r | |
562 | {\r | |
563 | PEI_USB2_HC_DEV *Ehc;\r | |
564 | PEI_URB *Urb;\r | |
565 | EFI_STATUS Status;\r | |
566 | \r | |
567 | //\r | |
568 | // Validate the parameters\r | |
569 | //\r | |
570 | if ((DataLength == NULL) || (*DataLength == 0) || \r | |
571 | (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {\r | |
572 | return EFI_INVALID_PARAMETER;\r | |
573 | }\r | |
574 | \r | |
575 | if ((*DataToggle != 0) && (*DataToggle != 1)) {\r | |
576 | return EFI_INVALID_PARAMETER;\r | |
577 | }\r | |
578 | \r | |
579 | if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||\r | |
580 | ((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r | |
581 | ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {\r | |
582 | return EFI_INVALID_PARAMETER;\r | |
583 | }\r | |
584 | \r | |
585 | Ehc =PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);\r | |
586 | *TransferResult = EFI_USB_ERR_SYSTEM;\r | |
587 | Status = EFI_DEVICE_ERROR;\r | |
588 | \r | |
589 | if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {\r | |
590 | EhcAckAllInterrupt (Ehc);\r | |
591 | goto ON_EXIT;\r | |
592 | }\r | |
593 | \r | |
594 | EhcAckAllInterrupt (Ehc);\r | |
595 | \r | |
596 | //\r | |
597 | // Create a new URB, insert it into the asynchronous\r | |
598 | // schedule list, then poll the execution status.\r | |
599 | //\r | |
600 | Urb = EhcCreateUrb (\r | |
601 | Ehc,\r | |
602 | DeviceAddress,\r | |
603 | EndPointAddress,\r | |
604 | DeviceSpeed,\r | |
605 | *DataToggle,\r | |
606 | MaximumPacketLength,\r | |
607 | Translator,\r | |
608 | EHC_BULK_TRANSFER,\r | |
609 | NULL,\r | |
610 | Data[0],\r | |
611 | *DataLength,\r | |
612 | NULL,\r | |
613 | NULL,\r | |
614 | 1\r | |
615 | );\r | |
616 | \r | |
617 | if (Urb == NULL) {\r | |
618 | Status = EFI_OUT_OF_RESOURCES;\r | |
619 | goto ON_EXIT;\r | |
620 | }\r | |
621 | \r | |
622 | EhcLinkQhToAsync (Ehc, Urb->Qh);\r | |
623 | Status = EhcExecTransfer (Ehc, Urb, TimeOut);\r | |
624 | EhcUnlinkQhFromAsync (Ehc, Urb->Qh);\r | |
625 | \r | |
626 | *TransferResult = Urb->Result;\r | |
627 | *DataLength = Urb->Completed;\r | |
628 | *DataToggle = Urb->DataToggle;\r | |
629 | \r | |
630 | if (*TransferResult == EFI_USB_NOERROR) {\r | |
631 | Status = EFI_SUCCESS;\r | |
632 | }\r | |
633 | \r | |
634 | EhcAckAllInterrupt (Ehc);\r | |
635 | EhcFreeUrb (Ehc, Urb);\r | |
636 | \r | |
637 | ON_EXIT:\r | |
638 | return Status;\r | |
639 | }\r | |
640 | \r | |
641 | /**\r | |
642 | Retrieves the number of root hub ports.\r | |
643 | \r | |
644 | @param[in] PeiServices The pointer to the PEI Services Table.\r | |
645 | @param[in] This The pointer to this instance of the \r | |
646 | PEI_USB2_HOST_CONTROLLER_PPI.\r | |
647 | @param[out] PortNumber The pointer to the number of the root hub ports. \r | |
648 | \r | |
649 | @retval EFI_SUCCESS The port number was retrieved successfully.\r | |
650 | @retval EFI_INVALID_PARAMETER PortNumber is NULL.\r | |
651 | \r | |
652 | **/\r | |
653 | EFI_STATUS\r | |
654 | EFIAPI\r | |
655 | EhcGetRootHubPortNumber (\r | |
656 | IN EFI_PEI_SERVICES **PeiServices,\r | |
657 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
658 | OUT UINT8 *PortNumber\r | |
659 | )\r | |
660 | {\r | |
661 | \r | |
662 | PEI_USB2_HC_DEV *EhcDev;\r | |
663 | EhcDev = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r | |
664 | \r | |
665 | if (PortNumber == NULL) {\r | |
666 | return EFI_INVALID_PARAMETER;\r | |
667 | } \r | |
668 | \r | |
669 | *PortNumber = (UINT8)(EhcDev->HcStructParams & HCSP_NPORTS);\r | |
670 | return EFI_SUCCESS;\r | |
671 | \r | |
672 | }\r | |
673 | \r | |
674 | /**\r | |
675 | Clears a feature for the specified root hub port.\r | |
676 | \r | |
677 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
678 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
679 | @param PortNumber Specifies the root hub port whose feature\r | |
680 | is requested to be cleared.\r | |
681 | @param PortFeature Indicates the feature selector associated with the\r | |
682 | feature clear request.\r | |
683 | \r | |
684 | @retval EFI_SUCCESS The feature specified by PortFeature was cleared \r | |
685 | for the USB root hub port specified by PortNumber.\r | |
686 | @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r | |
687 | \r | |
688 | **/\r | |
689 | EFI_STATUS\r | |
690 | EFIAPI\r | |
691 | EhcClearRootHubPortFeature (\r | |
692 | IN EFI_PEI_SERVICES **PeiServices,\r | |
693 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
694 | IN UINT8 PortNumber,\r | |
695 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
696 | )\r | |
697 | {\r | |
698 | PEI_USB2_HC_DEV *Ehc;\r | |
699 | UINT32 Offset;\r | |
700 | UINT32 State;\r | |
701 | UINT32 TotalPort;\r | |
702 | EFI_STATUS Status;\r | |
703 | \r | |
704 | Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r | |
705 | Status = EFI_SUCCESS;\r | |
706 | \r | |
707 | TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);\r | |
708 | \r | |
709 | if (PortNumber >= TotalPort) {\r | |
710 | Status = EFI_INVALID_PARAMETER;\r | |
711 | goto ON_EXIT;\r | |
712 | }\r | |
713 | \r | |
714 | Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);\r | |
715 | State = EhcReadOpReg (Ehc, Offset);\r | |
716 | State &= ~PORTSC_CHANGE_MASK;\r | |
717 | \r | |
718 | switch (PortFeature) {\r | |
719 | case EfiUsbPortEnable:\r | |
720 | //\r | |
721 | // Clear PORT_ENABLE feature means disable port.\r | |
722 | //\r | |
723 | State &= ~PORTSC_ENABLED;\r | |
724 | EhcWriteOpReg (Ehc, Offset, State);\r | |
725 | break;\r | |
726 | \r | |
727 | case EfiUsbPortSuspend:\r | |
728 | //\r | |
729 | // A write of zero to this bit is ignored by the host\r | |
730 | // controller. The host controller will unconditionally\r | |
731 | // set this bit to a zero when:\r | |
732 | // 1. software sets the Forct Port Resume bit to a zero from a one.\r | |
733 | // 2. software sets the Port Reset bit to a one frome a zero.\r | |
734 | //\r | |
735 | State &= ~PORSTSC_RESUME;\r | |
736 | EhcWriteOpReg (Ehc, Offset, State);\r | |
737 | break;\r | |
738 | \r | |
739 | case EfiUsbPortReset:\r | |
740 | //\r | |
741 | // Clear PORT_RESET means clear the reset signal.\r | |
742 | //\r | |
743 | State &= ~PORTSC_RESET;\r | |
744 | EhcWriteOpReg (Ehc, Offset, State);\r | |
745 | break;\r | |
746 | \r | |
747 | case EfiUsbPortOwner:\r | |
748 | //\r | |
749 | // Clear port owner means this port owned by EHC\r | |
750 | //\r | |
751 | State &= ~PORTSC_OWNER;\r | |
752 | EhcWriteOpReg (Ehc, Offset, State);\r | |
753 | break;\r | |
754 | \r | |
755 | case EfiUsbPortConnectChange:\r | |
756 | //\r | |
757 | // Clear connect status change\r | |
758 | //\r | |
759 | State |= PORTSC_CONN_CHANGE;\r | |
760 | EhcWriteOpReg (Ehc, Offset, State);\r | |
761 | break;\r | |
762 | \r | |
763 | case EfiUsbPortEnableChange:\r | |
764 | //\r | |
765 | // Clear enable status change\r | |
766 | //\r | |
767 | State |= PORTSC_ENABLE_CHANGE;\r | |
768 | EhcWriteOpReg (Ehc, Offset, State);\r | |
769 | break;\r | |
770 | \r | |
771 | case EfiUsbPortOverCurrentChange:\r | |
772 | //\r | |
773 | // Clear PortOverCurrent change\r | |
774 | //\r | |
775 | State |= PORTSC_OVERCUR_CHANGE;\r | |
776 | EhcWriteOpReg (Ehc, Offset, State);\r | |
777 | break;\r | |
778 | \r | |
779 | case EfiUsbPortPower:\r | |
780 | case EfiUsbPortSuspendChange:\r | |
781 | case EfiUsbPortResetChange:\r | |
782 | //\r | |
783 | // Not supported or not related operation\r | |
784 | //\r | |
785 | break;\r | |
786 | \r | |
787 | default:\r | |
788 | Status = EFI_INVALID_PARAMETER;\r | |
789 | break;\r | |
790 | }\r | |
791 | \r | |
792 | ON_EXIT:\r | |
793 | return Status;\r | |
794 | }\r | |
795 | \r | |
796 | /**\r | |
797 | Sets a feature for the specified root hub port.\r | |
798 | \r | |
799 | @param PeiServices The pointer of EFI_PEI_SERVICES\r | |
800 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI\r | |
801 | @param PortNumber Root hub port to set.\r | |
802 | @param PortFeature Feature to set.\r | |
803 | \r | |
804 | @retval EFI_SUCCESS The feature specified by PortFeature was set.\r | |
805 | @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r | |
806 | @retval EFI_TIMEOUT The time out occurred.\r | |
807 | \r | |
808 | **/\r | |
809 | EFI_STATUS\r | |
810 | EFIAPI\r | |
811 | EhcSetRootHubPortFeature (\r | |
812 | IN EFI_PEI_SERVICES **PeiServices,\r | |
813 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
814 | IN UINT8 PortNumber,\r | |
815 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
816 | )\r | |
817 | {\r | |
818 | PEI_USB2_HC_DEV *Ehc;\r | |
819 | UINT32 Offset;\r | |
820 | UINT32 State;\r | |
821 | UINT32 TotalPort;\r | |
822 | EFI_STATUS Status;\r | |
823 | \r | |
824 | Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r | |
825 | Status = EFI_SUCCESS;\r | |
826 | \r | |
827 | TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);\r | |
828 | \r | |
829 | if (PortNumber >= TotalPort) {\r | |
830 | Status = EFI_INVALID_PARAMETER;\r | |
831 | goto ON_EXIT;\r | |
832 | }\r | |
833 | \r | |
834 | Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));\r | |
835 | State = EhcReadOpReg (Ehc, Offset);\r | |
836 | \r | |
837 | //\r | |
838 | // Mask off the port status change bits, these bits are\r | |
839 | // write clean bit\r | |
840 | //\r | |
841 | State &= ~PORTSC_CHANGE_MASK;\r | |
842 | \r | |
843 | switch (PortFeature) {\r | |
844 | case EfiUsbPortEnable:\r | |
845 | //\r | |
846 | // Sofeware can't set this bit, Port can only be enable by\r | |
847 | // EHCI as a part of the reset and enable\r | |
848 | //\r | |
849 | State |= PORTSC_ENABLED;\r | |
850 | EhcWriteOpReg (Ehc, Offset, State);\r | |
851 | break;\r | |
852 | \r | |
853 | case EfiUsbPortSuspend:\r | |
854 | State |= PORTSC_SUSPEND;\r | |
855 | EhcWriteOpReg (Ehc, Offset, State);\r | |
856 | break;\r | |
857 | \r | |
858 | case EfiUsbPortReset:\r | |
859 | //\r | |
860 | // Make sure Host Controller not halt before reset it\r | |
861 | //\r | |
862 | if (EhcIsHalt (Ehc)) {\r | |
863 | Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);\r | |
864 | \r | |
865 | if (EFI_ERROR (Status)) {\r | |
866 | break;\r | |
867 | }\r | |
868 | }\r | |
869 | \r | |
870 | //\r | |
871 | // Set one to PortReset bit must also set zero to PortEnable bit\r | |
872 | //\r | |
873 | State |= PORTSC_RESET;\r | |
874 | State &= ~PORTSC_ENABLED;\r | |
875 | EhcWriteOpReg (Ehc, Offset, State);\r | |
876 | break;\r | |
877 | \r | |
878 | case EfiUsbPortPower:\r | |
879 | //\r | |
880 | // Not supported, ignore the operation\r | |
881 | //\r | |
882 | Status = EFI_SUCCESS;\r | |
883 | break;\r | |
884 | \r | |
885 | case EfiUsbPortOwner:\r | |
886 | State |= PORTSC_OWNER;\r | |
887 | EhcWriteOpReg (Ehc, Offset, State);\r | |
888 | break;\r | |
889 | \r | |
890 | default:\r | |
891 | Status = EFI_INVALID_PARAMETER;\r | |
892 | }\r | |
893 | \r | |
894 | ON_EXIT:\r | |
895 | return Status;\r | |
896 | }\r | |
897 | \r | |
898 | /**\r | |
899 | Retrieves the current status of a USB root hub port.\r | |
900 | \r | |
901 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
902 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
903 | @param PortNumber The root hub port to retrieve the state from. \r | |
904 | @param PortStatus Variable to receive the port state.\r | |
905 | \r | |
906 | @retval EFI_SUCCESS The status of the USB root hub port specified.\r | |
907 | by PortNumber was returned in PortStatus.\r | |
908 | @retval EFI_INVALID_PARAMETER PortNumber is invalid.\r | |
909 | \r | |
910 | **/\r | |
911 | EFI_STATUS\r | |
912 | EFIAPI\r | |
913 | EhcGetRootHubPortStatus (\r | |
914 | IN EFI_PEI_SERVICES **PeiServices,\r | |
915 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
916 | IN UINT8 PortNumber,\r | |
917 | OUT EFI_USB_PORT_STATUS *PortStatus\r | |
918 | )\r | |
919 | {\r | |
920 | PEI_USB2_HC_DEV *Ehc;\r | |
921 | UINT32 Offset;\r | |
922 | UINT32 State;\r | |
923 | UINT32 TotalPort;\r | |
924 | UINTN Index;\r | |
925 | UINTN MapSize;\r | |
926 | EFI_STATUS Status;\r | |
927 | \r | |
928 | if (PortStatus == NULL) {\r | |
929 | return EFI_INVALID_PARAMETER;\r | |
930 | }\r | |
931 | \r | |
932 | Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);\r | |
933 | Status = EFI_SUCCESS;\r | |
934 | \r | |
935 | TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);\r | |
936 | \r | |
937 | if (PortNumber >= TotalPort) {\r | |
938 | Status = EFI_INVALID_PARAMETER;\r | |
939 | goto ON_EXIT;\r | |
940 | }\r | |
941 | \r | |
942 | Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));\r | |
943 | PortStatus->PortStatus = 0;\r | |
944 | PortStatus->PortChangeStatus = 0;\r | |
945 | \r | |
946 | State = EhcReadOpReg (Ehc, Offset);\r | |
947 | \r | |
948 | //\r | |
949 | // Identify device speed. If in K state, it is low speed.\r | |
950 | // If the port is enabled after reset, the device is of \r | |
951 | // high speed. The USB bus driver should retrieve the actual\r | |
952 | // port speed after reset. \r | |
953 | //\r | |
954 | if (EHC_BIT_IS_SET (State, PORTSC_LINESTATE_K)) {\r | |
955 | PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r | |
956 | \r | |
957 | } else if (EHC_BIT_IS_SET (State, PORTSC_ENABLED)) {\r | |
958 | PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r | |
959 | }\r | |
960 | \r | |
961 | //\r | |
962 | // Convert the EHCI port/port change state to UEFI status\r | |
963 | //\r | |
964 | MapSize = sizeof (mUsbPortStateMap) / sizeof (USB_PORT_STATE_MAP);\r | |
965 | \r | |
966 | for (Index = 0; Index < MapSize; Index++) {\r | |
967 | if (EHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {\r | |
968 | PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);\r | |
969 | }\r | |
970 | }\r | |
971 | \r | |
972 | MapSize = sizeof (mUsbPortChangeMap) / sizeof (USB_PORT_STATE_MAP);\r | |
973 | \r | |
974 | for (Index = 0; Index < MapSize; Index++) {\r | |
975 | if (EHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {\r | |
976 | PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);\r | |
977 | }\r | |
978 | }\r | |
979 | \r | |
980 | ON_EXIT:\r | |
981 | return Status;\r | |
982 | }\r | |
983 | \r | |
984 | /**\r | |
985 | Submits control transfer to a target USB device.\r | |
986 | \r | |
987 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
988 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
989 | @param DeviceAddress The target device address.\r | |
990 | @param DeviceSpeed Target device speed.\r | |
991 | @param MaximumPacketLength Maximum packet size the default control transfer \r | |
992 | endpoint is capable of sending or receiving.\r | |
993 | @param Request USB device request to send.\r | |
994 | @param TransferDirection Specifies the data direction for the data stage.\r | |
995 | @param Data Data buffer to be transmitted or received from USB device.\r | |
996 | @param DataLength The size (in bytes) of the data buffer.\r | |
997 | @param TimeOut Indicates the maximum timeout, in millisecond.\r | |
998 | @param Translator Transaction translator to be used by this device.\r | |
999 | @param TransferResult Return the result of this control transfer.\r | |
1000 | \r | |
1001 | @retval EFI_SUCCESS Transfer was completed successfully.\r | |
1002 | @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.\r | |
1003 | @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r | |
1004 | @retval EFI_TIMEOUT Transfer failed due to timeout.\r | |
1005 | @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.\r | |
1006 | \r | |
1007 | **/\r | |
1008 | EFI_STATUS\r | |
1009 | EFIAPI\r | |
1010 | EhcControlTransfer (\r | |
1011 | IN EFI_PEI_SERVICES **PeiServices,\r | |
1012 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
1013 | IN UINT8 DeviceAddress,\r | |
1014 | IN UINT8 DeviceSpeed,\r | |
1015 | IN UINTN MaximumPacketLength,\r | |
1016 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
1017 | IN EFI_USB_DATA_DIRECTION TransferDirection,\r | |
1018 | IN OUT VOID *Data,\r | |
1019 | IN OUT UINTN *DataLength,\r | |
1020 | IN UINTN TimeOut,\r | |
1021 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
1022 | OUT UINT32 *TransferResult\r | |
1023 | )\r | |
1024 | {\r | |
1025 | PEI_USB2_HC_DEV *Ehc;\r | |
1026 | PEI_URB *Urb;\r | |
1027 | UINT8 Endpoint;\r | |
1028 | EFI_STATUS Status;\r | |
1029 | \r | |
1030 | //\r | |
1031 | // Validate parameters\r | |
1032 | //\r | |
1033 | if ((Request == NULL) || (TransferResult == NULL)) {\r | |
1034 | return EFI_INVALID_PARAMETER;\r | |
1035 | }\r | |
1036 | \r | |
1037 | if ((TransferDirection != EfiUsbDataIn) &&\r | |
1038 | (TransferDirection != EfiUsbDataOut) &&\r | |
1039 | (TransferDirection != EfiUsbNoData)) {\r | |
1040 | return EFI_INVALID_PARAMETER;\r | |
1041 | }\r | |
1042 | \r | |
1043 | if ((TransferDirection == EfiUsbNoData) && \r | |
1044 | ((Data != NULL) || (*DataLength != 0))) {\r | |
1045 | return EFI_INVALID_PARAMETER;\r | |
1046 | }\r | |
1047 | \r | |
1048 | if ((TransferDirection != EfiUsbNoData) && \r | |
1049 | ((Data == NULL) || (*DataLength == 0))) {\r | |
1050 | return EFI_INVALID_PARAMETER;\r | |
1051 | }\r | |
1052 | \r | |
1053 | if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&\r | |
1054 | (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {\r | |
1055 | return EFI_INVALID_PARAMETER;\r | |
1056 | }\r | |
1057 | \r | |
1058 | \r | |
1059 | if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||\r | |
1060 | ((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r | |
1061 | ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {\r | |
1062 | return EFI_INVALID_PARAMETER;\r | |
1063 | }\r | |
1064 | \r | |
1065 | Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);\r | |
1066 | \r | |
1067 | Status = EFI_DEVICE_ERROR;\r | |
1068 | *TransferResult = EFI_USB_ERR_SYSTEM;\r | |
1069 | \r | |
1070 | if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {\r | |
1071 | EhcAckAllInterrupt (Ehc);\r | |
1072 | goto ON_EXIT;\r | |
1073 | }\r | |
1074 | \r | |
1075 | EhcAckAllInterrupt (Ehc);\r | |
1076 | \r | |
1077 | //\r | |
1078 | // Create a new URB, insert it into the asynchronous\r | |
1079 | // schedule list, then poll the execution status.\r | |
1080 | //\r | |
1081 | //\r | |
1082 | // Encode the direction in address, although default control\r | |
1083 | // endpoint is bidirectional. EhcCreateUrb expects this\r | |
1084 | // combination of Ep addr and its direction.\r | |
1085 | //\r | |
1086 | Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));\r | |
1087 | Urb = EhcCreateUrb (\r | |
1088 | Ehc,\r | |
1089 | DeviceAddress,\r | |
1090 | Endpoint,\r | |
1091 | DeviceSpeed,\r | |
1092 | 0,\r | |
1093 | MaximumPacketLength,\r | |
1094 | Translator,\r | |
1095 | EHC_CTRL_TRANSFER,\r | |
1096 | Request,\r | |
1097 | Data,\r | |
1098 | *DataLength,\r | |
1099 | NULL,\r | |
1100 | NULL,\r | |
1101 | 1\r | |
1102 | );\r | |
1103 | \r | |
1104 | if (Urb == NULL) {\r | |
1105 | Status = EFI_OUT_OF_RESOURCES;\r | |
1106 | goto ON_EXIT;\r | |
1107 | }\r | |
1108 | \r | |
1109 | EhcLinkQhToAsync (Ehc, Urb->Qh);\r | |
1110 | Status = EhcExecTransfer (Ehc, Urb, TimeOut);\r | |
1111 | EhcUnlinkQhFromAsync (Ehc, Urb->Qh);\r | |
1112 | \r | |
1113 | //\r | |
1114 | // Get the status from URB. The result is updated in EhcCheckUrbResult\r | |
1115 | // which is called by EhcExecTransfer\r | |
1116 | //\r | |
1117 | *TransferResult = Urb->Result;\r | |
1118 | *DataLength = Urb->Completed;\r | |
1119 | \r | |
1120 | if (*TransferResult == EFI_USB_NOERROR) {\r | |
1121 | Status = EFI_SUCCESS;\r | |
1122 | }\r | |
1123 | \r | |
1124 | EhcAckAllInterrupt (Ehc);\r | |
1125 | EhcFreeUrb (Ehc, Urb);\r | |
1126 | \r | |
1127 | ON_EXIT:\r | |
1128 | return Status;\r | |
1129 | }\r | |
1130 | \r | |
1131 | /**\r | |
1132 | @param FileHandle Handle of the file being invoked.\r | |
1133 | @param PeiServices Describes the list of possible PEI Services.\r | |
1134 | \r | |
1135 | @retval EFI_SUCCESS PPI successfully installed.\r | |
1136 | \r | |
1137 | **/\r | |
1138 | EFI_STATUS\r | |
1139 | EFIAPI\r | |
1140 | EhcPeimEntry (\r | |
1141 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
1142 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
1143 | )\r | |
1144 | {\r | |
1145 | PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;\r | |
1146 | EFI_STATUS Status;\r | |
1147 | UINT8 Index;\r | |
1148 | UINTN ControllerType;\r | |
1149 | UINTN BaseAddress;\r | |
1150 | UINTN MemPages;\r | |
1151 | PEI_USB2_HC_DEV *EhcDev;\r | |
1152 | EFI_PHYSICAL_ADDRESS TempPtr;\r | |
1153 | \r | |
1154 | //\r | |
1155 | // Shadow this PEIM to run from memory\r | |
1156 | //\r | |
1157 | if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {\r | |
1158 | return EFI_SUCCESS;\r | |
1159 | }\r | |
1160 | \r | |
1161 | Status = PeiServicesLocatePpi (\r | |
1162 | &gPeiUsbControllerPpiGuid,\r | |
1163 | 0,\r | |
1164 | NULL,\r | |
1165 | (VOID **) &ChipSetUsbControllerPpi\r | |
1166 | );\r | |
1167 | if (EFI_ERROR (Status)) {\r | |
1168 | return EFI_UNSUPPORTED;\r | |
1169 | }\r | |
1170 | \r | |
1171 | Index = 0;\r | |
1172 | while (TRUE) {\r | |
1173 | Status = ChipSetUsbControllerPpi->GetUsbController (\r | |
1174 | (EFI_PEI_SERVICES **) PeiServices,\r | |
1175 | ChipSetUsbControllerPpi,\r | |
1176 | Index,\r | |
1177 | &ControllerType,\r | |
1178 | &BaseAddress\r | |
1179 | );\r | |
1180 | //\r | |
1181 | // When status is error, meant no controller is found\r | |
1182 | //\r | |
1183 | if (EFI_ERROR (Status)) {\r | |
1184 | break;\r | |
1185 | }\r | |
1186 | \r | |
1187 | //\r | |
1188 | // This PEIM is for UHC type controller.\r | |
1189 | //\r | |
1190 | if (ControllerType != PEI_EHCI_CONTROLLER) {\r | |
1191 | Index++;\r | |
1192 | continue;\r | |
1193 | }\r | |
1194 | \r | |
1195 | MemPages = sizeof (PEI_USB2_HC_DEV) / PAGESIZE + 1;\r | |
1196 | Status = PeiServicesAllocatePages (\r | |
1197 | EfiBootServicesCode,\r | |
1198 | MemPages,\r | |
1199 | &TempPtr\r | |
1200 | );\r | |
1201 | if (EFI_ERROR (Status)) {\r | |
1202 | return EFI_OUT_OF_RESOURCES;\r | |
1203 | }\r | |
1204 | \r | |
1205 | ZeroMem((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);\r | |
1206 | EhcDev = (PEI_USB2_HC_DEV *) ((UINTN) TempPtr);\r | |
1207 | \r | |
1208 | EhcDev->Signature = USB2_HC_DEV_SIGNATURE;\r | |
1209 | \r | |
1210 | EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;\r | |
1211 | \r | |
1212 | \r | |
1213 | EhcDev->HcStructParams = EhcReadCapRegister (EhcDev, EHC_HCSPARAMS_OFFSET);\r | |
1214 | EhcDev->HcCapParams = EhcReadCapRegister (EhcDev, EHC_HCCPARAMS_OFFSET);\r | |
1215 | EhcDev->CapLen = EhcReadCapRegister (EhcDev, EHC_CAPLENGTH_OFFSET) & 0x0FF;\r | |
1216 | //\r | |
1217 | // Initialize Uhc's hardware\r | |
1218 | //\r | |
1219 | Status = InitializeUsbHC (EhcDev);\r | |
1220 | if (EFI_ERROR (Status)) {\r | |
1221 | return Status;\r | |
1222 | }\r | |
1223 | \r | |
1224 | EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;\r | |
1225 | EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;\r | |
1226 | EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;\r | |
1227 | EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;\r | |
1228 | EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;\r | |
1229 | EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;\r | |
1230 | \r | |
1231 | EhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r | |
1232 | EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;\r | |
1233 | EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;\r | |
1234 | \r | |
1235 | Status = PeiServicesInstallPpi (&EhcDev->PpiDescriptor);\r | |
1236 | if (EFI_ERROR (Status)) {\r | |
1237 | Index++;\r | |
1238 | continue;\r | |
1239 | }\r | |
1240 | \r | |
1241 | Index++;\r | |
1242 | }\r | |
1243 | \r | |
1244 | return EFI_SUCCESS;\r | |
1245 | }\r | |
1246 | \r | |
1247 | /**\r | |
1248 | @param EhcDev EHCI Device.\r | |
1249 | \r | |
1250 | @retval EFI_SUCCESS EHCI successfully initialized.\r | |
1251 | @retval EFI_ABORTED EHCI was failed to be initialized.\r | |
1252 | \r | |
1253 | **/\r | |
1254 | EFI_STATUS\r | |
1255 | InitializeUsbHC (\r | |
1256 | IN PEI_USB2_HC_DEV *EhcDev \r | |
1257 | )\r | |
1258 | {\r | |
1259 | EFI_STATUS Status;\r | |
1260 | \r | |
1261 | \r | |
1262 | EhcResetHC (EhcDev, EHC_RESET_TIMEOUT);\r | |
1263 | \r | |
1264 | Status = EhcInitHC (EhcDev);\r | |
1265 | \r | |
1266 | if (EFI_ERROR (Status)) {\r | |
1267 | return EFI_ABORTED; \r | |
1268 | }\r | |
1269 | \r | |
1270 | return EFI_SUCCESS;\r | |
1271 | }\r |