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4b1bf81c | 1 | /** @file\r |
2 | Private Header file for Usb Host Controller PEIM\r | |
3 | \r | |
d1102dba LG |
4 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
5 | \r | |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4b1bf81c | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef _EFI_EHCI_URB_H_\r | |
11 | #define _EFI_EHCI_URB_H_\r | |
12 | \r | |
13 | typedef struct _PEI_EHC_QTD PEI_EHC_QTD;\r | |
14 | typedef struct _PEI_EHC_QH PEI_EHC_QH;\r | |
15 | typedef struct _PEI_URB PEI_URB;\r | |
16 | \r | |
17 | #define EHC_CTRL_TRANSFER 0x01\r | |
18 | #define EHC_BULK_TRANSFER 0x02\r | |
19 | #define EHC_INT_TRANSFER_SYNC 0x04\r | |
20 | #define EHC_INT_TRANSFER_ASYNC 0x08\r | |
21 | \r | |
22 | #define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')\r | |
23 | #define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')\r | |
24 | #define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r | |
25 | \r | |
26 | //\r | |
27 | // Hardware related bit definitions\r | |
28 | //\r | |
29 | #define EHC_TYPE_ITD 0x00\r | |
30 | #define EHC_TYPE_QH 0x02\r | |
31 | #define EHC_TYPE_SITD 0x04\r | |
32 | #define EHC_TYPE_FSTN 0x06\r | |
33 | \r | |
34 | #define QH_NAK_RELOAD 3\r | |
35 | #define QH_HSHBW_MULTI 1\r | |
36 | \r | |
37 | #define QTD_MAX_ERR 3\r | |
38 | #define QTD_PID_OUTPUT 0x00\r | |
39 | #define QTD_PID_INPUT 0x01\r | |
40 | #define QTD_PID_SETUP 0x02\r | |
41 | \r | |
42 | #define QTD_STAT_DO_OUT 0\r | |
43 | #define QTD_STAT_DO_SS 0\r | |
44 | #define QTD_STAT_DO_PING 0x01\r | |
45 | #define QTD_STAT_DO_CS 0x02\r | |
46 | #define QTD_STAT_TRANS_ERR 0x08\r | |
47 | #define QTD_STAT_BABBLE_ERR 0x10\r | |
48 | #define QTD_STAT_BUFF_ERR 0x20\r | |
49 | #define QTD_STAT_HALTED 0x40\r | |
50 | #define QTD_STAT_ACTIVE 0x80\r | |
51 | #define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)\r | |
52 | \r | |
53 | #define QTD_MAX_BUFFER 4\r | |
54 | #define QTD_BUF_LEN 4096\r | |
55 | #define QTD_BUF_MASK 0x0FFF\r | |
56 | \r | |
57 | #define QH_MICROFRAME_0 0x01\r | |
58 | #define QH_MICROFRAME_1 0x02\r | |
59 | #define QH_MICROFRAME_2 0x04\r | |
60 | #define QH_MICROFRAME_3 0x08\r | |
61 | #define QH_MICROFRAME_4 0x10\r | |
62 | #define QH_MICROFRAME_5 0x20\r | |
63 | #define QH_MICROFRAME_6 0x40\r | |
64 | #define QH_MICROFRAME_7 0x80\r | |
65 | \r | |
66 | #define USB_ERR_SHORT_PACKET 0x200\r | |
67 | \r | |
68 | //\r | |
d1102dba | 69 | // Fill in the hardware link point: pass in a EHC_QH/QH_HW\r |
4b1bf81c | 70 | // pointer to QH_LINK; A EHC_QTD/QTD_HW pointer to QTD_LINK\r |
71 | //\r | |
72 | #define QH_LINK(Addr, Type, Term) \\r | |
73 | ((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))\r | |
74 | \r | |
75 | #define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))\r | |
76 | \r | |
77 | //\r | |
d1102dba LG |
78 | // The defination of EHCI hardware used data structure for\r |
79 | // little endian architecture. The QTD and QH structures\r | |
80 | // are required to be 32 bytes aligned. Don't add members\r | |
4b1bf81c | 81 | // to the head of the associated software strucuture.\r |
82 | //\r | |
83 | #pragma pack(1)\r | |
84 | typedef struct {\r | |
85 | UINT32 NextQtd;\r | |
86 | UINT32 AltNext;\r | |
d1102dba | 87 | \r |
4b1bf81c | 88 | UINT32 Status : 8;\r |
89 | UINT32 Pid : 2;\r | |
90 | UINT32 ErrCnt : 2;\r | |
91 | UINT32 CurPage : 3;\r | |
92 | UINT32 Ioc : 1;\r | |
93 | UINT32 TotalBytes : 15;\r | |
94 | UINT32 DataToggle : 1;\r | |
95 | \r | |
96 | UINT32 Page[5];\r | |
97 | UINT32 PageHigh[5];\r | |
98 | } QTD_HW;\r | |
99 | \r | |
100 | typedef struct {\r | |
d1102dba | 101 | UINT32 HorizonLink;\r |
4b1bf81c | 102 | //\r |
103 | // Endpoint capabilities/Characteristics DWord 1 and DWord 2\r | |
104 | //\r | |
105 | UINT32 DeviceAddr : 7;\r | |
106 | UINT32 Inactive : 1;\r | |
107 | UINT32 EpNum : 4;\r | |
108 | UINT32 EpSpeed : 2;\r | |
109 | UINT32 DtCtrl : 1;\r | |
110 | UINT32 ReclaimHead : 1;\r | |
111 | UINT32 MaxPacketLen : 11;\r | |
112 | UINT32 CtrlEp : 1;\r | |
113 | UINT32 NakReload : 4;\r | |
114 | \r | |
115 | UINT32 SMask : 8;\r | |
116 | UINT32 CMask : 8;\r | |
117 | UINT32 HubAddr : 7;\r | |
118 | UINT32 PortNum : 7;\r | |
119 | UINT32 Multiplier : 2;\r | |
120 | \r | |
121 | //\r | |
122 | // Transaction execution overlay area\r | |
123 | //\r | |
124 | UINT32 CurQtd;\r | |
125 | UINT32 NextQtd;\r | |
126 | UINT32 AltQtd;\r | |
d1102dba | 127 | \r |
4b1bf81c | 128 | UINT32 Status : 8;\r |
129 | UINT32 Pid : 2;\r | |
130 | UINT32 ErrCnt : 2;\r | |
131 | UINT32 CurPage : 3;\r | |
132 | UINT32 Ioc : 1;\r | |
133 | UINT32 TotalBytes : 15;\r | |
134 | UINT32 DataToggle : 1;\r | |
135 | \r | |
136 | UINT32 Page[5];\r | |
137 | UINT32 PageHigh[5];\r | |
138 | } QH_HW;\r | |
139 | #pragma pack()\r | |
140 | \r | |
141 | \r | |
142 | //\r | |
143 | // Endpoint address and its capabilities\r | |
144 | //\r | |
145 | typedef struct _USB_ENDPOINT {\r | |
146 | UINT8 DevAddr;\r | |
147 | UINT8 EpAddr; // Endpoint address, no direction encoded in\r | |
148 | EFI_USB_DATA_DIRECTION Direction;\r | |
149 | UINT8 DevSpeed;\r | |
150 | UINTN MaxPacket;\r | |
151 | UINT8 HubAddr;\r | |
152 | UINT8 HubPort;\r | |
153 | UINT8 Toggle; // Data toggle, not used for control transfer\r | |
154 | UINTN Type;\r | |
155 | UINTN PollRate; // Polling interval used by EHCI\r | |
156 | } USB_ENDPOINT;\r | |
157 | \r | |
158 | //\r | |
d1102dba | 159 | // Software QTD strcture, this is used to manage all the\r |
4b1bf81c | 160 | // QTD generated from a URB. Don't add fields before QtdHw.\r |
161 | //\r | |
162 | struct _PEI_EHC_QTD {\r | |
163 | QTD_HW QtdHw;\r | |
164 | UINT32 Signature;\r | |
165 | EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point\r | |
166 | UINT8 *Data; // Buffer of the original data\r | |
167 | UINTN DataLen; // Original amount of data in this QTD\r | |
168 | };\r | |
169 | \r | |
170 | \r | |
171 | \r | |
172 | //\r | |
d1102dba LG |
173 | // Software QH structure. All three different transaction types\r |
174 | // supported by UEFI USB, that is the control/bulk/interrupt\r | |
175 | // transfers use the queue head and queue token strcuture.\r | |
4b1bf81c | 176 | //\r |
177 | // Interrupt QHs are linked to periodic frame list in the reversed\r | |
d1102dba | 178 | // 2^N tree. Each interrupt QH is linked to the list starting at\r |
4b1bf81c | 179 | // frame 0. There is a dummy interrupt QH linked to each frame as\r |
180 | // a sentinental whose polling interval is 1. Synchronous interrupt\r | |
d1102dba LG |
181 | // transfer is linked after this dummy QH.\r |
182 | //\r | |
183 | // For control/bulk transfer, only synchronous (in the sense of UEFI)\r | |
4b1bf81c | 184 | // transfer is supported. A dummy QH is linked to EHCI AsyncListAddr\r |
185 | // as the reclamation header. New transfer is inserted after this QH.\r | |
186 | //\r | |
187 | struct _PEI_EHC_QH {\r | |
188 | QH_HW QhHw;\r | |
189 | UINT32 Signature;\r | |
190 | PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link\r | |
191 | EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head\r | |
d1102dba | 192 | UINTN Interval;\r |
4b1bf81c | 193 | };\r |
194 | \r | |
195 | //\r | |
d1102dba | 196 | // URB (Usb Request Block) contains information for all kinds of\r |
4b1bf81c | 197 | // usb requests.\r |
198 | //\r | |
199 | struct _PEI_URB {\r | |
200 | UINT32 Signature;\r | |
201 | EFI_LIST_ENTRY UrbList;\r | |
d1102dba | 202 | \r |
4b1bf81c | 203 | //\r |
204 | // Transaction information\r | |
205 | //\r | |
206 | USB_ENDPOINT Ep;\r | |
207 | EFI_USB_DEVICE_REQUEST *Request; // Control transfer only\r | |
208 | VOID *RequestPhy; // Address of the mapped request\r | |
209 | VOID *RequestMap;\r | |
210 | VOID *Data;\r | |
211 | UINTN DataLen;\r | |
212 | VOID *DataPhy; // Address of the mapped user data\r | |
213 | VOID *DataMap;\r | |
d1102dba | 214 | EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r |
4b1bf81c | 215 | VOID *Context;\r |
216 | \r | |
217 | //\r | |
218 | // Schedule data\r | |
219 | //\r | |
220 | PEI_EHC_QH *Qh;\r | |
d1102dba | 221 | \r |
4b1bf81c | 222 | //\r |
223 | // Transaction result\r | |
224 | //\r | |
225 | UINT32 Result;\r | |
226 | UINTN Completed; // completed data length\r | |
227 | UINT8 DataToggle;\r | |
228 | };\r | |
229 | \r | |
230 | /**\r | |
231 | Delete a single asynchronous interrupt transfer for\r | |
232 | the device and endpoint.\r | |
d1102dba | 233 | \r |
4b1bf81c | 234 | @param Ehc The EHCI device.\r |
235 | @param Data Current data not associated with a QTD.\r | |
236 | @param DataLen The length of the data.\r | |
237 | @param PktId Packet ID to use in the QTD.\r | |
238 | @param Toggle Data toggle to use in the QTD.\r | |
239 | @param MaxPacket Maximu packet length of the endpoint.\r | |
240 | \r | |
241 | @retval the pointer to the created QTD or NULL if failed to create one.\r | |
242 | \r | |
243 | **/\r | |
244 | PEI_EHC_QTD *\r | |
245 | EhcCreateQtd (\r | |
246 | IN PEI_USB2_HC_DEV *Ehc,\r | |
247 | IN UINT8 *Data,\r | |
248 | IN UINTN DataLen,\r | |
249 | IN UINT8 PktId,\r | |
250 | IN UINT8 Toggle,\r | |
251 | IN UINTN MaxPacket\r | |
252 | )\r | |
253 | ;\r | |
254 | \r | |
255 | /**\r | |
256 | Allocate and initialize a EHCI queue head.\r | |
d1102dba | 257 | \r |
4b1bf81c | 258 | @param Ehci The EHCI device.\r |
259 | @param Ep The endpoint to create queue head for.\r | |
260 | \r | |
261 | @retval the pointer to the created queue head or NULL if failed to create one.\r | |
262 | \r | |
263 | **/\r | |
264 | PEI_EHC_QH *\r | |
265 | EhcCreateQh (\r | |
266 | IN PEI_USB2_HC_DEV *Ehci,\r | |
267 | IN USB_ENDPOINT *Ep\r | |
268 | )\r | |
269 | ;\r | |
270 | \r | |
271 | /**\r | |
272 | Free an allocated URB. It is possible for it to be partially inited.\r | |
d1102dba | 273 | \r |
4b1bf81c | 274 | @param Ehc The EHCI device.\r |
275 | @param Urb The URB to free.\r | |
276 | \r | |
277 | **/\r | |
278 | VOID\r | |
279 | EhcFreeUrb (\r | |
280 | IN PEI_USB2_HC_DEV *Ehc,\r | |
281 | IN PEI_URB *Urb\r | |
282 | )\r | |
283 | ;\r | |
284 | \r | |
285 | /**\r | |
286 | Create a new URB and its associated QTD.\r | |
d1102dba | 287 | \r |
4b1bf81c | 288 | @param Ehc The EHCI device.\r |
289 | @param DevAddr The device address.\r | |
290 | @param EpAddr Endpoint addrress & its direction.\r | |
291 | @param DevSpeed The device speed.\r | |
292 | @param Toggle Initial data toggle to use.\r | |
293 | @param MaxPacket The max packet length of the endpoint.\r | |
294 | @param Hub The transaction translator to use.\r | |
295 | @param Type The transaction type.\r | |
296 | @param Request The standard USB request for control transfer.\r | |
297 | @param Data The user data to transfer.\r | |
298 | @param DataLen The length of data buffer.\r | |
299 | @param Callback The function to call when data is transferred.\r | |
300 | @param Context The context to the callback.\r | |
301 | @param Interval The interval for interrupt transfer.\r | |
302 | \r | |
303 | @retval the pointer to the created URB or NULL.\r | |
304 | \r | |
305 | **/\r | |
306 | PEI_URB *\r | |
307 | EhcCreateUrb (\r | |
308 | IN PEI_USB2_HC_DEV *Ehc,\r | |
309 | IN UINT8 DevAddr,\r | |
d1102dba | 310 | IN UINT8 EpAddr,\r |
4b1bf81c | 311 | IN UINT8 DevSpeed,\r |
312 | IN UINT8 Toggle,\r | |
313 | IN UINTN MaxPacket,\r | |
314 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,\r | |
315 | IN UINTN Type,\r | |
316 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
317 | IN VOID *Data,\r | |
318 | IN UINTN DataLen,\r | |
319 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r | |
320 | IN VOID *Context,\r | |
321 | IN UINTN Interval\r | |
322 | )\r | |
323 | ;\r | |
324 | #endif\r |