[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressPei / NvmExpressPeiHci.h

/** @file\r
  The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
  which follows NVM Express specification at PEI phase.\r
\r
  Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions\r
  of the BSD License which accompanies this distribution.  The\r
  full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _NVM_EXPRESS_PEI_HCI_H_\r
#define _NVM_EXPRESS_PEI_HCI_H_\r
\r
//\r
// NVME host controller registers operation definitions\r
//\r
#define NVME_GET_CAP(Private, Cap)             NvmeMmioRead  (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))\r
#define NVME_GET_CC(Private, Cc)               NvmeMmioRead  (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))\r
#define NVME_SET_CC(Private, Cc)               NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))\r
#define NVME_GET_CSTS(Private, Csts)           NvmeMmioRead  (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))\r
#define NVME_GET_AQA(Private, Aqa)             NvmeMmioRead  (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))\r
#define NVME_SET_AQA(Private, Aqa)             NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))\r
#define NVME_GET_ASQ(Private, Asq)             NvmeMmioRead  (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))\r
#define NVME_SET_ASQ(Private, Asq)             NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))\r
#define NVME_GET_ACQ(Private, Acq)             NvmeMmioRead  (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))\r
#define NVME_SET_ACQ(Private, Acq)             NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))\r
#define NVME_GET_VER(Private, Ver)             NvmeMmioRead  (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))\r
#define NVME_SET_SQTDBL(Private, Qid, Sqtdbl)  NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))\r
#define NVME_SET_CQHDBL(Private, Qid, Cqhdbl)  NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))\r
\r
//\r
// Base memory address enum types\r
//\r
enum {\r
  BASEMEM_ASQ,\r
  BASEMEM_ACQ,\r
  BASEMEM_SQ,\r
  BASEMEM_CQ,\r
  BASEMEM_PRP,\r
  MAX_BASEMEM_COUNT\r
};\r
\r
//\r
// All of base memories are 4K(0x1000) alignment\r
//\r
#define ALIGN(v, a)                          (UINTN)((((v) - 1) | ((a) - 1)) + 1)\r
#define NVME_MEM_BASE(Private)               ((UINTN)(Private->Buffer))\r
#define NVME_ASQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_ACQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_SQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_CQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
#define NVME_PRP_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
\r
\r
/**\r
  Transfer MMIO Data to memory.\r
\r
  @param[in,out] MemBuffer    Destination: Memory address.\r
  @param[in] MmioAddr         Source: MMIO address.\r
  @param[in] Size             Size for read.\r
\r
  @retval EFI_SUCCESS         MMIO read sucessfully.\r
\r
**/\r
EFI_STATUS\r
NvmeMmioRead (\r
  IN OUT VOID *MemBuffer,\r
  IN     UINTN MmioAddr,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Transfer memory data to MMIO.\r
\r
  @param[in,out] MmioAddr    Destination: MMIO address.\r
  @param[in] MemBuffer       Source: Memory address.\r
  @param[in] Size            Size for write.\r
\r
  @retval EFI_SUCCESS        MMIO write sucessfully.\r
\r
**/\r
EFI_STATUS\r
NvmeMmioWrite (\r
  IN OUT UINTN MmioAddr,\r
  IN     VOID *MemBuffer,\r
  IN     UINTN Size\r
  );\r
\r
/**\r
  Get the page offset for specific NVME based memory.\r
\r
  @param[in] BaseMemIndex    The Index of BaseMem (0-based).\r
\r
  @retval - The page count for specific BaseMem Index\r
\r
**/\r
UINT32\r
NvmeBaseMemPageOffset (\r
  IN UINTN              BaseMemIndex\r
  );\r
\r
/**\r
  Initialize the Nvm Express controller.\r
\r
  @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
\r
  @retval EFI_SUCCESS    The NVM Express Controller is initialized successfully.\r
  @retval Others         A device error occurred while initializing the controller.\r
\r
**/\r
EFI_STATUS\r
NvmeControllerInit (\r
  IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private\r
  );\r
\r
/**\r
  Get specified identify namespace data.\r
\r
  @param[in] Private        The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
  @param[in] NamespaceId    The specified namespace identifier.\r
  @param[in] Buffer         The buffer used to store the identify namespace data.\r
\r
  @return EFI_SUCCESS         Successfully get the identify namespace data.\r
  @return EFI_DEVICE_ERROR    Fail to get the identify namespace data.\r
\r
**/\r
EFI_STATUS\r
NvmeIdentifyNamespace (\r
  IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private,\r
  IN UINT32                              NamespaceId,\r
  IN VOID                                *Buffer\r
  );\r
\r
/**\r
  Free the DMA resources allocated by an NVME controller.\r
\r
  @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
\r
**/\r
VOID\r
NvmeFreeDmaResource (\r
  IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private\r
  );\r
\r
#endif\r
Commit	Line	Data
b8b69433 HW	1	/** @file\r
	2	The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
	3	which follows NVM Express specification at PEI phase.\r
	4	\r
2e15b750	5	Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
b8b69433 HW	6	\r
	7	This program and the accompanying materials\r
	8	are licensed and made available under the terms and conditions\r
	9	of the BSD License which accompanies this distribution. The\r
	10	full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef _NVM_EXPRESS_PEI_HCI_H_\r
	19	#define _NVM_EXPRESS_PEI_HCI_H_\r
	20	\r
	21	//\r
	22	// NVME host controller registers operation definitions\r
	23	//\r
	24	#define NVME_GET_CAP(Private, Cap) NvmeMmioRead (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))\r
	25	#define NVME_GET_CC(Private, Cc) NvmeMmioRead (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))\r
	26	#define NVME_SET_CC(Private, Cc) NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))\r
	27	#define NVME_GET_CSTS(Private, Csts) NvmeMmioRead (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))\r
	28	#define NVME_GET_AQA(Private, Aqa) NvmeMmioRead (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))\r
	29	#define NVME_SET_AQA(Private, Aqa) NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))\r
	30	#define NVME_GET_ASQ(Private, Asq) NvmeMmioRead (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))\r
	31	#define NVME_SET_ASQ(Private, Asq) NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))\r
	32	#define NVME_GET_ACQ(Private, Acq) NvmeMmioRead (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))\r
	33	#define NVME_SET_ACQ(Private, Acq) NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))\r
	34	#define NVME_GET_VER(Private, Ver) NvmeMmioRead (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))\r
	35	#define NVME_SET_SQTDBL(Private, Qid, Sqtdbl) NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))\r
	36	#define NVME_SET_CQHDBL(Private, Qid, Cqhdbl) NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))\r
	37	\r
	38	//\r
	39	// Base memory address enum types\r
	40	//\r
	41	enum {\r
	42	BASEMEM_ASQ,\r
	43	BASEMEM_ACQ,\r
	44	BASEMEM_SQ,\r
	45	BASEMEM_CQ,\r
	46	BASEMEM_PRP,\r
	47	MAX_BASEMEM_COUNT\r
	48	};\r
	49	\r
	50	//\r
	51	// All of base memories are 4K(0x1000) alignment\r
	52	//\r
	53	#define ALIGN(v, a) (UINTN)((((v) - 1) \| ((a) - 1)) + 1)\r
	54	#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))\r
	55	#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
	56	#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
	57	#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)(NVME_MAX_QUEUES-1))) EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
	58	#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)(NVME_MAX_QUEUES-1))) EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
	59	#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
	60	\r
	61	\r
	62	/**\r
	63	Transfer MMIO Data to memory.\r
	64	\r
	65	@param[in,out] MemBuffer Destination: Memory address.\r
	66	@param[in] MmioAddr Source: MMIO address.\r
	67	@param[in] Size Size for read.\r
	68	\r
	69	@retval EFI_SUCCESS MMIO read sucessfully.\r
70	\r
71	**/\r
72	EFI_STATUS\r
73	NvmeMmioRead (\r
74	IN OUT VOID *MemBuffer,\r
75	IN UINTN MmioAddr,\r
76	IN UINTN Size\r
77	);\r
78	\r
79	/**\r
80	Transfer memory data to MMIO.\r
81	\r
82	@param[in,out] MmioAddr Destination: MMIO address.\r
83	@param[in] MemBuffer Source: Memory address.\r
84	@param[in] Size Size for write.\r
85	\r
86	@retval EFI_SUCCESS MMIO write sucessfully.\r
87	\r
88	**/\r
89	EFI_STATUS\r
90	NvmeMmioWrite (\r
91	IN OUT UINTN MmioAddr,\r
92	IN VOID *MemBuffer,\r
93	IN UINTN Size\r
94	);\r
95	\r
96	/**\r
97	Get the page offset for specific NVME based memory.\r
98	\r
99	@param[in] BaseMemIndex The Index of BaseMem (0-based).\r
100	\r
101	@retval - The page count for specific BaseMem Index\r
102	\r
103	**/\r
104	UINT32\r
105	NvmeBaseMemPageOffset (\r
106	IN UINTN BaseMemIndex\r
107	);\r
108	\r
b8b69433 HW	109	/**\r
	110	Initialize the Nvm Express controller.\r
	111	\r
	112	@param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
	113	\r
	114	@retval EFI_SUCCESS The NVM Express Controller is initialized successfully.\r
	115	@retval Others A device error occurred while initializing the controller.\r
	116	\r
	117	**/\r
	118	EFI_STATUS\r
	119	NvmeControllerInit (\r
	120	IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
	121	);\r
	122	\r
	123	/**\r
	124	Get specified identify namespace data.\r
	125	\r
	126	@param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
	127	@param[in] NamespaceId The specified namespace identifier.\r
	128	@param[in] Buffer The buffer used to store the identify namespace data.\r
	129	\r
	130	@return EFI_SUCCESS Successfully get the identify namespace data.\r
	131	@return EFI_DEVICE_ERROR Fail to get the identify namespace data.\r
	132	\r
	133	**/\r
	134	EFI_STATUS\r
	135	NvmeIdentifyNamespace (\r
	136	IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,\r
	137	IN UINT32 NamespaceId,\r
	138	IN VOID *Buffer\r
	139	);\r
	140	\r
	141	/**\r
2e15b750	142	Free the DMA resources allocated by an NVME controller.\r
b8b69433 HW	143	\r
	144	@param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.\r
	145	\r
	146	**/\r
	147	VOID\r
2e15b750	148	NvmeFreeDmaResource (\r
b8b69433 HW	149	IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private\r
	150	);\r
	151	\r
	152	#endif\r