[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciBus.h

/** @file\r
  Header files and data structures needed by PCI Bus module.\r
\r
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_PCI_BUS_H_\r
#define _EFI_PCI_BUS_H_\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/LoadedImage.h>\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciIo.h>\r
#include <Protocol/LoadFile2.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/PciHotPlugRequest.h>\r
#include <Protocol/DevicePath.h>\r
#include <Protocol/PciPlatform.h>\r
#include <Protocol/PciHotPlugInit.h>\r
#include <Protocol/Decompress.h>\r
#include <Protocol/BusSpecificDriverOverride.h>\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
#include <Protocol/PciOverride.h>\r
#include <Protocol/PciEnumerationComplete.h>\r
#include <Protocol/IoMmu.h>\r
#include <Protocol/DeviceSecurity.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/PcdLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/PeImage.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
typedef struct _PCI_IO_DEVICE  PCI_IO_DEVICE;\r
typedef struct _PCI_BAR        PCI_BAR;\r
\r
#define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
#define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)\r
\r
#define     EFI_PCI_IOV_POLICY_ARI    0x0001\r
#define     EFI_PCI_IOV_POLICY_SRIOV  0x0002\r
#define     EFI_PCI_IOV_POLICY_MRIOV  0x0004\r
\r
typedef enum {\r
  PciBarTypeUnknown = 0,\r
  PciBarTypeIo16,\r
  PciBarTypeIo32,\r
  PciBarTypeMem32,\r
  PciBarTypePMem32,\r
  PciBarTypeMem64,\r
  PciBarTypePMem64,\r
  PciBarTypeOpRom,\r
  PciBarTypeIo,\r
  PciBarTypeMem,\r
  PciBarTypeMaxType\r
} PCI_BAR_TYPE;\r
\r
#include "ComponentName.h"\r
#include "PciIo.h"\r
#include "PciCommand.h"\r
#include "PciDeviceSupport.h"\r
#include "PciEnumerator.h"\r
#include "PciEnumeratorSupport.h"\r
#include "PciDriverOverride.h"\r
#include "PciRomTable.h"\r
#include "PciOptionRomSupport.h"\r
#include "PciPowerManagement.h"\r
#include "PciHotPlugSupport.h"\r
#include "PciLib.h"\r
\r
#define VGABASE1   0x3B0\r
#define VGALIMIT1  0x3BB\r
\r
#define VGABASE2   0x3C0\r
#define VGALIMIT2  0x3DF\r
\r
#define ISABASE   0x100\r
#define ISALIMIT  0x3FF\r
\r
//\r
// PCI BAR parameters\r
//\r
struct _PCI_BAR {\r
  UINT64          BaseAddress;\r
  UINT64          Length;\r
  UINT64          Alignment;\r
  PCI_BAR_TYPE    BarType;\r
  BOOLEAN         BarTypeFixed;\r
  UINT16          Offset;\r
};\r
\r
//\r
// defined in PCI Card Specification, 8.0\r
//\r
#define PCI_CARD_MEMORY_BASE_0     0x1C\r
#define PCI_CARD_MEMORY_LIMIT_0    0x20\r
#define PCI_CARD_MEMORY_BASE_1     0x24\r
#define PCI_CARD_MEMORY_LIMIT_1    0x28\r
#define PCI_CARD_IO_BASE_0_LOWER   0x2C\r
#define PCI_CARD_IO_BASE_0_UPPER   0x2E\r
#define PCI_CARD_IO_LIMIT_0_LOWER  0x30\r
#define PCI_CARD_IO_LIMIT_0_UPPER  0x32\r
#define PCI_CARD_IO_BASE_1_LOWER   0x34\r
#define PCI_CARD_IO_BASE_1_UPPER   0x36\r
#define PCI_CARD_IO_LIMIT_1_LOWER  0x38\r
#define PCI_CARD_IO_LIMIT_1_UPPER  0x3A\r
#define PCI_CARD_BRIDGE_CONTROL    0x3E\r
\r
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE  BIT8\r
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE  BIT9\r
\r
#define RB_IO_RANGE      1\r
#define RB_MEM32_RANGE   2\r
#define RB_PMEM32_RANGE  3\r
#define RB_MEM64_RANGE   4\r
#define RB_PMEM64_RANGE  5\r
\r
#define PPB_BAR_0         0\r
#define PPB_BAR_1         1\r
#define PPB_IO_RANGE      2\r
#define PPB_MEM32_RANGE   3\r
#define PPB_PMEM32_RANGE  4\r
#define PPB_PMEM64_RANGE  5\r
#define PPB_MEM64_RANGE   0xFF\r
\r
#define P2C_BAR_0  0\r
#define P2C_MEM_1  1\r
#define P2C_MEM_2  2\r
#define P2C_IO_1   3\r
#define P2C_IO_2   4\r
\r
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED       0x0001\r
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED     0x0002\r
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED     0x0004\r
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED       0x0008\r
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED  0x0010\r
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED      0x0020\r
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED      0x0040\r
\r
#define PCI_MAX_HOST_BRIDGE_NUM  0x0010\r
\r
//\r
// Define option for attribute\r
//\r
#define EFI_SET_SUPPORTS    0\r
#define EFI_SET_ATTRIBUTES  1\r
\r
#define PCI_IO_DEVICE_SIGNATURE  SIGNATURE_32 ('p', 'c', 'i', 'o')\r
\r
struct _PCI_IO_DEVICE {\r
  UINT32                                       Signature;\r
  EFI_HANDLE                                   Handle;\r
  EFI_PCI_IO_PROTOCOL                          PciIo;\r
  LIST_ENTRY                                   Link;\r
\r
  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL    PciDriverOverride;\r
  EFI_DEVICE_PATH_PROTOCOL                     *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *PciRootBridgeIo;\r
  EFI_LOAD_FILE2_PROTOCOL                      LoadFile2;\r
\r
  //\r
  // PCI configuration space header type\r
  //\r
  PCI_TYPE00                                   Pci;\r
\r
  //\r
  // Bus number, Device number, Function number\r
  //\r
  UINT8                                        BusNumber;\r
  UINT8                                        DeviceNumber;\r
  UINT8                                        FunctionNumber;\r
\r
  //\r
  // BAR for this PCI Device\r
  //\r
  PCI_BAR                                      PciBar[PCI_MAX_BAR];\r
\r
  //\r
  // The bridge device this pci device is subject to\r
  //\r
  PCI_IO_DEVICE                                *Parent;\r
\r
  //\r
  // A linked list for children Pci Device if it is bridge device\r
  //\r
  LIST_ENTRY                                   ChildList;\r
\r
  //\r
  // TRUE if the PCI bus driver creates the handle for this PCI device\r
  //\r
  BOOLEAN                                      Registered;\r
\r
  //\r
  // TRUE if the PCI bus driver successfully allocates the resource required by\r
  // this PCI device\r
  //\r
  BOOLEAN                                      Allocated;\r
\r
  //\r
  // The attribute this PCI device currently set\r
  //\r
  UINT64                                       Attributes;\r
\r
  //\r
  // The attributes this PCI device actually supports\r
  //\r
  UINT64                                       Supports;\r
\r
  //\r
  // The resource decode the bridge supports\r
  //\r
  UINT32                                       Decodes;\r
\r
  //\r
  // TRUE if the ROM image is from the PCI Option ROM BAR\r
  //\r
  BOOLEAN                                      EmbeddedRom;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT32                                       RomSize;\r
\r
  //\r
  // TRUE if all OpROM (in device or in platform specific position) have been processed\r
  //\r
  BOOLEAN                                      AllOpRomProcessed;\r
\r
  //\r
  // TRUE if there is any EFI driver in the OptionRom\r
  //\r
  BOOLEAN                                      BusOverride;\r
\r
  //\r
  // A list tracking reserved resource on a bridge device\r
  //\r
  LIST_ENTRY                                   ReservedResourceList;\r
\r
  //\r
  // A list tracking image handle of platform specific overriding driver\r
  //\r
  LIST_ENTRY                                   OptionRomDriverList;\r
\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR            *ResourcePaddingDescriptors;\r
  EFI_HPC_PADDING_ATTRIBUTES                   PaddingAttributes;\r
\r
  //\r
  // Bus number ranges for a PCI Root Bridge device\r
  //\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR            *BusNumberRanges;\r
\r
  BOOLEAN                                      IsPciExp;\r
  //\r
  // For SR-IOV\r
  //\r
  UINT8                                        PciExpressCapabilityOffset;\r
  UINT32                                       AriCapabilityOffset;\r
  UINT32                                       SrIovCapabilityOffset;\r
  UINT32                                       MrIovCapabilityOffset;\r
  PCI_BAR                                      VfPciBar[PCI_MAX_BAR];\r
  UINT32                                       SystemPageSize;\r
  UINT16                                       InitialVFs;\r
  UINT16                                       ReservedBusNum;\r
  //\r
  // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
  // but some chipsets support non-standard I/O window alignments less than 4K.\r
  // This field is used to support this case.\r
  //\r
  UINT16                                       BridgeIoAlignment;\r
  UINT32                                       ResizableBarOffset;\r
  UINT32                                       ResizableBarNumber;\r
};\r
\r
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LINK(a) \\r
  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
\r
//\r
// Global Variables\r
//\r
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL  *gIncompatiblePciDeviceSupport;\r
extern EFI_DRIVER_BINDING_PROTOCOL                   gPciBusDriverBinding;\r
extern EFI_COMPONENT_NAME_PROTOCOL                   gPciBusComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL                  gPciBusComponentName2;\r
extern BOOLEAN                                       gFullEnumeration;\r
extern UINTN                                         gPciHostBridgeNumber;\r
extern EFI_HANDLE                                    gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
extern UINT64                                        gAllOne;\r
extern UINT64                                        gAllZero;\r
extern EFI_PCI_PLATFORM_PROTOCOL                     *gPciPlatformProtocol;\r
extern EFI_PCI_OVERRIDE_PROTOCOL                     *gPciOverrideProtocol;\r
extern BOOLEAN                                       mReserveIsaAliases;\r
extern BOOLEAN                                       mReserveVgaAliases;\r
\r
/**\r
  Macro that checks whether device is a GFX device.\r
\r
  @param  _p      Specified device.\r
\r
  @retval TRUE    Device is a GFX device.\r
  @retval FALSE   Device is not a GFX device.\r
\r
**/\r
#define IS_PCI_GFX(_p)  IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
\r
/**\r
  Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
  than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
\r
  @param  This                Protocol instance pointer.\r
  @param  Controller          Handle of device to test.\r
  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
                              device to start.\r
\r
  @retval EFI_SUCCESS         This driver supports this device.\r
  @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
  @retval other               This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingSupported (\r
  IN EFI_DRIVER_BINDING_PROTOCOL  *This,\r
  IN EFI_HANDLE                   Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath\r
  );\r
\r
/**\r
  Start this driver on ControllerHandle and enumerate Pci bus and start\r
  all device under PCI bus.\r
\r
  @param  This                 Protocol instance pointer.\r
  @param  Controller           Handle of device to bind driver to.\r
  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
                               device to start.\r
\r
  @retval EFI_SUCCESS          This driver is added to ControllerHandle.\r
  @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.\r
  @retval other                This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStart (\r
  IN EFI_DRIVER_BINDING_PROTOCOL  *This,\r
  IN EFI_HANDLE                   Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath\r
  );\r
\r
/**\r
  Stop this driver on ControllerHandle. Support stopping any child handles\r
  created by this driver.\r
\r
  @param  This              Protocol instance pointer.\r
  @param  Controller        Handle of device to stop driver on.\r
  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
                            children is zero stop the entire bus driver.\r
  @param  ChildHandleBuffer List of Child Handles to Stop.\r
\r
  @retval EFI_SUCCESS       This driver is removed ControllerHandle.\r
  @retval other             This driver was not removed from this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStop (\r
  IN  EFI_DRIVER_BINDING_PROTOCOL  *This,\r
  IN  EFI_HANDLE                   Controller,\r
  IN  UINTN                        NumberOfChildren,\r
  IN  EFI_HANDLE                   *ChildHandleBuffer\r
  );\r
\r
#endif\r
Commit	Line	Data
9060e3ec	1	/** @file\r
	2	Header files and data structures needed by PCI Bus module.\r
	3	\r
0785c619	4	Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
9d510e61	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9060e3ec	6	\r
	7	**/\r
	8	\r
9060e3ec	9	#ifndef _EFI_PCI_BUS_H_\r
	10	#define _EFI_PCI_BUS_H_\r
	11	\r
	12	#include <PiDxe.h>\r
	13	\r
	14	#include <Protocol/LoadedImage.h>\r
	15	#include <Protocol/PciHostBridgeResourceAllocation.h>\r
	16	#include <Protocol/PciIo.h>\r
	17	#include <Protocol/LoadFile2.h>\r
	18	#include <Protocol/PciRootBridgeIo.h>\r
	19	#include <Protocol/PciHotPlugRequest.h>\r
	20	#include <Protocol/DevicePath.h>\r
	21	#include <Protocol/PciPlatform.h>\r
	22	#include <Protocol/PciHotPlugInit.h>\r
	23	#include <Protocol/Decompress.h>\r
	24	#include <Protocol/BusSpecificDriverOverride.h>\r
	25	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
	26	#include <Protocol/PciOverride.h>\r
	27	#include <Protocol/PciEnumerationComplete.h>\r
11a6cc5b	28	#include <Protocol/IoMmu.h>\r
995d8b85	29	#include <Protocol/DeviceSecurity.h>\r
9060e3ec	30	\r
	31	#include <Library/DebugLib.h>\r
	32	#include <Library/UefiDriverEntryPoint.h>\r
	33	#include <Library/BaseLib.h>\r
	34	#include <Library/UefiLib.h>\r
	35	#include <Library/BaseMemoryLib.h>\r
	36	#include <Library/ReportStatusCodeLib.h>\r
	37	#include <Library/MemoryAllocationLib.h>\r
	38	#include <Library/UefiBootServicesTableLib.h>\r
	39	#include <Library/DevicePathLib.h>\r
	40	#include <Library/PcdLib.h>\r
9060e3ec	41	\r
	42	#include <IndustryStandard/Pci.h>\r
	43	#include <IndustryStandard/PeImage.h>\r
	44	#include <IndustryStandard/Acpi.h>\r
	45	\r
1436aea4 MK	46	typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
1436aea4 MK	47	typedef struct _PCI_BAR PCI_BAR;\r
9060e3ec	48	\r
	49	#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
	50	#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)\r
	51	\r
1436aea4 MK	52	#define EFI_PCI_IOV_POLICY_ARI 0x0001\r
	53	#define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r
	54	#define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r
9060e3ec	55	\r
	56	typedef enum {\r
	57	PciBarTypeUnknown = 0,\r
	58	PciBarTypeIo16,\r
	59	PciBarTypeIo32,\r
	60	PciBarTypeMem32,\r
	61	PciBarTypePMem32,\r
	62	PciBarTypeMem64,\r
	63	PciBarTypePMem64,\r
0176af14	64	PciBarTypeOpRom,\r
9060e3ec	65	PciBarTypeIo,\r
	66	PciBarTypeMem,\r
	67	PciBarTypeMaxType\r
	68	} PCI_BAR_TYPE;\r
	69	\r
	70	#include "ComponentName.h"\r
	71	#include "PciIo.h"\r
	72	#include "PciCommand.h"\r
	73	#include "PciDeviceSupport.h"\r
	74	#include "PciEnumerator.h"\r
	75	#include "PciEnumeratorSupport.h"\r
	76	#include "PciDriverOverride.h"\r
	77	#include "PciRomTable.h"\r
	78	#include "PciOptionRomSupport.h"\r
	79	#include "PciPowerManagement.h"\r
	80	#include "PciHotPlugSupport.h"\r
	81	#include "PciLib.h"\r
	82	\r
1436aea4 MK	83	#define VGABASE1 0x3B0\r
1436aea4 MK	84	#define VGALIMIT1 0x3BB\r
9060e3ec	85	\r
1436aea4 MK	86	#define VGABASE2 0x3C0\r
1436aea4 MK	87	#define VGALIMIT2 0x3DF\r
9060e3ec	88	\r
	89	#define ISABASE 0x100\r
	90	#define ISALIMIT 0x3FF\r
	91	\r
	92	//\r
	93	// PCI BAR parameters\r
	94	//\r
	95	struct _PCI_BAR {\r
1436aea4 MK	96	UINT64 BaseAddress;\r
	97	UINT64 Length;\r
	98	UINT64 Alignment;\r
	99	PCI_BAR_TYPE BarType;\r
	100	BOOLEAN BarTypeFixed;\r
	101	UINT16 Offset;\r
9060e3ec	102	};\r
	103	\r
	104	//\r
	105	// defined in PCI Card Specification, 8.0\r
	106	//\r
1436aea4 MK	107	#define PCI_CARD_MEMORY_BASE_0 0x1C\r
	108	#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
	109	#define PCI_CARD_MEMORY_BASE_1 0x24\r
	110	#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
	111	#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
	112	#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
	113	#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
	114	#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
	115	#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
	116	#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
	117	#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
	118	#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
	119	#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
	120	\r
	121	#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
	122	#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
	123	\r
	124	#define RB_IO_RANGE 1\r
	125	#define RB_MEM32_RANGE 2\r
	126	#define RB_PMEM32_RANGE 3\r
	127	#define RB_MEM64_RANGE 4\r
	128	#define RB_PMEM64_RANGE 5\r
	129	\r
	130	#define PPB_BAR_0 0\r
	131	#define PPB_BAR_1 1\r
	132	#define PPB_IO_RANGE 2\r
	133	#define PPB_MEM32_RANGE 3\r
	134	#define PPB_PMEM32_RANGE 4\r
	135	#define PPB_PMEM64_RANGE 5\r
	136	#define PPB_MEM64_RANGE 0xFF\r
	137	\r
	138	#define P2C_BAR_0 0\r
	139	#define P2C_MEM_1 1\r
	140	#define P2C_MEM_2 2\r
	141	#define P2C_IO_1 3\r
	142	#define P2C_IO_2 4\r
	143	\r
	144	#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
	145	#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
	146	#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
	147	#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
	148	#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
	149	#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
	150	#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
	151	\r
	152	#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
9060e3ec	153	\r
	154	//\r
	155	// Define option for attribute\r
	156	//\r
	157	#define EFI_SET_SUPPORTS 0\r
	158	#define EFI_SET_ATTRIBUTES 1\r
	159	\r
1436aea4	160	#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
9060e3ec	161	\r
9060e3ec	162	struct _PCI_IO_DEVICE {\r
1436aea4 MK	163	UINT32 Signature;\r
	164	EFI_HANDLE Handle;\r
	165	EFI_PCI_IO_PROTOCOL PciIo;\r
	166	LIST_ENTRY Link;\r
9060e3ec	167	\r
1436aea4 MK	168	EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
	169	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	170	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
	171	EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
9060e3ec	172	\r
	173	//\r
	174	// PCI configuration space header type\r
	175	//\r
1436aea4	176	PCI_TYPE00 Pci;\r
9060e3ec	177	\r
	178	//\r
	179	// Bus number, Device number, Function number\r
	180	//\r
1436aea4 MK	181	UINT8 BusNumber;\r
	182	UINT8 DeviceNumber;\r
	183	UINT8 FunctionNumber;\r
9060e3ec	184	\r
	185	//\r
	186	// BAR for this PCI Device\r
	187	//\r
1436aea4	188	PCI_BAR PciBar[PCI_MAX_BAR];\r
9060e3ec	189	\r
	190	//\r
	191	// The bridge device this pci device is subject to\r
	192	//\r
1436aea4	193	PCI_IO_DEVICE *Parent;\r
9060e3ec	194	\r
	195	//\r
	196	// A linked list for children Pci Device if it is bridge device\r
	197	//\r
1436aea4	198	LIST_ENTRY ChildList;\r
9060e3ec	199	\r
9060e3ec	200	//\r
ed356b9e	201	// TRUE if the PCI bus driver creates the handle for this PCI device\r
9060e3ec	202	//\r
1436aea4	203	BOOLEAN Registered;\r
9060e3ec	204	\r
	205	//\r
	206	// TRUE if the PCI bus driver successfully allocates the resource required by\r
	207	// this PCI device\r
	208	//\r
1436aea4	209	BOOLEAN Allocated;\r
9060e3ec	210	\r
	211	//\r
	212	// The attribute this PCI device currently set\r
	213	//\r
1436aea4	214	UINT64 Attributes;\r
9060e3ec	215	\r
	216	//\r
	217	// The attributes this PCI device actually supports\r
	218	//\r
1436aea4	219	UINT64 Supports;\r
9060e3ec	220	\r
	221	//\r
	222	// The resource decode the bridge supports\r
	223	//\r
1436aea4	224	UINT32 Decodes;\r
9060e3ec	225	\r
4ed4e19c	226	//\r
	227	// TRUE if the ROM image is from the PCI Option ROM BAR\r
	228	//\r
1436aea4	229	BOOLEAN EmbeddedRom;\r
4ed4e19c	230	\r
9060e3ec	231	//\r
	232	// The OptionRom Size\r
	233	//\r
1436aea4	234	UINT32 RomSize;\r
9060e3ec	235	\r
9060e3ec	236	//\r
	237	// TRUE if all OpROM (in device or in platform specific position) have been processed\r
	238	//\r
1436aea4	239	BOOLEAN AllOpRomProcessed;\r
9060e3ec	240	\r
	241	//\r
	242	// TRUE if there is any EFI driver in the OptionRom\r
	243	//\r
1436aea4	244	BOOLEAN BusOverride;\r
9060e3ec	245	\r
	246	//\r
	247	// A list tracking reserved resource on a bridge device\r
	248	//\r
1436aea4	249	LIST_ENTRY ReservedResourceList;\r
9060e3ec	250	\r
	251	//\r
	252	// A list tracking image handle of platform specific overriding driver\r
	253	//\r
1436aea4	254	LIST_ENTRY OptionRomDriverList;\r
9060e3ec	255	\r
1436aea4 MK	256	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
1436aea4 MK	257	EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
9060e3ec	258	\r
306bbe82	259	//\r
	260	// Bus number ranges for a PCI Root Bridge device\r
	261	//\r
1436aea4	262	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;\r
306bbe82	263	\r
1436aea4	264	BOOLEAN IsPciExp;\r
9060e3ec	265	//\r
	266	// For SR-IOV\r
	267	//\r
1436aea4 MK	268	UINT8 PciExpressCapabilityOffset;\r
	269	UINT32 AriCapabilityOffset;\r
	270	UINT32 SrIovCapabilityOffset;\r
	271	UINT32 MrIovCapabilityOffset;\r
	272	PCI_BAR VfPciBar[PCI_MAX_BAR];\r
	273	UINT32 SystemPageSize;\r
	274	UINT16 InitialVFs;\r
	275	UINT16 ReservedBusNum;\r
1ef26783	276	//\r
1ef26783	277	// Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
ed356b9e	278	// but some chipsets support non-standard I/O window alignments less than 4K.\r
1ef26783	279	// This field is used to support this case.\r
1ef26783	280	//\r
1436aea4 MK	281	UINT16 BridgeIoAlignment;\r
	282	UINT32 ResizableBarOffset;\r
	283	UINT32 ResizableBarNumber;\r
9060e3ec	284	};\r
	285	\r
	286	#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
	287	CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
	288	\r
	289	#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
	290	CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
	291	\r
	292	#define PCI_IO_DEVICE_FROM_LINK(a) \\r
	293	CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
	294	\r
	295	#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
	296	CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
	297	\r
9060e3ec	298	//\r
	299	// Global Variables\r
	300	//\r
1436aea4 MK	301	extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;\r
	302	extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
	303	extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
	304	extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
	305	extern BOOLEAN gFullEnumeration;\r
	306	extern UINTN gPciHostBridgeNumber;\r
	307	extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
	308	extern UINT64 gAllOne;\r
	309	extern UINT64 gAllZero;\r
	310	extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
	311	extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r
	312	extern BOOLEAN mReserveIsaAliases;\r
	313	extern BOOLEAN mReserveVgaAliases;\r
9060e3ec	314	\r
	315	/**\r
	316	Macro that checks whether device is a GFX device.\r
	317	\r
	318	@param _p Specified device.\r
	319	\r
ed356b9e GL	320	@retval TRUE Device is a GFX device.\r
ed356b9e GL	321	@retval FALSE Device is not a GFX device.\r
9060e3ec	322	\r
9060e3ec	323	**/\r
1436aea4	324	#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
9060e3ec	325	\r
	326	/**\r
	327	Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
	328	than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
	329	\r
	330	@param This Protocol instance pointer.\r
	331	@param Controller Handle of device to test.\r
ed356b9e	332	@param RemainingDevicePath Optional parameter use to pick a specific child\r
9060e3ec	333	device to start.\r
	334	\r
	335	@retval EFI_SUCCESS This driver supports this device.\r
	336	@retval EFI_ALREADY_STARTED This driver is already running on this device.\r
	337	@retval other This driver does not support this device.\r
	338	\r
	339	**/\r
	340	EFI_STATUS\r
	341	EFIAPI\r
	342	PciBusDriverBindingSupported (\r
1436aea4 MK	343	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	344	IN EFI_HANDLE Controller,\r
	345	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
9060e3ec	346	);\r
	347	\r
	348	/**\r
	349	Start this driver on ControllerHandle and enumerate Pci bus and start\r
	350	all device under PCI bus.\r
	351	\r
	352	@param This Protocol instance pointer.\r
	353	@param Controller Handle of device to bind driver to.\r
ed356b9e	354	@param RemainingDevicePath Optional parameter use to pick a specific child\r
9060e3ec	355	device to start.\r
	356	\r
	357	@retval EFI_SUCCESS This driver is added to ControllerHandle.\r
	358	@retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r
	359	@retval other This driver does not support this device.\r
	360	\r
	361	**/\r
	362	EFI_STATUS\r
	363	EFIAPI\r
	364	PciBusDriverBindingStart (\r
1436aea4 MK	365	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	366	IN EFI_HANDLE Controller,\r
	367	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
9060e3ec	368	);\r
	369	\r
	370	/**\r
ed356b9e	371	Stop this driver on ControllerHandle. Support stopping any child handles\r
9060e3ec	372	created by this driver.\r
	373	\r
	374	@param This Protocol instance pointer.\r
	375	@param Controller Handle of device to stop driver on.\r
	376	@param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r
	377	children is zero stop the entire bus driver.\r
	378	@param ChildHandleBuffer List of Child Handles to Stop.\r
	379	\r
	380	@retval EFI_SUCCESS This driver is removed ControllerHandle.\r
	381	@retval other This driver was not removed from this device.\r
	382	\r
	383	**/\r
	384	EFI_STATUS\r
	385	EFIAPI\r
	386	PciBusDriverBindingStop (\r
1436aea4 MK	387	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	388	IN EFI_HANDLE Controller,\r
	389	IN UINTN NumberOfChildren,\r
	390	IN EFI_HANDLE *ChildHandleBuffer\r
9060e3ec	391	);\r
	392	\r
	393	#endif\r