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MdeModulePkg/Pci: Add DeviceSecurity support.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciBus.h
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9060e3ec 1/** @file\r
2 Header files and data structures needed by PCI Bus module.\r
3\r
1f6785c4 4Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
9d510e61 5SPDX-License-Identifier: BSD-2-Clause-Patent\r
9060e3ec 6\r
7**/\r
8\r
9\r
10#ifndef _EFI_PCI_BUS_H_\r
11#define _EFI_PCI_BUS_H_\r
12\r
13#include <PiDxe.h>\r
14\r
15#include <Protocol/LoadedImage.h>\r
16#include <Protocol/PciHostBridgeResourceAllocation.h>\r
17#include <Protocol/PciIo.h>\r
18#include <Protocol/LoadFile2.h>\r
19#include <Protocol/PciRootBridgeIo.h>\r
20#include <Protocol/PciHotPlugRequest.h>\r
21#include <Protocol/DevicePath.h>\r
22#include <Protocol/PciPlatform.h>\r
23#include <Protocol/PciHotPlugInit.h>\r
24#include <Protocol/Decompress.h>\r
25#include <Protocol/BusSpecificDriverOverride.h>\r
26#include <Protocol/IncompatiblePciDeviceSupport.h>\r
27#include <Protocol/PciOverride.h>\r
28#include <Protocol/PciEnumerationComplete.h>\r
11a6cc5b 29#include <Protocol/IoMmu.h>\r
995d8b85 30#include <Protocol/DeviceSecurity.h>\r
9060e3ec 31\r
32#include <Library/DebugLib.h>\r
33#include <Library/UefiDriverEntryPoint.h>\r
34#include <Library/BaseLib.h>\r
35#include <Library/UefiLib.h>\r
36#include <Library/BaseMemoryLib.h>\r
37#include <Library/ReportStatusCodeLib.h>\r
38#include <Library/MemoryAllocationLib.h>\r
39#include <Library/UefiBootServicesTableLib.h>\r
40#include <Library/DevicePathLib.h>\r
41#include <Library/PcdLib.h>\r
9060e3ec 42\r
43#include <IndustryStandard/Pci.h>\r
44#include <IndustryStandard/PeImage.h>\r
45#include <IndustryStandard/Acpi.h>\r
46\r
47typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
48typedef struct _PCI_BAR PCI_BAR;\r
49\r
50#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
51#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)\r
52\r
53#define EFI_PCI_IOV_POLICY_ARI 0x0001\r
54#define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r
55#define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r
56\r
57typedef enum {\r
58 PciBarTypeUnknown = 0,\r
59 PciBarTypeIo16,\r
60 PciBarTypeIo32,\r
61 PciBarTypeMem32,\r
62 PciBarTypePMem32,\r
63 PciBarTypeMem64,\r
64 PciBarTypePMem64,\r
0176af14 65 PciBarTypeOpRom,\r
9060e3ec 66 PciBarTypeIo,\r
67 PciBarTypeMem,\r
68 PciBarTypeMaxType\r
69} PCI_BAR_TYPE;\r
70\r
71#include "ComponentName.h"\r
72#include "PciIo.h"\r
73#include "PciCommand.h"\r
74#include "PciDeviceSupport.h"\r
75#include "PciEnumerator.h"\r
76#include "PciEnumeratorSupport.h"\r
77#include "PciDriverOverride.h"\r
78#include "PciRomTable.h"\r
79#include "PciOptionRomSupport.h"\r
80#include "PciPowerManagement.h"\r
81#include "PciHotPlugSupport.h"\r
82#include "PciLib.h"\r
83\r
84#define VGABASE1 0x3B0\r
85#define VGALIMIT1 0x3BB\r
86\r
87#define VGABASE2 0x3C0\r
88#define VGALIMIT2 0x3DF\r
89\r
90#define ISABASE 0x100\r
91#define ISALIMIT 0x3FF\r
92\r
93//\r
94// PCI BAR parameters\r
95//\r
96struct _PCI_BAR {\r
97 UINT64 BaseAddress;\r
98 UINT64 Length;\r
99 UINT64 Alignment;\r
100 PCI_BAR_TYPE BarType;\r
05070c1b 101 BOOLEAN BarTypeFixed;\r
d4048391 102 UINT16 Offset;\r
9060e3ec 103};\r
104\r
105//\r
106// defined in PCI Card Specification, 8.0\r
107//\r
108#define PCI_CARD_MEMORY_BASE_0 0x1C\r
109#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
110#define PCI_CARD_MEMORY_BASE_1 0x24\r
111#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
112#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
113#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
114#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
115#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
116#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
117#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
118#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
119#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
120#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
121\r
122#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
123#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
124\r
8db6a82c
RN		 125#define RB_IO_RANGE 1\r
126#define RB_MEM32_RANGE 2\r
127#define RB_PMEM32_RANGE 3\r
128#define RB_MEM64_RANGE 4\r
129#define RB_PMEM64_RANGE 5\r
130\r
9060e3ec 131#define PPB_BAR_0 0\r
132#define PPB_BAR_1 1\r
133#define PPB_IO_RANGE 2\r
134#define PPB_MEM32_RANGE 3\r
135#define PPB_PMEM32_RANGE 4\r
136#define PPB_PMEM64_RANGE 5\r
137#define PPB_MEM64_RANGE 0xFF\r
138\r
139#define P2C_BAR_0 0\r
140#define P2C_MEM_1 1\r
141#define P2C_MEM_2 2\r
142#define P2C_IO_1 3\r
143#define P2C_IO_2 4\r
144\r
145#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
146#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
147#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
148#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
149#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
150#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
151#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
152\r
153#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
154\r
155//\r
156// Define option for attribute\r
157//\r
158#define EFI_SET_SUPPORTS 0\r
159#define EFI_SET_ATTRIBUTES 1\r
160\r
161#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
162\r
163struct _PCI_IO_DEVICE {\r
164 UINT32 Signature;\r
165 EFI_HANDLE Handle;\r
166 EFI_PCI_IO_PROTOCOL PciIo;\r
167 LIST_ENTRY Link;\r
168\r
169 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
170 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
171 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
172 EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
173\r
174 //\r
175 // PCI configuration space header type\r
176 //\r
177 PCI_TYPE00 Pci;\r
178\r
179 //\r
180 // Bus number, Device number, Function number\r
181 //\r
182 UINT8 BusNumber;\r
183 UINT8 DeviceNumber;\r
184 UINT8 FunctionNumber;\r
185\r
186 //\r
187 // BAR for this PCI Device\r
188 //\r
189 PCI_BAR PciBar[PCI_MAX_BAR];\r
190\r
191 //\r
192 // The bridge device this pci device is subject to\r
193 //\r
194 PCI_IO_DEVICE *Parent;\r
195\r
196 //\r
197 // A linked list for children Pci Device if it is bridge device\r
198 //\r
199 LIST_ENTRY ChildList;\r
200\r
201 //\r
ed356b9e 202 // TRUE if the PCI bus driver creates the handle for this PCI device\r
9060e3ec 203 //\r
204 BOOLEAN Registered;\r
205\r
206 //\r
207 // TRUE if the PCI bus driver successfully allocates the resource required by\r
208 // this PCI device\r
209 //\r
210 BOOLEAN Allocated;\r
211\r
212 //\r
213 // The attribute this PCI device currently set\r
214 //\r
215 UINT64 Attributes;\r
216\r
217 //\r
218 // The attributes this PCI device actually supports\r
219 //\r
220 UINT64 Supports;\r
221\r
222 //\r
223 // The resource decode the bridge supports\r
224 //\r
225 UINT32 Decodes;\r
226\r
4ed4e19c 227 //\r
228 // TRUE if the ROM image is from the PCI Option ROM BAR\r
229 //\r
230 BOOLEAN EmbeddedRom;\r
231\r
9060e3ec 232 //\r
233 // The OptionRom Size\r
234 //\r
1f6785c4 235 UINT32 RomSize;\r
9060e3ec 236\r
9060e3ec 237 //\r
238 // TRUE if all OpROM (in device or in platform specific position) have been processed\r
239 //\r
240 BOOLEAN AllOpRomProcessed;\r
241\r
242 //\r
243 // TRUE if there is any EFI driver in the OptionRom\r
244 //\r
245 BOOLEAN BusOverride;\r
246\r
247 //\r
248 // A list tracking reserved resource on a bridge device\r
249 //\r
250 LIST_ENTRY ReservedResourceList;\r
251\r
252 //\r
253 // A list tracking image handle of platform specific overriding driver\r
254 //\r
255 LIST_ENTRY OptionRomDriverList;\r
256\r
257 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
258 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
259\r
306bbe82 260 //\r
261 // Bus number ranges for a PCI Root Bridge device\r
262 //\r
263 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;\r
264\r
9060e3ec 265 BOOLEAN IsPciExp;\r
266 //\r
267 // For SR-IOV\r
268 //\r
269 UINT8 PciExpressCapabilityOffset;\r
270 UINT32 AriCapabilityOffset;\r
271 UINT32 SrIovCapabilityOffset;\r
272 UINT32 MrIovCapabilityOffset;\r
273 PCI_BAR VfPciBar[PCI_MAX_BAR];\r
274 UINT32 SystemPageSize;\r
275 UINT16 InitialVFs;\r
276 UINT16 ReservedBusNum;\r
1ef26783 277 //\r
278 // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
ed356b9e 279 // but some chipsets support non-standard I/O window alignments less than 4K.\r
1ef26783 280 // This field is used to support this case.\r
281 //\r
282 UINT16 BridgeIoAlignment;\r
9060e3ec 283};\r
284\r
285#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
286 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
287\r
288#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
289 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
290\r
291#define PCI_IO_DEVICE_FROM_LINK(a) \\r
292 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
293\r
294#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
295 CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
296\r
297\r
298\r
299//\r
300// Global Variables\r
301//\r
ea669c1b 302extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;\r
9060e3ec 303extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
304extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
305extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
306extern BOOLEAN gFullEnumeration;\r
307extern UINTN gPciHostBridgeNumber;\r
308extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
309extern UINT64 gAllOne;\r
310extern UINT64 gAllZero;\r
311extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
312extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r
e0ee9d93 313extern BOOLEAN mReserveIsaAliases;\r
314extern BOOLEAN mReserveVgaAliases;\r
9060e3ec 315\r
316/**\r
317 Macro that checks whether device is a GFX device.\r
318\r
319 @param _p Specified device.\r
320\r
ed356b9e
GL		 321 @retval TRUE Device is a GFX device.\r
322 @retval FALSE Device is not a GFX device.\r
9060e3ec 323\r
324**/\r
325#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
326\r
327/**\r
328 Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
329 than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
330\r
331 @param This Protocol instance pointer.\r
332 @param Controller Handle of device to test.\r
ed356b9e 333 @param RemainingDevicePath Optional parameter use to pick a specific child\r
9060e3ec 334 device to start.\r
335\r
336 @retval EFI_SUCCESS This driver supports this device.\r
337 @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
338 @retval other This driver does not support this device.\r
339\r
340**/\r
341EFI_STATUS\r
342EFIAPI\r
343PciBusDriverBindingSupported (\r
344 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
345 IN EFI_HANDLE Controller,\r
346 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
347 );\r
348\r
349/**\r
350 Start this driver on ControllerHandle and enumerate Pci bus and start\r
351 all device under PCI bus.\r
352\r
353 @param This Protocol instance pointer.\r
354 @param Controller Handle of device to bind driver to.\r
ed356b9e 355 @param RemainingDevicePath Optional parameter use to pick a specific child\r
9060e3ec 356 device to start.\r
357\r
358 @retval EFI_SUCCESS This driver is added to ControllerHandle.\r
359 @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r
360 @retval other This driver does not support this device.\r
361\r
362**/\r
363EFI_STATUS\r
364EFIAPI\r
365PciBusDriverBindingStart (\r
366 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
367 IN EFI_HANDLE Controller,\r
368 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
369 );\r
370\r
371/**\r
ed356b9e 372 Stop this driver on ControllerHandle. Support stopping any child handles\r
9060e3ec 373 created by this driver.\r
374\r
375 @param This Protocol instance pointer.\r
376 @param Controller Handle of device to stop driver on.\r
377 @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r
378 children is zero stop the entire bus driver.\r
379 @param ChildHandleBuffer List of Child Handles to Stop.\r
380\r
381 @retval EFI_SUCCESS This driver is removed ControllerHandle.\r
382 @retval other This driver was not removed from this device.\r
383\r
384**/\r
385EFI_STATUS\r
386EFIAPI\r
387PciBusDriverBindingStop (\r
388 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
389 IN EFI_HANDLE Controller,\r
390 IN UINTN NumberOfChildren,\r
391 IN EFI_HANDLE *ChildHandleBuffer\r
392 );\r
393\r
394#endif\r
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