MdeModulePkg/SdMmcPciHcDxe: Do not map memory for non DMA transfer

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciCommand.h

/** @file\r
  PCI command register operations supporting functions declaration for PCI Bus module.\r
\r
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
\r
#ifndef _EFI_PCI_COMMAND_H_\r
#define _EFI_PCI_COMMAND_H_\r
\r
//\r
// The PCI Command register bits owned by PCI Bus driver.\r
//\r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
#define EFI_PCI_COMMAND_BITS_OWNED                          ( \\r
                EFI_PCI_COMMAND_IO_SPACE                    | \\r
                EFI_PCI_COMMAND_MEMORY_SPACE                | \\r
                EFI_PCI_COMMAND_BUS_MASTER                  | \\r
                EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \\r
                EFI_PCI_COMMAND_VGA_PALETTE_SNOOP           | \\r
                EFI_PCI_COMMAND_FAST_BACK_TO_BACK             \\r
                )\r
\r
//\r
// The PCI Bridge Control register bits owned by PCI Bus driver.\r
//\r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED                   ( \\r
                EFI_PCI_BRIDGE_CONTROL_ISA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_VGA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_VGA_16               | \\r
                EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \\r
                )\r
\r
//\r
// The PCCard Bridge Control register bits owned by PCI Bus driver.\r
//\r
// They should be cleared at the beginning. The other registers\r
// are owned by chipset, we should not touch them.\r
//\r
#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED                ( \\r
                EFI_PCI_BRIDGE_CONTROL_ISA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_VGA                  | \\r
                EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \\r
                )\r
\r
\r
#define EFI_GET_REGISTER      1\r
#define EFI_SET_REGISTER      2\r
#define EFI_ENABLE_REGISTER   3\r
#define EFI_DISABLE_REGISTER  4\r
\r
/**\r
  Operate the PCI register via PciIo function interface.\r
\r
  @param PciIoDevice    Pointer to instance of PCI_IO_DEVICE.\r
  @param Command        Operator command.\r
  @param Offset         The address within the PCI configuration space for the PCI controller.\r
  @param Operation      Type of Operation.\r
  @param PtrCommand     Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.\r
\r
  @return Status of PciIo operation.\r
\r
**/\r
EFI_STATUS\r
PciOperateRegister (\r
  IN  PCI_IO_DEVICE *PciIoDevice,\r
  IN  UINT16        Command,\r
  IN  UINT8         Offset,\r
  IN  UINT8         Operation,\r
  OUT UINT16        *PtrCommand\r
  );\r
\r
/**\r
  Check the capability supporting by given device.\r
\r
  @param PciIoDevice   Pointer to instance of PCI_IO_DEVICE.\r
\r
  @retval TRUE         Capability supported.\r
  @retval FALSE        Capability not supported.\r
\r
**/\r
BOOLEAN\r
PciCapabilitySupport (\r
  IN PCI_IO_DEVICE  *PciIoDevice\r
  );\r
\r
/**\r
  Locate capability register block per capability ID.\r
\r
  @param PciIoDevice       A pointer to the PCI_IO_DEVICE.\r
  @param CapId             The capability ID.\r
  @param Offset            A pointer to the offset returned.\r
  @param NextRegBlock      A pointer to the next block returned.\r
\r
  @retval EFI_SUCCESS      Successfully located capability register block.\r
  @retval EFI_UNSUPPORTED  Pci device does not support capability.\r
  @retval EFI_NOT_FOUND    Pci device support but can not find register block.\r
\r
**/\r
EFI_STATUS\r
LocateCapabilityRegBlock (\r
  IN PCI_IO_DEVICE  *PciIoDevice,\r
  IN UINT8          CapId,\r
  IN OUT UINT8      *Offset,\r
  OUT UINT8         *NextRegBlock OPTIONAL\r
  );\r
\r
/**\r
  Locate PciExpress capability register block per capability ID.\r
\r
  @param PciIoDevice       A pointer to the PCI_IO_DEVICE.\r
  @param CapId             The capability ID.\r
  @param Offset            A pointer to the offset returned.\r
  @param NextRegBlock      A pointer to the next block returned.\r
\r
  @retval EFI_SUCCESS      Successfully located capability register block.\r
  @retval EFI_UNSUPPORTED  Pci device does not support capability.\r
  @retval EFI_NOT_FOUND    Pci device support but can not find register block.\r
\r
**/\r
EFI_STATUS\r
LocatePciExpressCapabilityRegBlock (\r
  IN     PCI_IO_DEVICE *PciIoDevice,\r
  IN     UINT16        CapId,\r
  IN OUT UINT32        *Offset,\r
     OUT UINT32        *NextRegBlock OPTIONAL\r
  );\r
\r
/**\r
  Macro that reads command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[out]           Pointer to the 16-bit value read from command register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_READ_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
\r
/**\r
  Macro that writes command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The 16-bit value written into command register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_SET_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
\r
/**\r
  Macro that enables command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The enabled value written into command register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_ENABLE_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
/**\r
  Macro that disables command register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The disabled value written into command register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_DISABLE_COMMAND_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
\r
/**\r
  Macro that reads PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[out]           The 16-bit value read from control register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
\r
/**\r
  Macro that writes PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The 16-bit value written into control register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
\r
/**\r
  Macro that enables PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The enabled value written into command register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
\r
/**\r
 Macro that disables PCI bridge control register.\r
\r
  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
  @param b[in]            The disabled value written into command register.\r
\r
  @return status of PciIo operation\r
\r
**/\r
#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
\r
#endif\r