[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.h

/** @file\r
\r
  Provides some data structure definitions used by the SD/MMC host controller driver.\r
\r
Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _SD_MMC_PCI_HCI_H_\r
#define _SD_MMC_PCI_HCI_H_\r
\r
//\r
// SD Host Controller SlotInfo Register Offset\r
//\r
#define SD_MMC_HC_SLOT_OFFSET         0x40\r
\r
#define SD_MMC_HC_MAX_SLOT            6\r
\r
//\r
// SD Host Controller MMIO Register Offset\r
//\r
#define SD_MMC_HC_SDMA_ADDR           0x00\r
#define SD_MMC_HC_ARG2                0x00\r
#define SD_MMC_HC_BLK_SIZE            0x04\r
#define SD_MMC_HC_BLK_COUNT           0x06\r
#define SD_MMC_HC_ARG1                0x08\r
#define SD_MMC_HC_TRANS_MOD           0x0C\r
#define SD_MMC_HC_COMMAND             0x0E\r
#define SD_MMC_HC_RESPONSE            0x10\r
#define SD_MMC_HC_BUF_DAT_PORT        0x20\r
#define SD_MMC_HC_PRESENT_STATE       0x24\r
#define SD_MMC_HC_HOST_CTRL1          0x28\r
#define SD_MMC_HC_POWER_CTRL          0x29\r
#define SD_MMC_HC_BLK_GAP_CTRL        0x2A\r
#define SD_MMC_HC_WAKEUP_CTRL         0x2B\r
#define SD_MMC_HC_CLOCK_CTRL          0x2C\r
#define SD_MMC_HC_TIMEOUT_CTRL        0x2E\r
#define SD_MMC_HC_SW_RST              0x2F\r
#define SD_MMC_HC_NOR_INT_STS         0x30\r
#define SD_MMC_HC_ERR_INT_STS         0x32\r
#define SD_MMC_HC_NOR_INT_STS_EN      0x34\r
#define SD_MMC_HC_ERR_INT_STS_EN      0x36\r
#define SD_MMC_HC_NOR_INT_SIG_EN      0x38\r
#define SD_MMC_HC_ERR_INT_SIG_EN      0x3A\r
#define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C\r
#define SD_MMC_HC_HOST_CTRL2          0x3E\r
#define SD_MMC_HC_CAP                 0x40\r
#define SD_MMC_HC_MAX_CURRENT_CAP     0x48\r
#define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50\r
#define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52\r
#define SD_MMC_HC_ADMA_ERR_STS        0x54\r
#define SD_MMC_HC_ADMA_SYS_ADDR       0x58\r
#define SD_MMC_HC_PRESET_VAL          0x60\r
#define SD_MMC_HC_SHARED_BUS_CTRL     0xE0\r
#define SD_MMC_HC_SLOT_INT_STS        0xFC\r
#define SD_MMC_HC_CTRL_VER            0xFE\r
\r
//\r
// SD Host Controller bits to HOST_CTRL2 register\r
//\r
#define SD_MMC_HC_CTRL_UHS_MASK       0x0007\r
#define SD_MMC_HC_CTRL_UHS_SDR12      0x0000\r
#define SD_MMC_HC_CTRL_UHS_SDR25      0x0001\r
#define SD_MMC_HC_CTRL_UHS_SDR50      0x0002\r
#define SD_MMC_HC_CTRL_UHS_SDR104     0x0003\r
#define SD_MMC_HC_CTRL_UHS_DDR50      0x0004\r
#define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000\r
#define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001\r
#define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004\r
#define SD_MMC_HC_CTRL_MMC_HS200      0x0003\r
#define SD_MMC_HC_CTRL_MMC_HS400      0x0005\r
\r
//\r
// The transfer modes supported by SD Host Controller\r
//\r
typedef enum {\r
  SdMmcNoData,\r
  SdMmcPioMode,\r
  SdMmcSdmaMode,\r
  SdMmcAdma32bMode,\r
  SdMmcAdma64bV3Mode,\r
  SdMmcAdma64bV4Mode\r
} SD_MMC_HC_TRANSFER_MODE;\r
\r
//\r
// The ADMA transfer lengths supported by SD Host Controller\r
//\r
typedef enum {\r
  SdMmcAdmaLen16b,\r
  SdMmcAdmaLen26b\r
} SD_MMC_HC_ADMA_LENGTH_MODE;\r
\r
//\r
// The maximum data length of each descriptor line\r
//\r
#define ADMA_MAX_DATA_PER_LINE_16B     SIZE_64KB\r
#define ADMA_MAX_DATA_PER_LINE_26B     SIZE_64MB\r
\r
//\r
// ADMA descriptor for 32b addressing.\r
//\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 Address;\r
} SD_MMC_HC_ADMA_32_DESC_LINE;\r
\r
//\r
// ADMA descriptor for 64b addressing.\r
//\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 LowerAddress;\r
  UINT32 UpperAddress;\r
} SD_MMC_HC_ADMA_64_V3_DESC_LINE;\r
\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 UpperLength:10;\r
  UINT32 LowerLength:16;\r
  UINT32 LowerAddress;\r
  UINT32 UpperAddress;\r
  UINT32 Reserved1;\r
} SD_MMC_HC_ADMA_64_V4_DESC_LINE;\r
\r
#define SD_MMC_SDMA_BOUNDARY          512 * 1024\r
#define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))\r
\r
typedef struct {\r
  UINT8    FirstBar:3;        // bit 0:2\r
  UINT8    Reserved:1;        // bit 3\r
  UINT8    SlotNum:3;         // bit 4:6\r
  UINT8    Reserved1:1;       // bit 7\r
} SD_MMC_HC_SLOT_INFO;\r
\r
typedef struct {\r
  UINT32   TimeoutFreq:6;     // bit 0:5\r
  UINT32   Reserved:1;        // bit 6\r
  UINT32   TimeoutUnit:1;     // bit 7\r
  UINT32   BaseClkFreq:8;     // bit 8:15\r
  UINT32   MaxBlkLen:2;       // bit 16:17\r
  UINT32   BusWidth8:1;       // bit 18\r
  UINT32   Adma2:1;           // bit 19\r
  UINT32   Reserved2:1;       // bit 20\r
  UINT32   HighSpeed:1;       // bit 21\r
  UINT32   Sdma:1;            // bit 22\r
  UINT32   SuspRes:1;         // bit 23\r
  UINT32   Voltage33:1;       // bit 24\r
  UINT32   Voltage30:1;       // bit 25\r
  UINT32   Voltage18:1;       // bit 26\r
  UINT32   SysBus64V4:1;      // bit 27\r
  UINT32   SysBus64V3:1;      // bit 28\r
  UINT32   AsyncInt:1;        // bit 29\r
  UINT32   SlotType:2;        // bit 30:31\r
  UINT32   Sdr50:1;           // bit 32\r
  UINT32   Sdr104:1;          // bit 33\r
  UINT32   Ddr50:1;           // bit 34\r
  UINT32   Reserved3:1;       // bit 35\r
  UINT32   DriverTypeA:1;     // bit 36\r
  UINT32   DriverTypeC:1;     // bit 37\r
  UINT32   DriverTypeD:1;     // bit 38\r
  UINT32   DriverType4:1;     // bit 39\r
  UINT32   TimerCount:4;      // bit 40:43\r
  UINT32   Reserved4:1;       // bit 44\r
  UINT32   TuningSDR50:1;     // bit 45\r
  UINT32   RetuningMod:2;     // bit 46:47\r
  UINT32   ClkMultiplier:8;   // bit 48:55\r
  UINT32   Reserved5:7;       // bit 56:62\r
  UINT32   Hs400:1;           // bit 63\r
} SD_MMC_HC_SLOT_CAP;\r
\r
//\r
// SD Host controller version\r
//\r
#define SD_MMC_HC_CTRL_VER_100        0x00\r
#define SD_MMC_HC_CTRL_VER_200        0x01\r
#define SD_MMC_HC_CTRL_VER_300        0x02\r
#define SD_MMC_HC_CTRL_VER_400        0x03\r
#define SD_MMC_HC_CTRL_VER_410        0x04\r
#define SD_MMC_HC_CTRL_VER_420        0x05\r
\r
//\r
// SD Host controller V4 enhancements\r
//\r
#define SD_MMC_HC_V4_EN               BIT12\r
#define SD_MMC_HC_64_ADDR_EN          BIT13\r
#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
\r
/**\r
  Dump the content of SD/MMC host controller's Capability Register.\r
\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[in]  Capability      The buffer to store the capability data.\r
\r
**/\r
VOID\r
DumpCapabilityReg (\r
  IN UINT8                Slot,\r
  IN SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Read SlotInfo register from SD/MMC host controller pci config space.\r
\r
  @param[in]  PciIo        The PCI IO protocol instance.\r
  @param[out] FirstBar     The buffer to store the first BAR value.\r
  @param[out] SlotNum      The buffer to store the supported slot number.\r
\r
  @retval EFI_SUCCESS      The operation succeeds.\r
  @retval Others           The operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcGetSlotInfo (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
     OUT UINT8                 *FirstBar,\r
     OUT UINT8                 *SlotNum\r
  );\r
\r
/**\r
  Read/Write specified SD/MMC host controller mmio register.\r
\r
  @param[in]      PciIo        The PCI IO protocol instance.\r
  @param[in]      BarIndex     The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in]      Offset       The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in]      Read         A boolean to indicate it's read or write operation.\r
  @param[in]      Count        The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in, out] Data         For read operations, the destination buffer to store\r
                               the results. For write operations, the source buffer\r
                               to write data from. The caller is responsible for\r
                               having ownership of the data buffer and ensuring its\r
                               size not less than Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The read/write operation succeeds.\r
  @retval Others                The read/write operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcRwMmio (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
  IN     UINT8                 BarIndex,\r
  IN     UINT32                Offset,\r
  IN     BOOLEAN               Read,\r
  IN     UINT8                 Count,\r
  IN OUT VOID                  *Data\r
  );\r
\r
/**\r
  Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] OrData            The pointer to the data used to do OR operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The OR operation succeeds.\r
  @retval Others                The OR operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcOrMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *OrData\r
  );\r
\r
/**\r
  Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] AndData           The pointer to the data used to do AND operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The AND operation succeeds.\r
  @retval Others                The AND operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcAndMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *AndData\r
  );\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  BarIndex      The BAR index of the standard PCI Configuration\r
                            header to use as the base address for the memory\r
                            operation to perform.\r
  @param[in]  Offset        The offset within the selected BAR to start the\r
                            memory operation.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
  @param[in]  Timeout       The time out value for wait memory set, uses 1\r
                            microsecond as a unit.\r
\r
  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout\r
                            range.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcWaitMmioSet (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     BarIndex,\r
  IN  UINT32                    Offset,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue,\r
  IN  UINT64                    Timeout\r
  );\r
\r
/**\r
  Get the controller version information from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Version         The buffer to store the version information.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetControllerVersion (\r
  IN  EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN  UINT8                Slot,\r
  OUT UINT16               *Version\r
  );\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcEnableInterrupt (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetCapability (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Get the maximum current capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] MaxCurrent      The buffer to store the maximum current capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetMaxCurrent (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT UINT64               *MaxCurrent\r
  );\r
\r
/**\r
  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  Slot          The slot number of the SD card to send the command to.\r
  @param[out] MediaPresent  The pointer to the media present boolean value.\r
\r
  @retval EFI_SUCCESS       There is no media change happened.\r
  @retval EFI_MEDIA_CHANGED There is media change happened.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcCardDetect (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
     OUT BOOLEAN            *MediaPresent\r
  );\r
\r
/**\r
  Stop SD/MMC card clock.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.\r
  @retval Others            Fail to stop SD/MMC clock.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcStopClock (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  SD/MMC card clock supply.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.\r
  @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcClockSupply (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT64                 ClockFreq,\r
  IN UINT32                 BaseClkFreq,\r
  IN UINT16                 ControllerVer\r
  );\r
\r
/**\r
  SD/MMC bus power control.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] PowerCtrl      The value setting to the power control register.\r
\r
  @retval TRUE              There is a SD/MMC card attached.\r
  @retval FALSE             There is no a SD/MMC card attached.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcPowerControl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT8                  PowerCtrl\r
  );\r
\r
/**\r
  Set the SD/MMC bus width.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
\r
  @retval EFI_SUCCESS       The bus width is set successfully.\r
  @retval Others            The bus width isn't set successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcSetBusWidth (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT16                 BusWidth\r
  );\r
\r
/**\r
  Supply SD/MMC card with lowest clock frequency at initialization.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.\r
  @param[in] ControllerVer  The version of host controller.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitClockFreq (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT32                 BaseClkFreq,\r
  IN UINT16                 ControllerVer\r
  );\r
\r
/**\r
  Supply SD/MMC card with maximum voltage at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Capability     The capability of the slot.\r
\r
  @retval EFI_SUCCESS       The voltage is supplied successfully.\r
  @retval Others            The voltage isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitPowerVoltage (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_HC_SLOT_CAP     Capability\r
  );\r
\r
/**\r
  Initialize the Timeout Control register with most conservative value at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The timeout control register is configured successfully.\r
  @retval Others            The timeout control register isn't configured successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitTimeoutCtrl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Set SD Host Controller control 2 registry according to selected speed.\r
\r
  @param[in] ControllerHandle The handle of the controller.\r
  @param[in] PciIo            The PCI IO protocol instance.\r
  @param[in] Slot             The slot number of the SD card to send the command to.\r
  @param[in] Timing           The timing to select.\r
\r
  @retval EFI_SUCCESS         The timing is set successfully.\r
  @retval Others              The timing isn't set successfully.\r
**/\r
EFI_STATUS\r
SdMmcHcUhsSignaling (\r
  IN EFI_HANDLE             ControllerHandle,\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_BUS_MODE        Timing\r
  );\r
\r
#endif\r
Commit	Line	Data
48555339 FT	1	/** @file\r
	2	\r
	3	Provides some data structure definitions used by the SD/MMC host controller driver.\r
	4	\r
690d60c0	5	Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
48555339 FT	6	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
	7	This program and the accompanying materials\r
	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	#ifndef _SD_MMC_PCI_HCI_H_\r
	18	#define _SD_MMC_PCI_HCI_H_\r
	19	\r
	20	//\r
	21	// SD Host Controller SlotInfo Register Offset\r
	22	//\r
	23	#define SD_MMC_HC_SLOT_OFFSET 0x40\r
	24	\r
	25	#define SD_MMC_HC_MAX_SLOT 6\r
	26	\r
	27	//\r
	28	// SD Host Controller MMIO Register Offset\r
	29	//\r
	30	#define SD_MMC_HC_SDMA_ADDR 0x00\r
	31	#define SD_MMC_HC_ARG2 0x00\r
	32	#define SD_MMC_HC_BLK_SIZE 0x04\r
	33	#define SD_MMC_HC_BLK_COUNT 0x06\r
	34	#define SD_MMC_HC_ARG1 0x08\r
	35	#define SD_MMC_HC_TRANS_MOD 0x0C\r
	36	#define SD_MMC_HC_COMMAND 0x0E\r
	37	#define SD_MMC_HC_RESPONSE 0x10\r
	38	#define SD_MMC_HC_BUF_DAT_PORT 0x20\r
	39	#define SD_MMC_HC_PRESENT_STATE 0x24\r
	40	#define SD_MMC_HC_HOST_CTRL1 0x28\r
	41	#define SD_MMC_HC_POWER_CTRL 0x29\r
	42	#define SD_MMC_HC_BLK_GAP_CTRL 0x2A\r
	43	#define SD_MMC_HC_WAKEUP_CTRL 0x2B\r
	44	#define SD_MMC_HC_CLOCK_CTRL 0x2C\r
	45	#define SD_MMC_HC_TIMEOUT_CTRL 0x2E\r
	46	#define SD_MMC_HC_SW_RST 0x2F\r
	47	#define SD_MMC_HC_NOR_INT_STS 0x30\r
	48	#define SD_MMC_HC_ERR_INT_STS 0x32\r
	49	#define SD_MMC_HC_NOR_INT_STS_EN 0x34\r
	50	#define SD_MMC_HC_ERR_INT_STS_EN 0x36\r
	51	#define SD_MMC_HC_NOR_INT_SIG_EN 0x38\r
	52	#define SD_MMC_HC_ERR_INT_SIG_EN 0x3A\r
	53	#define SD_MMC_HC_AUTO_CMD_ERR_STS 0x3C\r
	54	#define SD_MMC_HC_HOST_CTRL2 0x3E\r
	55	#define SD_MMC_HC_CAP 0x40\r
	56	#define SD_MMC_HC_MAX_CURRENT_CAP 0x48\r
	57	#define SD_MMC_HC_FORCE_EVT_AUTO_CMD 0x50\r
	58	#define SD_MMC_HC_FORCE_EVT_ERR_INT 0x52\r
	59	#define SD_MMC_HC_ADMA_ERR_STS 0x54\r
	60	#define SD_MMC_HC_ADMA_SYS_ADDR 0x58\r
	61	#define SD_MMC_HC_PRESET_VAL 0x60\r
	62	#define SD_MMC_HC_SHARED_BUS_CTRL 0xE0\r
	63	#define SD_MMC_HC_SLOT_INT_STS 0xFC\r
	64	#define SD_MMC_HC_CTRL_VER 0xFE\r
	65	\r
a4708009 TM	66	//\r
	67	// SD Host Controller bits to HOST_CTRL2 register\r
	68	//\r
	69	#define SD_MMC_HC_CTRL_UHS_MASK 0x0007\r
	70	#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000\r
	71	#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001\r
	72	#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002\r
	73	#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003\r
	74	#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004\r
	75	#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000\r
	76	#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001\r
	77	#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004\r
	78	#define SD_MMC_HC_CTRL_MMC_HS200 0x0003\r
	79	#define SD_MMC_HC_CTRL_MMC_HS400 0x0005\r
	80	\r
48555339 FT	81	//\r
48555339 FT	82	// The transfer modes supported by SD Host Controller\r
48555339 FT	83	//\r
	84	typedef enum {\r
	85	SdMmcNoData,\r
	86	SdMmcPioMode,\r
	87	SdMmcSdmaMode,\r
690d60c0 AS	88	SdMmcAdma32bMode,\r
	89	SdMmcAdma64bV3Mode,\r
	90	SdMmcAdma64bV4Mode\r
48555339 FT	91	} SD_MMC_HC_TRANSFER_MODE;\r
48555339 FT	92	\r
690d60c0 AS	93	//\r
	94	// The ADMA transfer lengths supported by SD Host Controller\r
	95	//\r
	96	typedef enum {\r
	97	SdMmcAdmaLen16b,\r
	98	SdMmcAdmaLen26b\r
	99	} SD_MMC_HC_ADMA_LENGTH_MODE;\r
	100	\r
48555339 FT	101	//\r
	102	// The maximum data length of each descriptor line\r
	103	//\r
b5547b9c AS	104	#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB\r
b5547b9c AS	105	#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB\r
48555339	106	\r
b5547b9c AS	107	//\r
	108	// ADMA descriptor for 32b addressing.\r
	109	//\r
48555339 FT	110	typedef struct {\r
	111	UINT32 Valid:1;\r
	112	UINT32 End:1;\r
	113	UINT32 Int:1;\r
	114	UINT32 Reserved:1;\r
	115	UINT32 Act:2;\r
b5547b9c AS	116	UINT32 UpperLength:10;\r
b5547b9c AS	117	UINT32 LowerLength:16;\r
48555339	118	UINT32 Address;\r
b5547b9c AS	119	} SD_MMC_HC_ADMA_32_DESC_LINE;\r
	120	\r
	121	//\r
	122	// ADMA descriptor for 64b addressing.\r
	123	//\r
690d60c0 AS	124	typedef struct {\r
	125	UINT32 Valid:1;\r
	126	UINT32 End:1;\r
	127	UINT32 Int:1;\r
	128	UINT32 Reserved:1;\r
	129	UINT32 Act:2;\r
	130	UINT32 UpperLength:10;\r
	131	UINT32 LowerLength:16;\r
	132	UINT32 LowerAddress;\r
	133	UINT32 UpperAddress;\r
	134	} SD_MMC_HC_ADMA_64_V3_DESC_LINE;\r
	135	\r
b5547b9c AS	136	typedef struct {\r
	137	UINT32 Valid:1;\r
	138	UINT32 End:1;\r
	139	UINT32 Int:1;\r
	140	UINT32 Reserved:1;\r
	141	UINT32 Act:2;\r
	142	UINT32 UpperLength:10;\r
	143	UINT32 LowerLength:16;\r
	144	UINT32 LowerAddress;\r
	145	UINT32 UpperAddress;\r
	146	UINT32 Reserved1;\r
690d60c0	147	} SD_MMC_HC_ADMA_64_V4_DESC_LINE;\r
48555339 FT	148	\r
	149	#define SD_MMC_SDMA_BOUNDARY 512 * 1024\r
	150	#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
	151	\r
	152	typedef struct {\r
	153	UINT8 FirstBar:3; // bit 0:2\r
	154	UINT8 Reserved:1; // bit 3\r
	155	UINT8 SlotNum:3; // bit 4:6\r
	156	UINT8 Reserved1:1; // bit 7\r
	157	} SD_MMC_HC_SLOT_INFO;\r
	158	\r
	159	typedef struct {\r
	160	UINT32 TimeoutFreq:6; // bit 0:5\r
	161	UINT32 Reserved:1; // bit 6\r
	162	UINT32 TimeoutUnit:1; // bit 7\r
	163	UINT32 BaseClkFreq:8; // bit 8:15\r
	164	UINT32 MaxBlkLen:2; // bit 16:17\r
	165	UINT32 BusWidth8:1; // bit 18\r
	166	UINT32 Adma2:1; // bit 19\r
	167	UINT32 Reserved2:1; // bit 20\r
	168	UINT32 HighSpeed:1; // bit 21\r
	169	UINT32 Sdma:1; // bit 22\r
	170	UINT32 SuspRes:1; // bit 23\r
	171	UINT32 Voltage33:1; // bit 24\r
	172	UINT32 Voltage30:1; // bit 25\r
	173	UINT32 Voltage18:1; // bit 26\r
b5547b9c AS	174	UINT32 SysBus64V4:1; // bit 27\r
b5547b9c AS	175	UINT32 SysBus64V3:1; // bit 28\r
48555339 FT	176	UINT32 AsyncInt:1; // bit 29\r
	177	UINT32 SlotType:2; // bit 30:31\r
	178	UINT32 Sdr50:1; // bit 32\r
	179	UINT32 Sdr104:1; // bit 33\r
	180	UINT32 Ddr50:1; // bit 34\r
b5547b9c	181	UINT32 Reserved3:1; // bit 35\r
48555339 FT	182	UINT32 DriverTypeA:1; // bit 36\r
	183	UINT32 DriverTypeC:1; // bit 37\r
	184	UINT32 DriverTypeD:1; // bit 38\r
	185	UINT32 DriverType4:1; // bit 39\r
	186	UINT32 TimerCount:4; // bit 40:43\r
b5547b9c	187	UINT32 Reserved4:1; // bit 44\r
48555339 FT	188	UINT32 TuningSDR50:1; // bit 45\r
	189	UINT32 RetuningMod:2; // bit 46:47\r
	190	UINT32 ClkMultiplier:8; // bit 48:55\r
b5547b9c	191	UINT32 Reserved5:7; // bit 56:62\r
48555339 FT	192	UINT32 Hs400:1; // bit 63\r
	193	} SD_MMC_HC_SLOT_CAP;\r
	194	\r
bdf038cc JB	195	//\r
	196	// SD Host controller version\r
	197	//\r
b5547b9c AS	198	#define SD_MMC_HC_CTRL_VER_100 0x00\r
	199	#define SD_MMC_HC_CTRL_VER_200 0x01\r
	200	#define SD_MMC_HC_CTRL_VER_300 0x02\r
	201	#define SD_MMC_HC_CTRL_VER_400 0x03\r
	202	#define SD_MMC_HC_CTRL_VER_410 0x04\r
	203	#define SD_MMC_HC_CTRL_VER_420 0x05\r
	204	\r
	205	//\r
	206	// SD Host controller V4 enhancements\r
	207	//\r
	208	#define SD_MMC_HC_V4_EN BIT12\r
	209	#define SD_MMC_HC_64_ADDR_EN BIT13\r
	210	#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
bdf038cc	211	\r
48555339 FT	212	/**\r
	213	Dump the content of SD/MMC host controller's Capability Register.\r
	214	\r
	215	@param[in] Slot The slot number of the SD card to send the command to.\r
	216	@param[in] Capability The buffer to store the capability data.\r
	217	\r
	218	**/\r
	219	VOID\r
	220	DumpCapabilityReg (\r
	221	IN UINT8 Slot,\r
	222	IN SD_MMC_HC_SLOT_CAP *Capability\r
	223	);\r
	224	\r
	225	/**\r
	226	Read SlotInfo register from SD/MMC host controller pci config space.\r
	227	\r
	228	@param[in] PciIo The PCI IO protocol instance.\r
	229	@param[out] FirstBar The buffer to store the first BAR value.\r
	230	@param[out] SlotNum The buffer to store the supported slot number.\r
	231	\r
	232	@retval EFI_SUCCESS The operation succeeds.\r
	233	@retval Others The operation fails.\r
	234	\r
	235	**/\r
	236	EFI_STATUS\r
	237	EFIAPI\r
	238	SdMmcHcGetSlotInfo (\r
	239	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	240	OUT UINT8 *FirstBar,\r
	241	OUT UINT8 *SlotNum\r
	242	);\r
	243	\r
	244	/**\r
	245	Read/Write specified SD/MMC host controller mmio register.\r
	246	\r
	247	@param[in] PciIo The PCI IO protocol instance.\r
	248	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
	249	header to use as the base address for the memory\r
	250	operation to perform.\r
	251	@param[in] Offset The offset within the selected BAR to start the\r
	252	memory operation.\r
	253	@param[in] Read A boolean to indicate it's read or write operation.\r
	254	@param[in] Count The width of the mmio register in bytes.\r
	255	Must be 1, 2 , 4 or 8 bytes.\r
	256	@param[in, out] Data For read operations, the destination buffer to store\r
	257	the results. For write operations, the source buffer\r
	258	to write data from. The caller is responsible for\r
	259	having ownership of the data buffer and ensuring its\r
	260	size not less than Count bytes.\r
	261	\r
	262	@retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
	263	@retval EFI_SUCCESS The read/write operation succeeds.\r
	264	@retval Others The read/write operation fails.\r
	265	\r
	266	**/\r
	267	EFI_STATUS\r
	268	EFIAPI\r
	269	SdMmcHcRwMmio (\r
	270	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	271	IN UINT8 BarIndex,\r
	272	IN UINT32 Offset,\r
	273	IN BOOLEAN Read,\r
	274	IN UINT8 Count,\r
	275	IN OUT VOID *Data\r
276	);\r
277	\r
278	/**\r
279	Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
280	\r
281	@param[in] PciIo The PCI IO protocol instance.\r
282	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
283	header to use as the base address for the memory\r
284	operation to perform.\r
285	@param[in] Offset The offset within the selected BAR to start the\r
286	memory operation.\r
287	@param[in] Count The width of the mmio register in bytes.\r
288	Must be 1, 2 , 4 or 8 bytes.\r
289	@param[in] OrData The pointer to the data used to do OR operation.\r
290	The caller is responsible for having ownership of\r
291	the data buffer and ensuring its size not less than\r
292	Count bytes.\r
293	\r
294	@retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
295	@retval EFI_SUCCESS The OR operation succeeds.\r
296	@retval Others The OR operation fails.\r
297	\r
298	**/\r
299	EFI_STATUS\r
300	EFIAPI\r
301	SdMmcHcOrMmio (\r
302	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
303	IN UINT8 BarIndex,\r
304	IN UINT32 Offset,\r
305	IN UINT8 Count,\r
306	IN VOID *OrData\r
307	);\r
308	\r
309	/**\r
310	Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
311	\r
312	@param[in] PciIo The PCI IO protocol instance.\r
313	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
314	header to use as the base address for the memory\r
315	operation to perform.\r
316	@param[in] Offset The offset within the selected BAR to start the\r
317	memory operation.\r
318	@param[in] Count The width of the mmio register in bytes.\r
319	Must be 1, 2 , 4 or 8 bytes.\r
320	@param[in] AndData The pointer to the data used to do AND operation.\r
321	The caller is responsible for having ownership of\r
322	the data buffer and ensuring its size not less than\r
323	Count bytes.\r
324	\r
325	@retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
326	@retval EFI_SUCCESS The AND operation succeeds.\r
327	@retval Others The AND operation fails.\r
328	\r
329	**/\r
330	EFI_STATUS\r
331	EFIAPI\r
332	SdMmcHcAndMmio (\r
333	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
334	IN UINT8 BarIndex,\r
335	IN UINT32 Offset,\r
336	IN UINT8 Count,\r
337	IN VOID *AndData\r
338	);\r
339	\r
340	/**\r
341	Wait for the value of the specified MMIO register set to the test value.\r
342	\r
343	@param[in] PciIo The PCI IO protocol instance.\r
344	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
345	header to use as the base address for the memory\r
346	operation to perform.\r
347	@param[in] Offset The offset within the selected BAR to start the\r
348	memory operation.\r
349	@param[in] Count The width of the mmio register in bytes.\r
350	Must be 1, 2, 4 or 8 bytes.\r
351	@param[in] MaskValue The mask value of memory.\r
352	@param[in] TestValue The test value of memory.\r
353	@param[in] Timeout The time out value for wait memory set, uses 1\r
354	microsecond as a unit.\r
355	\r
356	@retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r
357	range.\r
358	@retval EFI_SUCCESS The MMIO register has expected value.\r
359	@retval Others The MMIO operation fails.\r
360	\r
361	**/\r
362	EFI_STATUS\r
363	EFIAPI\r
364	SdMmcHcWaitMmioSet (\r
365	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
366	IN UINT8 BarIndex,\r
367	IN UINT32 Offset,\r
368	IN UINT8 Count,\r
369	IN UINT64 MaskValue,\r
370	IN UINT64 TestValue,\r
371	IN UINT64 Timeout\r
372	);\r
373	\r
b5547b9c AS	374	/**\r
	375	Get the controller version information from the specified slot.\r
	376	\r
	377	@param[in] PciIo The PCI IO protocol instance.\r
	378	@param[in] Slot The slot number of the SD card to send the command to.\r
	379	@param[out] Version The buffer to store the version information.\r
	380	\r
	381	@retval EFI_SUCCESS The operation executes successfully.\r
	382	@retval Others The operation fails.\r
	383	\r
	384	**/\r
	385	EFI_STATUS\r
	386	SdMmcHcGetControllerVersion (\r
	387	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	388	IN UINT8 Slot,\r
	389	OUT UINT16 *Version\r
	390	);\r
	391	\r
48555339 FT	392	/**\r
	393	Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
	394	register.\r
	395	\r
	396	@param[in] PciIo The PCI IO protocol instance.\r
	397	@param[in] Slot The slot number of the SD card to send the command to.\r
	398	\r
	399	@retval EFI_SUCCESS The operation executes successfully.\r
	400	@retval Others The operation fails.\r
	401	\r
	402	**/\r
	403	EFI_STATUS\r
	404	SdMmcHcEnableInterrupt (\r
	405	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	406	IN UINT8 Slot\r
	407	);\r
	408	\r
	409	/**\r
	410	Get the capability data from the specified slot.\r
	411	\r
	412	@param[in] PciIo The PCI IO protocol instance.\r
	413	@param[in] Slot The slot number of the SD card to send the command to.\r
	414	@param[out] Capability The buffer to store the capability data.\r
	415	\r
	416	@retval EFI_SUCCESS The operation executes successfully.\r
	417	@retval Others The operation fails.\r
	418	\r
	419	**/\r
	420	EFI_STATUS\r
	421	SdMmcHcGetCapability (\r
	422	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	423	IN UINT8 Slot,\r
	424	OUT SD_MMC_HC_SLOT_CAP *Capability\r
	425	);\r
	426	\r
	427	/**\r
	428	Get the maximum current capability data from the specified slot.\r
	429	\r
	430	@param[in] PciIo The PCI IO protocol instance.\r
	431	@param[in] Slot The slot number of the SD card to send the command to.\r
	432	@param[out] MaxCurrent The buffer to store the maximum current capability data.\r
	433	\r
	434	@retval EFI_SUCCESS The operation executes successfully.\r
	435	@retval Others The operation fails.\r
	436	\r
	437	**/\r
	438	EFI_STATUS\r
	439	SdMmcHcGetMaxCurrent (\r
	440	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	441	IN UINT8 Slot,\r
	442	OUT UINT64 *MaxCurrent\r
	443	);\r
	444	\r
	445	/**\r
	446	Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
	447	slot.\r
	448	\r
	449	Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
	450	\r
	451	@param[in] PciIo The PCI IO protocol instance.\r
	452	@param[in] Slot The slot number of the SD card to send the command to.\r
	453	@param[out] MediaPresent The pointer to the media present boolean value.\r
	454	\r
	455	@retval EFI_SUCCESS There is no media change happened.\r
456	@retval EFI_MEDIA_CHANGED There is media change happened.\r
457	@retval Others The detection fails.\r
458	\r
459	**/\r
460	EFI_STATUS\r
461	SdMmcHcCardDetect (\r
462	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
463	IN UINT8 Slot,\r
464	OUT BOOLEAN *MediaPresent\r
465	);\r
466	\r
467	/**\r
468	Stop SD/MMC card clock.\r
469	\r
470	Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
471	\r
472	@param[in] PciIo The PCI IO protocol instance.\r
473	@param[in] Slot The slot number of the SD card to send the command to.\r
474	\r
475	@retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r
476	@retval Others Fail to stop SD/MMC clock.\r
477	\r
478	**/\r
479	EFI_STATUS\r
480	SdMmcHcStopClock (\r
481	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
482	IN UINT8 Slot\r
483	);\r
484	\r
485	/**\r
486	SD/MMC card clock supply.\r
487	\r
488	Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
489	\r
490	@param[in] PciIo The PCI IO protocol instance.\r
491	@param[in] Slot The slot number of the SD card to send the command to.\r
492	@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
7f3b0bad	493	@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
b5547b9c	494	@param[in] ControllerVer The version of host controller.\r
48555339 FT	495	\r
	496	@retval EFI_SUCCESS The clock is supplied successfully.\r
	497	@retval Others The clock isn't supplied successfully.\r
	498	\r
	499	**/\r
	500	EFI_STATUS\r
	501	SdMmcHcClockSupply (\r
	502	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	503	IN UINT8 Slot,\r
	504	IN UINT64 ClockFreq,\r
b5547b9c AS	505	IN UINT32 BaseClkFreq,\r
b5547b9c AS	506	IN UINT16 ControllerVer\r
48555339 FT	507	);\r
	508	\r
	509	/**\r
	510	SD/MMC bus power control.\r
	511	\r
	512	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
	513	\r
	514	@param[in] PciIo The PCI IO protocol instance.\r
	515	@param[in] Slot The slot number of the SD card to send the command to.\r
	516	@param[in] PowerCtrl The value setting to the power control register.\r
	517	\r
	518	@retval TRUE There is a SD/MMC card attached.\r
	519	@retval FALSE There is no a SD/MMC card attached.\r
	520	\r
	521	**/\r
	522	EFI_STATUS\r
	523	SdMmcHcPowerControl (\r
	524	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	525	IN UINT8 Slot,\r
	526	IN UINT8 PowerCtrl\r
	527	);\r
	528	\r
	529	/**\r
	530	Set the SD/MMC bus width.\r
	531	\r
	532	Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
	533	\r
	534	@param[in] PciIo The PCI IO protocol instance.\r
	535	@param[in] Slot The slot number of the SD card to send the command to.\r
	536	@param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
	537	\r
	538	@retval EFI_SUCCESS The bus width is set successfully.\r
	539	@retval Others The bus width isn't set successfully.\r
	540	\r
	541	**/\r
	542	EFI_STATUS\r
	543	SdMmcHcSetBusWidth (\r
	544	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	545	IN UINT8 Slot,\r
	546	IN UINT16 BusWidth\r
	547	);\r
	548	\r
	549	/**\r
	550	Supply SD/MMC card with lowest clock frequency at initialization.\r
	551	\r
	552	@param[in] PciIo The PCI IO protocol instance.\r
	553	@param[in] Slot The slot number of the SD card to send the command to.\r
7f3b0bad	554	@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
b5547b9c	555	@param[in] ControllerVer The version of host controller.\r
48555339 FT	556	\r
	557	@retval EFI_SUCCESS The clock is supplied successfully.\r
	558	@retval Others The clock isn't supplied successfully.\r
	559	\r
	560	**/\r
	561	EFI_STATUS\r
	562	SdMmcHcInitClockFreq (\r
	563	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	564	IN UINT8 Slot,\r
b5547b9c AS	565	IN UINT32 BaseClkFreq,\r
b5547b9c AS	566	IN UINT16 ControllerVer\r
48555339 FT	567	);\r
	568	\r
	569	/**\r
	570	Supply SD/MMC card with maximum voltage at initialization.\r
	571	\r
	572	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
	573	\r
	574	@param[in] PciIo The PCI IO protocol instance.\r
	575	@param[in] Slot The slot number of the SD card to send the command to.\r
	576	@param[in] Capability The capability of the slot.\r
	577	\r
	578	@retval EFI_SUCCESS The voltage is supplied successfully.\r
	579	@retval Others The voltage isn't supplied successfully.\r
	580	\r
	581	**/\r
	582	EFI_STATUS\r
	583	SdMmcHcInitPowerVoltage (\r
	584	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	585	IN UINT8 Slot,\r
	586	IN SD_MMC_HC_SLOT_CAP Capability\r
	587	);\r
	588	\r
	589	/**\r
	590	Initialize the Timeout Control register with most conservative value at initialization.\r
	591	\r
	592	Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
	593	\r
	594	@param[in] PciIo The PCI IO protocol instance.\r
	595	@param[in] Slot The slot number of the SD card to send the command to.\r
	596	\r
	597	@retval EFI_SUCCESS The timeout control register is configured successfully.\r
	598	@retval Others The timeout control register isn't configured successfully.\r
	599	\r
	600	**/\r
	601	EFI_STATUS\r
	602	SdMmcHcInitTimeoutCtrl (\r
	603	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	604	IN UINT8 Slot\r
	605	);\r
	606	\r
a4708009 TM	607	/**\r
	608	Set SD Host Controller control 2 registry according to selected speed.\r
	609	\r
	610	@param[in] ControllerHandle The handle of the controller.\r
	611	@param[in] PciIo The PCI IO protocol instance.\r
	612	@param[in] Slot The slot number of the SD card to send the command to.\r
	613	@param[in] Timing The timing to select.\r
	614	\r
	615	@retval EFI_SUCCESS The timing is set successfully.\r
	616	@retval Others The timing isn't set successfully.\r
	617	**/\r
	618	EFI_STATUS\r
	619	SdMmcHcUhsSignaling (\r
	620	IN EFI_HANDLE ControllerHandle,\r
	621	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	622	IN UINT8 Slot,\r
	623	IN SD_MMC_BUS_MODE Timing\r
	624	);\r
	625	\r
48555339	626	#endif\r