[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.h

/** @file\r
\r
  Provides some data structure definitions used by the SD/MMC host controller driver.\r
\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _SD_MMC_PCI_HCI_H_\r
#define _SD_MMC_PCI_HCI_H_\r
\r
//\r
// SD Host Controller SlotInfo Register Offset\r
//\r
#define SD_MMC_HC_SLOT_OFFSET         0x40\r
\r
#define SD_MMC_HC_MAX_SLOT            6\r
\r
//\r
// SD Host Controller MMIO Register Offset\r
//\r
#define SD_MMC_HC_SDMA_ADDR           0x00\r
#define SD_MMC_HC_ARG2                0x00\r
#define SD_MMC_HC_BLK_SIZE            0x04\r
#define SD_MMC_HC_BLK_COUNT           0x06\r
#define SD_MMC_HC_ARG1                0x08\r
#define SD_MMC_HC_TRANS_MOD           0x0C\r
#define SD_MMC_HC_COMMAND             0x0E\r
#define SD_MMC_HC_RESPONSE            0x10\r
#define SD_MMC_HC_BUF_DAT_PORT        0x20\r
#define SD_MMC_HC_PRESENT_STATE       0x24\r
#define SD_MMC_HC_HOST_CTRL1          0x28\r
#define SD_MMC_HC_POWER_CTRL          0x29\r
#define SD_MMC_HC_BLK_GAP_CTRL        0x2A\r
#define SD_MMC_HC_WAKEUP_CTRL         0x2B\r
#define SD_MMC_HC_CLOCK_CTRL          0x2C\r
#define SD_MMC_HC_TIMEOUT_CTRL        0x2E\r
#define SD_MMC_HC_SW_RST              0x2F\r
#define SD_MMC_HC_NOR_INT_STS         0x30\r
#define SD_MMC_HC_ERR_INT_STS         0x32\r
#define SD_MMC_HC_NOR_INT_STS_EN      0x34\r
#define SD_MMC_HC_ERR_INT_STS_EN      0x36\r
#define SD_MMC_HC_NOR_INT_SIG_EN      0x38\r
#define SD_MMC_HC_ERR_INT_SIG_EN      0x3A\r
#define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C\r
#define SD_MMC_HC_HOST_CTRL2          0x3E\r
#define SD_MMC_HC_CAP                 0x40\r
#define SD_MMC_HC_MAX_CURRENT_CAP     0x48\r
#define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50\r
#define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52\r
#define SD_MMC_HC_ADMA_ERR_STS        0x54\r
#define SD_MMC_HC_ADMA_SYS_ADDR       0x58\r
#define SD_MMC_HC_PRESET_VAL          0x60\r
#define SD_MMC_HC_SHARED_BUS_CTRL     0xE0\r
#define SD_MMC_HC_SLOT_INT_STS        0xFC\r
#define SD_MMC_HC_CTRL_VER            0xFE\r
\r
//\r
// The transfer modes supported by SD Host Controller\r
// Simplified Spec 3.0 Table 1-2\r
//\r
typedef enum {\r
  SdMmcNoData,\r
  SdMmcPioMode,\r
  SdMmcSdmaMode,\r
  SdMmcAdmaMode\r
} SD_MMC_HC_TRANSFER_MODE;\r
\r
//\r
// The maximum data length of each descriptor line\r
//\r
#define ADMA_MAX_DATA_PER_LINE     0x10000\r
\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 Reserved1:10;\r
  UINT32 Length:16;\r
  UINT32 Address;\r
} SD_MMC_HC_ADMA_DESC_LINE;\r
\r
#define SD_MMC_SDMA_BOUNDARY          512 * 1024\r
#define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))\r
\r
typedef struct {\r
  UINT8    FirstBar:3;        // bit 0:2\r
  UINT8    Reserved:1;        // bit 3\r
  UINT8    SlotNum:3;         // bit 4:6\r
  UINT8    Reserved1:1;       // bit 7\r
} SD_MMC_HC_SLOT_INFO;\r
\r
typedef struct {\r
  UINT32   TimeoutFreq:6;     // bit 0:5\r
  UINT32   Reserved:1;        // bit 6\r
  UINT32   TimeoutUnit:1;     // bit 7\r
  UINT32   BaseClkFreq:8;     // bit 8:15\r
  UINT32   MaxBlkLen:2;       // bit 16:17\r
  UINT32   BusWidth8:1;       // bit 18\r
  UINT32   Adma2:1;           // bit 19\r
  UINT32   Reserved2:1;       // bit 20\r
  UINT32   HighSpeed:1;       // bit 21\r
  UINT32   Sdma:1;            // bit 22\r
  UINT32   SuspRes:1;         // bit 23\r
  UINT32   Voltage33:1;       // bit 24\r
  UINT32   Voltage30:1;       // bit 25\r
  UINT32   Voltage18:1;       // bit 26\r
  UINT32   Reserved3:1;       // bit 27\r
  UINT32   SysBus64:1;        // bit 28\r
  UINT32   AsyncInt:1;        // bit 29\r
  UINT32   SlotType:2;        // bit 30:31\r
  UINT32   Sdr50:1;           // bit 32\r
  UINT32   Sdr104:1;          // bit 33\r
  UINT32   Ddr50:1;           // bit 34\r
  UINT32   Reserved4:1;       // bit 35\r
  UINT32   DriverTypeA:1;     // bit 36\r
  UINT32   DriverTypeC:1;     // bit 37\r
  UINT32   DriverTypeD:1;     // bit 38\r
  UINT32   DriverType4:1;     // bit 39\r
  UINT32   TimerCount:4;      // bit 40:43\r
  UINT32   Reserved5:1;       // bit 44\r
  UINT32   TuningSDR50:1;     // bit 45\r
  UINT32   RetuningMod:2;     // bit 46:47\r
  UINT32   ClkMultiplier:8;   // bit 48:55\r
  UINT32   Reserved6:7;       // bit 56:62\r
  UINT32   Hs400:1;           // bit 63\r
} SD_MMC_HC_SLOT_CAP;\r
\r
/**\r
  Dump the content of SD/MMC host controller's Capability Register.\r
\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[in]  Capability      The buffer to store the capability data.\r
\r
**/\r
VOID\r
DumpCapabilityReg (\r
  IN UINT8                Slot,\r
  IN SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Read SlotInfo register from SD/MMC host controller pci config space.\r
\r
  @param[in]  PciIo        The PCI IO protocol instance.\r
  @param[out] FirstBar     The buffer to store the first BAR value.\r
  @param[out] SlotNum      The buffer to store the supported slot number.\r
\r
  @retval EFI_SUCCESS      The operation succeeds.\r
  @retval Others           The operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcGetSlotInfo (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
     OUT UINT8                 *FirstBar,\r
     OUT UINT8                 *SlotNum\r
  );\r
\r
/**\r
  Read/Write specified SD/MMC host controller mmio register.\r
\r
  @param[in]      PciIo        The PCI IO protocol instance.\r
  @param[in]      BarIndex     The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in]      Offset       The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in]      Read         A boolean to indicate it's read or write operation.\r
  @param[in]      Count        The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in, out] Data         For read operations, the destination buffer to store\r
                               the results. For write operations, the source buffer\r
                               to write data from. The caller is responsible for\r
                               having ownership of the data buffer and ensuring its\r
                               size not less than Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The read/write operation succeeds.\r
  @retval Others                The read/write operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcRwMmio (\r
  IN     EFI_PCI_IO_PROTOCOL   *PciIo,\r
  IN     UINT8                 BarIndex,\r
  IN     UINT32                Offset,\r
  IN     BOOLEAN               Read,\r
  IN     UINT8                 Count,\r
  IN OUT VOID                  *Data\r
  );\r
\r
/**\r
  Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] OrData            The pointer to the data used to do OR operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The OR operation succeeds.\r
  @retval Others                The OR operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcOrMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *OrData\r
  );\r
\r
/**\r
  Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
\r
  @param[in] PciIo             The PCI IO protocol instance.\r
  @param[in] BarIndex          The BAR index of the standard PCI Configuration\r
                               header to use as the base address for the memory\r
                               operation to perform.\r
  @param[in] Offset            The offset within the selected BAR to start the\r
                               memory operation.\r
  @param[in] Count             The width of the mmio register in bytes.\r
                               Must be 1, 2 , 4 or 8 bytes.\r
  @param[in] AndData           The pointer to the data used to do AND operation.\r
                               The caller is responsible for having ownership of\r
                               the data buffer and ensuring its size not less than\r
                               Count bytes.\r
\r
  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
  @retval EFI_SUCCESS           The AND operation succeeds.\r
  @retval Others                The AND operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcAndMmio (\r
  IN  EFI_PCI_IO_PROTOCOL      *PciIo,\r
  IN  UINT8                    BarIndex,\r
  IN  UINT32                   Offset,\r
  IN  UINT8                    Count,\r
  IN  VOID                     *AndData\r
  );\r
\r
/**\r
  Wait for the value of the specified MMIO register set to the test value.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  BarIndex      The BAR index of the standard PCI Configuration\r
                            header to use as the base address for the memory\r
                            operation to perform.\r
  @param[in]  Offset        The offset within the selected BAR to start the\r
                            memory operation.\r
  @param[in]  Count         The width of the mmio register in bytes.\r
                            Must be 1, 2, 4 or 8 bytes.\r
  @param[in]  MaskValue     The mask value of memory.\r
  @param[in]  TestValue     The test value of memory.\r
  @param[in]  Timeout       The time out value for wait memory set, uses 1\r
                            microsecond as a unit.\r
\r
  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout\r
                            range.\r
  @retval EFI_SUCCESS       The MMIO register has expected value.\r
  @retval Others            The MMIO operation fails.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SdMmcHcWaitMmioSet (\r
  IN  EFI_PCI_IO_PROTOCOL       *PciIo,\r
  IN  UINT8                     BarIndex,\r
  IN  UINT32                    Offset,\r
  IN  UINT8                     Count,\r
  IN  UINT64                    MaskValue,\r
  IN  UINT64                    TestValue,\r
  IN  UINT64                    Timeout\r
  );\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcEnableInterrupt (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetCapability (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT SD_MMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Get the maximum current capability data from the specified slot.\r
\r
  @param[in]  PciIo           The PCI IO protocol instance.\r
  @param[in]  Slot            The slot number of the SD card to send the command to.\r
  @param[out] MaxCurrent      The buffer to store the maximum current capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcGetMaxCurrent (\r
  IN     EFI_PCI_IO_PROTOCOL  *PciIo,\r
  IN     UINT8                Slot,\r
     OUT UINT64               *MaxCurrent\r
  );\r
\r
/**\r
  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  PciIo         The PCI IO protocol instance.\r
  @param[in]  Slot          The slot number of the SD card to send the command to.\r
  @param[out] MediaPresent  The pointer to the media present boolean value.\r
\r
  @retval EFI_SUCCESS       There is no media change happened.\r
  @retval EFI_MEDIA_CHANGED There is media change happened.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcCardDetect (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
     OUT BOOLEAN            *MediaPresent\r
  );\r
\r
/**\r
  Stop SD/MMC card clock.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.\r
  @retval Others            Fail to stop SD/MMC clock.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcStopClock (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
/**\r
  SD/MMC card clock supply.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.\r
  @param[in] Capability     The capability of the slot.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcClockSupply (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT64                 ClockFreq,\r
  IN SD_MMC_HC_SLOT_CAP     Capability\r
  );\r
\r
/**\r
  SD/MMC bus power control.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] PowerCtrl      The value setting to the power control register.\r
\r
  @retval TRUE              There is a SD/MMC card attached.\r
  @retval FALSE             There is no a SD/MMC card attached.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcPowerControl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT8                  PowerCtrl\r
  );\r
\r
/**\r
  Set the SD/MMC bus width.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
\r
  @retval EFI_SUCCESS       The bus width is set successfully.\r
  @retval Others            The bus width isn't set successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcSetBusWidth (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN UINT16                 BusWidth\r
  );\r
\r
/**\r
  Supply SD/MMC card with lowest clock frequency at initialization.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Capability     The capability of the slot.\r
\r
  @retval EFI_SUCCESS       The clock is supplied successfully.\r
  @retval Others            The clock isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitClockFreq (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_HC_SLOT_CAP     Capability\r
  );\r
\r
/**\r
  Supply SD/MMC card with maximum voltage at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
  @param[in] Capability     The capability of the slot.\r
\r
  @retval EFI_SUCCESS       The voltage is supplied successfully.\r
  @retval Others            The voltage isn't supplied successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitPowerVoltage (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot,\r
  IN SD_MMC_HC_SLOT_CAP     Capability\r
  );\r
\r
/**\r
  Initialize the Timeout Control register with most conservative value at initialization.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
\r
  @param[in] PciIo          The PCI IO protocol instance.\r
  @param[in] Slot           The slot number of the SD card to send the command to.\r
\r
  @retval EFI_SUCCESS       The timeout control register is configured successfully.\r
  @retval Others            The timeout control register isn't configured successfully.\r
\r
**/\r
EFI_STATUS\r
SdMmcHcInitTimeoutCtrl (\r
  IN EFI_PCI_IO_PROTOCOL    *PciIo,\r
  IN UINT8                  Slot\r
  );\r
\r
#endif\r
Commit	Line	Data
48555339 FT	1	/** @file\r
	2	\r
	3	Provides some data structure definitions used by the SD/MMC host controller driver.\r
	4	\r
	5	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _SD_MMC_PCI_HCI_H_\r
	17	#define _SD_MMC_PCI_HCI_H_\r
	18	\r
	19	//\r
	20	// SD Host Controller SlotInfo Register Offset\r
	21	//\r
	22	#define SD_MMC_HC_SLOT_OFFSET 0x40\r
	23	\r
	24	#define SD_MMC_HC_MAX_SLOT 6\r
	25	\r
	26	//\r
	27	// SD Host Controller MMIO Register Offset\r
	28	//\r
	29	#define SD_MMC_HC_SDMA_ADDR 0x00\r
	30	#define SD_MMC_HC_ARG2 0x00\r
	31	#define SD_MMC_HC_BLK_SIZE 0x04\r
	32	#define SD_MMC_HC_BLK_COUNT 0x06\r
	33	#define SD_MMC_HC_ARG1 0x08\r
	34	#define SD_MMC_HC_TRANS_MOD 0x0C\r
	35	#define SD_MMC_HC_COMMAND 0x0E\r
	36	#define SD_MMC_HC_RESPONSE 0x10\r
	37	#define SD_MMC_HC_BUF_DAT_PORT 0x20\r
	38	#define SD_MMC_HC_PRESENT_STATE 0x24\r
	39	#define SD_MMC_HC_HOST_CTRL1 0x28\r
	40	#define SD_MMC_HC_POWER_CTRL 0x29\r
	41	#define SD_MMC_HC_BLK_GAP_CTRL 0x2A\r
	42	#define SD_MMC_HC_WAKEUP_CTRL 0x2B\r
	43	#define SD_MMC_HC_CLOCK_CTRL 0x2C\r
	44	#define SD_MMC_HC_TIMEOUT_CTRL 0x2E\r
	45	#define SD_MMC_HC_SW_RST 0x2F\r
	46	#define SD_MMC_HC_NOR_INT_STS 0x30\r
	47	#define SD_MMC_HC_ERR_INT_STS 0x32\r
	48	#define SD_MMC_HC_NOR_INT_STS_EN 0x34\r
	49	#define SD_MMC_HC_ERR_INT_STS_EN 0x36\r
	50	#define SD_MMC_HC_NOR_INT_SIG_EN 0x38\r
	51	#define SD_MMC_HC_ERR_INT_SIG_EN 0x3A\r
	52	#define SD_MMC_HC_AUTO_CMD_ERR_STS 0x3C\r
	53	#define SD_MMC_HC_HOST_CTRL2 0x3E\r
	54	#define SD_MMC_HC_CAP 0x40\r
	55	#define SD_MMC_HC_MAX_CURRENT_CAP 0x48\r
	56	#define SD_MMC_HC_FORCE_EVT_AUTO_CMD 0x50\r
	57	#define SD_MMC_HC_FORCE_EVT_ERR_INT 0x52\r
	58	#define SD_MMC_HC_ADMA_ERR_STS 0x54\r
	59	#define SD_MMC_HC_ADMA_SYS_ADDR 0x58\r
	60	#define SD_MMC_HC_PRESET_VAL 0x60\r
	61	#define SD_MMC_HC_SHARED_BUS_CTRL 0xE0\r
	62	#define SD_MMC_HC_SLOT_INT_STS 0xFC\r
	63	#define SD_MMC_HC_CTRL_VER 0xFE\r
	64	\r
65	//\r
66	// The transfer modes supported by SD Host Controller\r
67	// Simplified Spec 3.0 Table 1-2\r
68	//\r
69	typedef enum {\r
70	SdMmcNoData,\r
71	SdMmcPioMode,\r
72	SdMmcSdmaMode,\r
73	SdMmcAdmaMode\r
74	} SD_MMC_HC_TRANSFER_MODE;\r
75	\r
76	//\r
77	// The maximum data length of each descriptor line\r
78	//\r
79	#define ADMA_MAX_DATA_PER_LINE 0x10000\r
80	\r
81	typedef struct {\r
82	UINT32 Valid:1;\r
83	UINT32 End:1;\r
84	UINT32 Int:1;\r
85	UINT32 Reserved:1;\r
86	UINT32 Act:2;\r
87	UINT32 Reserved1:10;\r
88	UINT32 Length:16;\r
89	UINT32 Address;\r
90	} SD_MMC_HC_ADMA_DESC_LINE;\r
91	\r
92	#define SD_MMC_SDMA_BOUNDARY 512 * 1024\r
93	#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
94	\r
95	typedef struct {\r
96	UINT8 FirstBar:3; // bit 0:2\r
97	UINT8 Reserved:1; // bit 3\r
98	UINT8 SlotNum:3; // bit 4:6\r
99	UINT8 Reserved1:1; // bit 7\r
100	} SD_MMC_HC_SLOT_INFO;\r
101	\r
102	typedef struct {\r
103	UINT32 TimeoutFreq:6; // bit 0:5\r
104	UINT32 Reserved:1; // bit 6\r
105	UINT32 TimeoutUnit:1; // bit 7\r
106	UINT32 BaseClkFreq:8; // bit 8:15\r
107	UINT32 MaxBlkLen:2; // bit 16:17\r
108	UINT32 BusWidth8:1; // bit 18\r
109	UINT32 Adma2:1; // bit 19\r
110	UINT32 Reserved2:1; // bit 20\r
111	UINT32 HighSpeed:1; // bit 21\r
112	UINT32 Sdma:1; // bit 22\r
113	UINT32 SuspRes:1; // bit 23\r
114	UINT32 Voltage33:1; // bit 24\r
115	UINT32 Voltage30:1; // bit 25\r
116	UINT32 Voltage18:1; // bit 26\r
117	UINT32 Reserved3:1; // bit 27\r
118	UINT32 SysBus64:1; // bit 28\r
119	UINT32 AsyncInt:1; // bit 29\r
120	UINT32 SlotType:2; // bit 30:31\r
121	UINT32 Sdr50:1; // bit 32\r
122	UINT32 Sdr104:1; // bit 33\r
123	UINT32 Ddr50:1; // bit 34\r
124	UINT32 Reserved4:1; // bit 35\r
125	UINT32 DriverTypeA:1; // bit 36\r
126	UINT32 DriverTypeC:1; // bit 37\r
127	UINT32 DriverTypeD:1; // bit 38\r
128	UINT32 DriverType4:1; // bit 39\r
129	UINT32 TimerCount:4; // bit 40:43\r
130	UINT32 Reserved5:1; // bit 44\r
131	UINT32 TuningSDR50:1; // bit 45\r
132	UINT32 RetuningMod:2; // bit 46:47\r
133	UINT32 ClkMultiplier:8; // bit 48:55\r
134	UINT32 Reserved6:7; // bit 56:62\r
135	UINT32 Hs400:1; // bit 63\r
136	} SD_MMC_HC_SLOT_CAP;\r
137	\r
138	/**\r
139	Dump the content of SD/MMC host controller's Capability Register.\r
140	\r
141	@param[in] Slot The slot number of the SD card to send the command to.\r
142	@param[in] Capability The buffer to store the capability data.\r
143	\r
144	**/\r
145	VOID\r
146	DumpCapabilityReg (\r
147	IN UINT8 Slot,\r
148	IN SD_MMC_HC_SLOT_CAP *Capability\r
149	);\r
150	\r
151	/**\r
152	Read SlotInfo register from SD/MMC host controller pci config space.\r
153	\r
154	@param[in] PciIo The PCI IO protocol instance.\r
155	@param[out] FirstBar The buffer to store the first BAR value.\r
156	@param[out] SlotNum The buffer to store the supported slot number.\r
157	\r
158	@retval EFI_SUCCESS The operation succeeds.\r
159	@retval Others The operation fails.\r
160	\r
161	**/\r
162	EFI_STATUS\r
163	EFIAPI\r
164	SdMmcHcGetSlotInfo (\r
165	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
166	OUT UINT8 *FirstBar,\r
167	OUT UINT8 *SlotNum\r
168	);\r
169	\r
170	/**\r
171	Read/Write specified SD/MMC host controller mmio register.\r
172	\r
173	@param[in] PciIo The PCI IO protocol instance.\r
174	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
175	header to use as the base address for the memory\r
176	operation to perform.\r
177	@param[in] Offset The offset within the selected BAR to start the\r
178	memory operation.\r
179	@param[in] Read A boolean to indicate it's read or write operation.\r
180	@param[in] Count The width of the mmio register in bytes.\r
181	Must be 1, 2 , 4 or 8 bytes.\r
182	@param[in, out] Data For read operations, the destination buffer to store\r
183	the results. For write operations, the source buffer\r
184	to write data from. The caller is responsible for\r
185	having ownership of the data buffer and ensuring its\r
186	size not less than Count bytes.\r
187	\r
188	@retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.\r
189	@retval EFI_SUCCESS The read/write operation succeeds.\r
190	@retval Others The read/write operation fails.\r
191	\r
192	**/\r
193	EFI_STATUS\r
194	EFIAPI\r
195	SdMmcHcRwMmio (\r
196	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
197	IN UINT8 BarIndex,\r
198	IN UINT32 Offset,\r
199	IN BOOLEAN Read,\r
200	IN UINT8 Count,\r
201	IN OUT VOID *Data\r
202	);\r
203	\r
204	/**\r
205	Do OR operation with the value of the specified SD/MMC host controller mmio register.\r
206	\r
207	@param[in] PciIo The PCI IO protocol instance.\r
208	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
209	header to use as the base address for the memory\r
210	operation to perform.\r
211	@param[in] Offset The offset within the selected BAR to start the\r
212	memory operation.\r
213	@param[in] Count The width of the mmio register in bytes.\r
214	Must be 1, 2 , 4 or 8 bytes.\r
215	@param[in] OrData The pointer to the data used to do OR operation.\r
216	The caller is responsible for having ownership of\r
217	the data buffer and ensuring its size not less than\r
218	Count bytes.\r
219	\r
220	@retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.\r
221	@retval EFI_SUCCESS The OR operation succeeds.\r
222	@retval Others The OR operation fails.\r
223	\r
224	**/\r
225	EFI_STATUS\r
226	EFIAPI\r
227	SdMmcHcOrMmio (\r
228	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
229	IN UINT8 BarIndex,\r
230	IN UINT32 Offset,\r
231	IN UINT8 Count,\r
232	IN VOID *OrData\r
233	);\r
234	\r
235	/**\r
236	Do AND operation with the value of the specified SD/MMC host controller mmio register.\r
237	\r
238	@param[in] PciIo The PCI IO protocol instance.\r
239	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
240	header to use as the base address for the memory\r
241	operation to perform.\r
242	@param[in] Offset The offset within the selected BAR to start the\r
243	memory operation.\r
244	@param[in] Count The width of the mmio register in bytes.\r
245	Must be 1, 2 , 4 or 8 bytes.\r
246	@param[in] AndData The pointer to the data used to do AND operation.\r
247	The caller is responsible for having ownership of\r
248	the data buffer and ensuring its size not less than\r
249	Count bytes.\r
250	\r
251	@retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.\r
252	@retval EFI_SUCCESS The AND operation succeeds.\r
253	@retval Others The AND operation fails.\r
254	\r
255	**/\r
256	EFI_STATUS\r
257	EFIAPI\r
258	SdMmcHcAndMmio (\r
259	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
260	IN UINT8 BarIndex,\r
261	IN UINT32 Offset,\r
262	IN UINT8 Count,\r
263	IN VOID *AndData\r
264	);\r
265	\r
266	/**\r
267	Wait for the value of the specified MMIO register set to the test value.\r
268	\r
269	@param[in] PciIo The PCI IO protocol instance.\r
270	@param[in] BarIndex The BAR index of the standard PCI Configuration\r
271	header to use as the base address for the memory\r
272	operation to perform.\r
273	@param[in] Offset The offset within the selected BAR to start the\r
274	memory operation.\r
275	@param[in] Count The width of the mmio register in bytes.\r
276	Must be 1, 2, 4 or 8 bytes.\r
277	@param[in] MaskValue The mask value of memory.\r
278	@param[in] TestValue The test value of memory.\r
279	@param[in] Timeout The time out value for wait memory set, uses 1\r
280	microsecond as a unit.\r
281	\r
282	@retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r
283	range.\r
284	@retval EFI_SUCCESS The MMIO register has expected value.\r
285	@retval Others The MMIO operation fails.\r
286	\r
287	**/\r
288	EFI_STATUS\r
289	EFIAPI\r
290	SdMmcHcWaitMmioSet (\r
291	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
292	IN UINT8 BarIndex,\r
293	IN UINT32 Offset,\r
294	IN UINT8 Count,\r
295	IN UINT64 MaskValue,\r
296	IN UINT64 TestValue,\r
297	IN UINT64 Timeout\r
298	);\r
299	\r
48555339 FT	300	/**\r
	301	Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
	302	register.\r
	303	\r
	304	@param[in] PciIo The PCI IO protocol instance.\r
	305	@param[in] Slot The slot number of the SD card to send the command to.\r
	306	\r
	307	@retval EFI_SUCCESS The operation executes successfully.\r
	308	@retval Others The operation fails.\r
	309	\r
	310	**/\r
	311	EFI_STATUS\r
	312	SdMmcHcEnableInterrupt (\r
	313	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	314	IN UINT8 Slot\r
	315	);\r
	316	\r
	317	/**\r
	318	Get the capability data from the specified slot.\r
	319	\r
	320	@param[in] PciIo The PCI IO protocol instance.\r
	321	@param[in] Slot The slot number of the SD card to send the command to.\r
	322	@param[out] Capability The buffer to store the capability data.\r
	323	\r
	324	@retval EFI_SUCCESS The operation executes successfully.\r
	325	@retval Others The operation fails.\r
	326	\r
	327	**/\r
	328	EFI_STATUS\r
	329	SdMmcHcGetCapability (\r
	330	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	331	IN UINT8 Slot,\r
	332	OUT SD_MMC_HC_SLOT_CAP *Capability\r
	333	);\r
	334	\r
	335	/**\r
	336	Get the maximum current capability data from the specified slot.\r
	337	\r
	338	@param[in] PciIo The PCI IO protocol instance.\r
	339	@param[in] Slot The slot number of the SD card to send the command to.\r
	340	@param[out] MaxCurrent The buffer to store the maximum current capability data.\r
	341	\r
	342	@retval EFI_SUCCESS The operation executes successfully.\r
	343	@retval Others The operation fails.\r
	344	\r
	345	**/\r
	346	EFI_STATUS\r
	347	SdMmcHcGetMaxCurrent (\r
	348	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	349	IN UINT8 Slot,\r
	350	OUT UINT64 *MaxCurrent\r
	351	);\r
	352	\r
	353	/**\r
	354	Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller\r
	355	slot.\r
	356	\r
	357	Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
	358	\r
	359	@param[in] PciIo The PCI IO protocol instance.\r
	360	@param[in] Slot The slot number of the SD card to send the command to.\r
	361	@param[out] MediaPresent The pointer to the media present boolean value.\r
	362	\r
	363	@retval EFI_SUCCESS There is no media change happened.\r
364	@retval EFI_MEDIA_CHANGED There is media change happened.\r
365	@retval Others The detection fails.\r
366	\r
367	**/\r
368	EFI_STATUS\r
369	SdMmcHcCardDetect (\r
370	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
371	IN UINT8 Slot,\r
372	OUT BOOLEAN *MediaPresent\r
373	);\r
374	\r
375	/**\r
376	Stop SD/MMC card clock.\r
377	\r
378	Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
379	\r
380	@param[in] PciIo The PCI IO protocol instance.\r
381	@param[in] Slot The slot number of the SD card to send the command to.\r
382	\r
383	@retval EFI_SUCCESS Succeed to stop SD/MMC clock.\r
384	@retval Others Fail to stop SD/MMC clock.\r
385	\r
386	**/\r
387	EFI_STATUS\r
388	SdMmcHcStopClock (\r
389	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
390	IN UINT8 Slot\r
391	);\r
392	\r
393	/**\r
394	SD/MMC card clock supply.\r
395	\r
396	Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
397	\r
398	@param[in] PciIo The PCI IO protocol instance.\r
399	@param[in] Slot The slot number of the SD card to send the command to.\r
400	@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
401	@param[in] Capability The capability of the slot.\r
402	\r
403	@retval EFI_SUCCESS The clock is supplied successfully.\r
404	@retval Others The clock isn't supplied successfully.\r
405	\r
406	**/\r
407	EFI_STATUS\r
408	SdMmcHcClockSupply (\r
409	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
410	IN UINT8 Slot,\r
411	IN UINT64 ClockFreq,\r
412	IN SD_MMC_HC_SLOT_CAP Capability\r
413	);\r
414	\r
415	/**\r
416	SD/MMC bus power control.\r
417	\r
418	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
419	\r
420	@param[in] PciIo The PCI IO protocol instance.\r
421	@param[in] Slot The slot number of the SD card to send the command to.\r
422	@param[in] PowerCtrl The value setting to the power control register.\r
423	\r
424	@retval TRUE There is a SD/MMC card attached.\r
425	@retval FALSE There is no a SD/MMC card attached.\r
426	\r
427	**/\r
428	EFI_STATUS\r
429	SdMmcHcPowerControl (\r
430	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
431	IN UINT8 Slot,\r
432	IN UINT8 PowerCtrl\r
433	);\r
434	\r
435	/**\r
436	Set the SD/MMC bus width.\r
437	\r
438	Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
439	\r
440	@param[in] PciIo The PCI IO protocol instance.\r
441	@param[in] Slot The slot number of the SD card to send the command to.\r
442	@param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.\r
443	\r
444	@retval EFI_SUCCESS The bus width is set successfully.\r
445	@retval Others The bus width isn't set successfully.\r
446	\r
447	**/\r
448	EFI_STATUS\r
449	SdMmcHcSetBusWidth (\r
450	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
451	IN UINT8 Slot,\r
452	IN UINT16 BusWidth\r
453	);\r
454	\r
455	/**\r
456	Supply SD/MMC card with lowest clock frequency at initialization.\r
457	\r
458	@param[in] PciIo The PCI IO protocol instance.\r
459	@param[in] Slot The slot number of the SD card to send the command to.\r
460	@param[in] Capability The capability of the slot.\r
461	\r
462	@retval EFI_SUCCESS The clock is supplied successfully.\r
463	@retval Others The clock isn't supplied successfully.\r
464	\r
465	**/\r
466	EFI_STATUS\r
467	SdMmcHcInitClockFreq (\r
468	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
469	IN UINT8 Slot,\r
470	IN SD_MMC_HC_SLOT_CAP Capability\r
471	);\r
472	\r
473	/**\r
474	Supply SD/MMC card with maximum voltage at initialization.\r
475	\r
476	Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
477	\r
478	@param[in] PciIo The PCI IO protocol instance.\r
479	@param[in] Slot The slot number of the SD card to send the command to.\r
480	@param[in] Capability The capability of the slot.\r
481	\r
482	@retval EFI_SUCCESS The voltage is supplied successfully.\r
483	@retval Others The voltage isn't supplied successfully.\r
484	\r
485	**/\r
486	EFI_STATUS\r
487	SdMmcHcInitPowerVoltage (\r
488	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
489	IN UINT8 Slot,\r
490	IN SD_MMC_HC_SLOT_CAP Capability\r
491	);\r
492	\r
493	/**\r
494	Initialize the Timeout Control register with most conservative value at initialization.\r
495	\r
496	Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
497	\r
498	@param[in] PciIo The PCI IO protocol instance.\r
499	@param[in] Slot The slot number of the SD card to send the command to.\r
500	\r
501	@retval EFI_SUCCESS The timeout control register is configured successfully.\r
502	@retval Others The timeout control register isn't configured successfully.\r
503	\r
504	**/\r
505	EFI_STATUS\r
506	SdMmcHcInitTimeoutCtrl (\r
507	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
508	IN UINT8 Slot\r
509	);\r
510	\r
48555339	511	#endif\r