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MdeModulePkg: Clean up source files
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcPei / SdMmcPciHcPei.c
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48555339
FT		 1/** @file\r
2 SdMmcPciHcPei driver is used to provide platform-dependent info, mainly SD/MMC\r
3 host controller MMIO base, to upper layer SD/MMC drivers.\r
4\r
d1102dba 5 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
48555339
FT		 6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "SdMmcPciHcPei.h"\r
17\r
18EDKII_SD_MMC_HOST_CONTROLLER_PPI mSdMmcHostControllerPpi = { GetSdMmcHcMmioBar };\r
19\r
20EFI_PEI_PPI_DESCRIPTOR mPpiList = {\r
21 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
22 &gEdkiiPeiSdMmcHostControllerPpiGuid,\r
23 &mSdMmcHostControllerPpi\r
24};\r
25\r
26/**\r
27 Get the MMIO base address of SD/MMC host controller.\r
28\r
29 @param[in] This The protocol instance pointer.\r
30 @param[in] ControllerId The ID of the SD/MMC host controller.\r
31 @param[in,out] MmioBar The pointer to store the array of available\r
32 SD/MMC host controller slot MMIO base addresses.\r
33 The entry number of the array is specified by BarNum.\r
34 @param[out] BarNum The pointer to store the supported bar number.\r
35\r
36 @retval EFI_SUCCESS The operation succeeds.\r
37 @retval EFI_INVALID_PARAMETER The parameters are invalid.\r
38\r
39**/\r
40EFI_STATUS\r
41EFIAPI\r
42GetSdMmcHcMmioBar (\r
43 IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,\r
44 IN UINT8 ControllerId,\r
45 IN OUT UINTN **MmioBar,\r
46 OUT UINT8 *BarNum\r
47 )\r
48{\r
49 SD_MMC_HC_PEI_PRIVATE_DATA *Private;\r
50\r
51 if ((This == NULL) || (MmioBar == NULL) || (BarNum == NULL)) {\r
52 return EFI_INVALID_PARAMETER;\r
53 }\r
54\r
55 Private = SD_MMC_HC_PEI_PRIVATE_DATA_FROM_THIS (This);\r
56\r
57 if (ControllerId >= Private->TotalSdMmcHcs) {\r
58 return EFI_INVALID_PARAMETER;\r
59 }\r
60\r
61 *MmioBar = &Private->MmioBar[ControllerId].MmioBarAddr[0];\r
62 *BarNum = (UINT8)Private->MmioBar[ControllerId].SlotNum;\r
63 return EFI_SUCCESS;\r
64}\r
65\r
66/**\r
67 The user code starts with this function.\r
68\r
69 @param FileHandle Handle of the file being invoked.\r
70 @param PeiServices Describes the list of possible PEI Services.\r
71\r
72 @retval EFI_SUCCESS The driver is successfully initialized.\r
73 @retval Others Can't initialize the driver.\r
74\r
75**/\r
76EFI_STATUS\r
77EFIAPI\r
78InitializeSdMmcHcPeim (\r
79 IN EFI_PEI_FILE_HANDLE FileHandle,\r
80 IN CONST EFI_PEI_SERVICES **PeiServices\r
81 )\r
82{\r
83 EFI_BOOT_MODE BootMode;\r
84 EFI_STATUS Status;\r
85 UINT16 Bus;\r
86 UINT16 Device;\r
87 UINT16 Function;\r
88 UINT32 Size;\r
89 UINT64 MmioSize;\r
90 UINT8 SubClass;\r
91 UINT8 BaseClass;\r
92 UINT8 SlotInfo;\r
93 UINT8 SlotNum;\r
94 UINT8 FirstBar;\r
95 UINT8 Index;\r
96 UINT8 Slot;\r
97 UINT32 BarAddr;\r
98 SD_MMC_HC_PEI_PRIVATE_DATA *Private;\r
99\r
100 //\r
101 // Shadow this PEIM to run from memory\r
102 //\r
103 if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {\r
104 return EFI_SUCCESS;\r
105 }\r
106\r
107 Status = PeiServicesGetBootMode (&BootMode);\r
108 ///\r
109 /// We do not expose this in S3 boot path, because it is only for recovery.\r
110 ///\r
111 if (BootMode == BOOT_ON_S3_RESUME) {\r
112 return EFI_SUCCESS;\r
113 }\r
114\r
115 Private = (SD_MMC_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));\r
116 if (Private == NULL) {\r
117 DEBUG ((EFI_D_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));\r
118 return EFI_OUT_OF_RESOURCES;\r
119 }\r
120\r
121 Private->Signature = SD_MMC_HC_PEI_SIGNATURE;\r
122 Private->SdMmcHostControllerPpi = mSdMmcHostControllerPpi;\r
123 Private->PpiList = mPpiList;\r
124 Private->PpiList.Ppi = &Private->SdMmcHostControllerPpi;\r
125\r
126 BarAddr = PcdGet32 (PcdSdMmcPciHostControllerMmioBase);\r
127 for (Bus = 0; Bus < 256; Bus++) {\r
128 for (Device = 0; Device < 32; Device++) {\r
129 for (Function = 0; Function < 8; Function++) {\r
130 SubClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0A));\r
131 BaseClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0B));\r
132\r
133 if ((SubClass == PCI_SUBCLASS_SD_HOST_CONTROLLER) && (BaseClass == PCI_CLASS_SYSTEM_PERIPHERAL)) {\r
134 //\r
135 // Get the SD/MMC Pci host controller's Slot Info.\r
136 //\r
137 SlotInfo = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, SD_MMC_HC_PEI_SLOT_OFFSET));\r
138 FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).FirstBar;\r
139 SlotNum = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).SlotNum + 1;\r
140 ASSERT ((FirstBar + SlotNum) < MAX_SD_MMC_SLOTS);\r
141\r
142 for (Index = 0, Slot = FirstBar; Slot < (FirstBar + SlotNum); Index++, Slot++) {\r
143 //\r
144 // Get the SD/MMC Pci host controller's MMIO region size.\r
145 //\r
146 PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));\r
147 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), 0xFFFFFFFF);\r
148 Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot));\r
149\r
150 switch (Size & 0x07) {\r
151 case 0x0:\r
152 //\r
153 // Memory space: anywhere in 32 bit address space\r
154 //\r
155 MmioSize = (~(Size & 0xFFFFFFF0)) + 1;\r
156 break;\r
157 case 0x4:\r
158 //\r
159 // Memory space: anywhere in 64 bit address space\r
160 //\r
161 MmioSize = Size & 0xFFFFFFF0;\r
162 PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);\r
d1102dba 163 Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));\r
48555339
FT		 164 //\r
165 // Fix the length to support some spefic 64 bit BAR\r
166 //\r
167 Size |= ((UINT32)(-1) << HighBitSet32 (Size));\r
168 //\r
169 // Calculate the size of 64bit bar\r
170 //\r
171 MmioSize |= LShiftU64 ((UINT64) Size, 32);\r
172 MmioSize = (~(MmioSize)) + 1;\r
173 //\r
174 // Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit BAR.\r
175 //\r
176 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot + 4), 0);\r
177 break;\r
178 default:\r
179 //\r
180 // Unknown BAR type\r
181 //\r
182 ASSERT (FALSE);\r
183 continue;\r
184 };\r
185 //\r
186 // Assign resource to the SdMmc Pci host controller's MMIO BAR.\r
187 // Enable the SdMmc Pci host controller by setting BME and MSE bits of PCI_CMD register.\r
188 //\r
189 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), BarAddr);\r
190 PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));\r
191 //\r
192 // Record the allocated Mmio base address.\r
193 //\r
194 Private->MmioBar[Private->TotalSdMmcHcs].SlotNum++;\r
195 Private->MmioBar[Private->TotalSdMmcHcs].MmioBarAddr[Index] = BarAddr;\r
196 BarAddr += (UINT32)MmioSize;\r
197 }\r
198 Private->TotalSdMmcHcs++;\r
199 ASSERT (Private->TotalSdMmcHcs < MAX_SD_MMC_HCS);\r
200 }\r
201 }\r
202 }\r
203 }\r
204\r
205 ///\r
206 /// Install SdMmc Host Controller PPI\r
207 ///\r
208 Status = PeiServicesInstallPpi (&Private->PpiList);\r
209\r
210 ASSERT_EFI_ERROR (Status);\r
211 return Status;\r
212}\r
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