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MdeModulePkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcPei / SdMmcPciHcPei.c
CommitLineData
48555339
FT		 1/** @file\r
2 SdMmcPciHcPei driver is used to provide platform-dependent info, mainly SD/MMC\r
3 host controller MMIO base, to upper layer SD/MMC drivers.\r
4\r
d1102dba 5 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
9d510e61 6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
48555339
FT		 7\r
8**/\r
9\r
10#include "SdMmcPciHcPei.h"\r
11\r
12EDKII_SD_MMC_HOST_CONTROLLER_PPI mSdMmcHostControllerPpi = { GetSdMmcHcMmioBar };\r
13\r
14EFI_PEI_PPI_DESCRIPTOR mPpiList = {\r
15 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
16 &gEdkiiPeiSdMmcHostControllerPpiGuid,\r
17 &mSdMmcHostControllerPpi\r
18};\r
19\r
20/**\r
21 Get the MMIO base address of SD/MMC host controller.\r
22\r
23 @param[in] This The protocol instance pointer.\r
24 @param[in] ControllerId The ID of the SD/MMC host controller.\r
25 @param[in,out] MmioBar The pointer to store the array of available\r
26 SD/MMC host controller slot MMIO base addresses.\r
27 The entry number of the array is specified by BarNum.\r
28 @param[out] BarNum The pointer to store the supported bar number.\r
29\r
30 @retval EFI_SUCCESS The operation succeeds.\r
31 @retval EFI_INVALID_PARAMETER The parameters are invalid.\r
32\r
33**/\r
34EFI_STATUS\r
35EFIAPI\r
36GetSdMmcHcMmioBar (\r
37 IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,\r
38 IN UINT8 ControllerId,\r
39 IN OUT UINTN **MmioBar,\r
40 OUT UINT8 *BarNum\r
41 )\r
42{\r
43 SD_MMC_HC_PEI_PRIVATE_DATA *Private;\r
44\r
45 if ((This == NULL) || (MmioBar == NULL) || (BarNum == NULL)) {\r
46 return EFI_INVALID_PARAMETER;\r
47 }\r
48\r
49 Private = SD_MMC_HC_PEI_PRIVATE_DATA_FROM_THIS (This);\r
50\r
51 if (ControllerId >= Private->TotalSdMmcHcs) {\r
52 return EFI_INVALID_PARAMETER;\r
53 }\r
54\r
55 *MmioBar = &Private->MmioBar[ControllerId].MmioBarAddr[0];\r
56 *BarNum = (UINT8)Private->MmioBar[ControllerId].SlotNum;\r
57 return EFI_SUCCESS;\r
58}\r
59\r
60/**\r
61 The user code starts with this function.\r
62\r
63 @param FileHandle Handle of the file being invoked.\r
64 @param PeiServices Describes the list of possible PEI Services.\r
65\r
66 @retval EFI_SUCCESS The driver is successfully initialized.\r
67 @retval Others Can't initialize the driver.\r
68\r
69**/\r
70EFI_STATUS\r
71EFIAPI\r
72InitializeSdMmcHcPeim (\r
73 IN EFI_PEI_FILE_HANDLE FileHandle,\r
74 IN CONST EFI_PEI_SERVICES **PeiServices\r
75 )\r
76{\r
77 EFI_BOOT_MODE BootMode;\r
78 EFI_STATUS Status;\r
79 UINT16 Bus;\r
80 UINT16 Device;\r
81 UINT16 Function;\r
82 UINT32 Size;\r
83 UINT64 MmioSize;\r
84 UINT8 SubClass;\r
85 UINT8 BaseClass;\r
86 UINT8 SlotInfo;\r
87 UINT8 SlotNum;\r
88 UINT8 FirstBar;\r
89 UINT8 Index;\r
90 UINT8 Slot;\r
91 UINT32 BarAddr;\r
92 SD_MMC_HC_PEI_PRIVATE_DATA *Private;\r
93\r
94 //\r
95 // Shadow this PEIM to run from memory\r
96 //\r
97 if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {\r
98 return EFI_SUCCESS;\r
99 }\r
100\r
101 Status = PeiServicesGetBootMode (&BootMode);\r
102 ///\r
103 /// We do not expose this in S3 boot path, because it is only for recovery.\r
104 ///\r
105 if (BootMode == BOOT_ON_S3_RESUME) {\r
106 return EFI_SUCCESS;\r
107 }\r
108\r
109 Private = (SD_MMC_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));\r
110 if (Private == NULL) {\r
111 DEBUG ((EFI_D_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));\r
112 return EFI_OUT_OF_RESOURCES;\r
113 }\r
114\r
115 Private->Signature = SD_MMC_HC_PEI_SIGNATURE;\r
116 Private->SdMmcHostControllerPpi = mSdMmcHostControllerPpi;\r
117 Private->PpiList = mPpiList;\r
118 Private->PpiList.Ppi = &Private->SdMmcHostControllerPpi;\r
119\r
120 BarAddr = PcdGet32 (PcdSdMmcPciHostControllerMmioBase);\r
121 for (Bus = 0; Bus < 256; Bus++) {\r
122 for (Device = 0; Device < 32; Device++) {\r
123 for (Function = 0; Function < 8; Function++) {\r
124 SubClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0A));\r
125 BaseClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0B));\r
126\r
127 if ((SubClass == PCI_SUBCLASS_SD_HOST_CONTROLLER) && (BaseClass == PCI_CLASS_SYSTEM_PERIPHERAL)) {\r
128 //\r
129 // Get the SD/MMC Pci host controller's Slot Info.\r
130 //\r
131 SlotInfo = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, SD_MMC_HC_PEI_SLOT_OFFSET));\r
132 FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).FirstBar;\r
133 SlotNum = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).SlotNum + 1;\r
134 ASSERT ((FirstBar + SlotNum) < MAX_SD_MMC_SLOTS);\r
135\r
136 for (Index = 0, Slot = FirstBar; Slot < (FirstBar + SlotNum); Index++, Slot++) {\r
137 //\r
138 // Get the SD/MMC Pci host controller's MMIO region size.\r
139 //\r
140 PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));\r
141 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), 0xFFFFFFFF);\r
142 Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot));\r
143\r
144 switch (Size & 0x07) {\r
145 case 0x0:\r
146 //\r
147 // Memory space: anywhere in 32 bit address space\r
148 //\r
149 MmioSize = (~(Size & 0xFFFFFFF0)) + 1;\r
150 break;\r
151 case 0x4:\r
152 //\r
153 // Memory space: anywhere in 64 bit address space\r
154 //\r
155 MmioSize = Size & 0xFFFFFFF0;\r
156 PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);\r
d1102dba 157 Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));\r
48555339
FT		 158 //\r
159 // Fix the length to support some spefic 64 bit BAR\r
160 //\r
161 Size |= ((UINT32)(-1) << HighBitSet32 (Size));\r
162 //\r
163 // Calculate the size of 64bit bar\r
164 //\r
165 MmioSize |= LShiftU64 ((UINT64) Size, 32);\r
166 MmioSize = (~(MmioSize)) + 1;\r
167 //\r
168 // Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit BAR.\r
169 //\r
170 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot + 4), 0);\r
171 break;\r
172 default:\r
173 //\r
174 // Unknown BAR type\r
175 //\r
176 ASSERT (FALSE);\r
177 continue;\r
178 };\r
179 //\r
180 // Assign resource to the SdMmc Pci host controller's MMIO BAR.\r
181 // Enable the SdMmc Pci host controller by setting BME and MSE bits of PCI_CMD register.\r
182 //\r
183 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), BarAddr);\r
184 PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));\r
185 //\r
186 // Record the allocated Mmio base address.\r
187 //\r
188 Private->MmioBar[Private->TotalSdMmcHcs].SlotNum++;\r
189 Private->MmioBar[Private->TotalSdMmcHcs].MmioBarAddr[Index] = BarAddr;\r
190 BarAddr += (UINT32)MmioSize;\r
191 }\r
192 Private->TotalSdMmcHcs++;\r
193 ASSERT (Private->TotalSdMmcHcs < MAX_SD_MMC_HCS);\r
194 }\r
195 }\r
196 }\r
197 }\r
198\r
199 ///\r
200 /// Install SdMmc Host Controller PPI\r
201 ///\r
202 Status = PeiServicesInstallPpi (&Private->PpiList);\r
203\r
204 ASSERT_EFI_ERROR (Status);\r
205 return Status;\r
206}\r
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