]>
Commit | Line | Data |
---|---|---|
48555339 FT |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r | |
9d510e61 | 4 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
48555339 FT |
5 | \r |
6 | **/\r | |
7 | \r | |
8 | #ifndef _SD_MMC_PCI_HOST_CONTROLLER_PEI_H_\r | |
9 | #define _SD_MMC_PCI_HOST_CONTROLLER_PEI_H_\r | |
10 | \r | |
11 | #include <PiPei.h>\r | |
12 | \r | |
13 | #include <Ppi/MasterBootMode.h>\r | |
14 | #include <Ppi/SdMmcHostController.h>\r | |
15 | \r | |
16 | #include <IndustryStandard/Pci.h>\r | |
17 | \r | |
18 | #include <Library/DebugLib.h>\r | |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/BaseMemoryLib.h>\r | |
21 | #include <Library/PciLib.h>\r | |
22 | #include <Library/PeiServicesLib.h>\r | |
23 | #include <Library/MemoryAllocationLib.h>\r | |
24 | \r | |
25 | #define SD_MMC_HC_PEI_SIGNATURE SIGNATURE_32 ('S', 'D', 'M', 'C')\r | |
26 | \r | |
27 | #define MAX_SD_MMC_HCS 8\r | |
28 | #define MAX_SD_MMC_SLOTS 6\r | |
29 | \r | |
30 | //\r | |
31 | // SD Host Controller SlotInfo Register Offset\r | |
32 | //\r | |
33 | #define SD_MMC_HC_PEI_SLOT_OFFSET 0x40\r | |
34 | \r | |
35 | typedef struct {\r | |
36 | UINT8 FirstBar:3; // bit 0:2\r | |
37 | UINT8 Reserved:1; // bit 3\r | |
38 | UINT8 SlotNum:3; // bit 4:6\r | |
39 | UINT8 Reserved1:1; // bit 7\r | |
40 | } SD_MMC_HC_PEI_SLOT_INFO;\r | |
41 | \r | |
42 | typedef struct {\r | |
43 | UINTN SlotNum;\r | |
44 | UINTN MmioBarAddr[MAX_SD_MMC_SLOTS];\r | |
45 | } SD_MMC_HC_PEI_BAR;\r | |
46 | \r | |
47 | typedef struct {\r | |
48 | UINTN Signature;\r | |
49 | EDKII_SD_MMC_HOST_CONTROLLER_PPI SdMmcHostControllerPpi;\r | |
50 | EFI_PEI_PPI_DESCRIPTOR PpiList;\r | |
51 | UINTN TotalSdMmcHcs;\r | |
52 | SD_MMC_HC_PEI_BAR MmioBar[MAX_SD_MMC_HCS];\r | |
53 | } SD_MMC_HC_PEI_PRIVATE_DATA;\r | |
54 | \r | |
55 | #define SD_MMC_HC_PEI_PRIVATE_DATA_FROM_THIS(a) CR (a, SD_MMC_HC_PEI_PRIVATE_DATA, SdMmcHostControllerPpi, SD_MMC_HC_PEI_SIGNATURE)\r | |
56 | \r | |
57 | /**\r | |
58 | Get the MMIO base address of SD/MMC host controller.\r | |
59 | \r | |
60 | @param[in] This The protocol instance pointer.\r | |
61 | @param[in] ControllerId The ID of the SD/MMC host controller.\r | |
62 | @param[in,out] MmioBar The pointer to store the array of available\r | |
63 | SD/MMC host controller slot MMIO base addresses.\r | |
64 | The entry number of the array is specified by BarNum.\r | |
65 | @param[out] BarNum The pointer to store the supported bar number.\r | |
66 | \r | |
67 | @retval EFI_SUCCESS The operation succeeds.\r | |
68 | @retval EFI_INVALID_PARAMETER The parameters are invalid.\r | |
69 | \r | |
70 | **/\r | |
71 | EFI_STATUS\r | |
72 | EFIAPI\r | |
73 | GetSdMmcHcMmioBar (\r | |
74 | IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,\r | |
75 | IN UINT8 ControllerId,\r | |
76 | IN OUT UINTN **MmioBar,\r | |
77 | OUT UINT8 *BarNum\r | |
78 | );\r | |
79 | \r | |
80 | #endif\r |