]>
Commit | Line | Data |
---|---|---|
913cb9dc | 1 | /** @file\r |
2 | \r | |
ab6495ea | 3 | The definition for UHCI driver model and HC protocol routines.\r |
4 | \r | |
913cb9dc | 5 | Copyright (c) 2004 - 2007, Intel Corporation\r |
6 | All rights reserved. This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
913cb9dc | 14 | **/\r |
15 | \r | |
ab6495ea | 16 | #ifndef _EFI_UHCI_H_\r |
17 | #define _EFI_UHCI_H_\r | |
913cb9dc | 18 | \r |
ed7748fe | 19 | \r |
60c93673 | 20 | #include <Uefi.h>\r |
ed7748fe | 21 | \r |
913cb9dc | 22 | #include <Protocol/Usb2HostController.h>\r |
23 | #include <Protocol/UsbHostController.h>\r | |
24 | #include <Protocol/PciIo.h>\r | |
ed7748fe | 25 | \r |
913cb9dc | 26 | #include <Library/DebugLib.h>\r |
27 | #include <Library/BaseMemoryLib.h>\r | |
28 | #include <Library/UefiDriverEntryPoint.h>\r | |
29 | #include <Library/UefiBootServicesTableLib.h>\r | |
30 | #include <Library/UefiLib.h>\r | |
31 | #include <Library/BaseLib.h>\r | |
32 | #include <Library/MemoryAllocationLib.h>\r | |
dd4047a5 | 33 | #include <Library/PcdLib.h>\r |
913cb9dc | 34 | \r |
35 | #include <IndustryStandard/Pci22.h>\r | |
36 | \r | |
37 | typedef struct _USB_HC_DEV USB_HC_DEV;\r | |
38 | \r | |
39 | #include "UsbHcMem.h"\r | |
40 | #include "UhciQueue.h"\r | |
41 | #include "UhciReg.h"\r | |
42 | #include "UhciSched.h"\r | |
43 | #include "UhciDebug.h"\r | |
44 | \r | |
ab6495ea | 45 | typedef enum {\r |
41e8ff27 | 46 | UHC_1_MICROSECOND = 1,\r |
47 | UHC_1_MILLISECOND = 1000 * UHC_1_MICROSECOND,\r | |
48 | UHC_1_SECOND = 1000 * UHC_1_MILLISECOND,\r | |
49 | \r | |
50 | //\r | |
51 | // UHCI register operation timeout, set by experience\r | |
913cb9dc | 52 | //\r |
41e8ff27 | 53 | UHC_GENERIC_TIMEOUT = UHC_1_SECOND,\r |
68246fa8 | 54 | \r |
913cb9dc | 55 | //\r |
41e8ff27 | 56 | // Wait for force global resume(FGR) complete, refers to\r |
57 | // specification[UHCI11-2.1.1]\r | |
68246fa8 | 58 | //\r |
41e8ff27 | 59 | UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,\r |
913cb9dc | 60 | \r |
41e8ff27 | 61 | //\r |
62 | // Wait for roothub port reset and recovery, reset stall\r | |
68246fa8 | 63 | // is set by experience, and recovery stall refers to\r |
41e8ff27 | 64 | // specification[UHCI11-2.1.1]\r |
65 | //\r | |
66 | UHC_ROOT_PORT_RESET_STALL = 50 * UHC_1_MILLISECOND,\r | |
67 | UHC_ROOT_PORT_RECOVERY_STALL = 10 * UHC_1_MILLISECOND,\r | |
913cb9dc | 68 | \r |
41e8ff27 | 69 | //\r |
68246fa8 | 70 | // Sync and Async transfer polling interval, set by experience,\r |
41e8ff27 | 71 | // and the unit of Async is 100us.\r |
72 | //\r | |
73 | UHC_SYNC_POLL_INTERVAL = 50 * UHC_1_MICROSECOND,\r | |
ab6495ea | 74 | UHC_ASYNC_POLL_INTERVAL = 50 * 10000UL\r |
75 | }UHC_TIMEOUT_EXPERIENCE_VALUE;\r | |
68246fa8 | 76 | \r |
913cb9dc | 77 | \r |
ab6495ea | 78 | //\r |
79 | // UHC raises TPL to TPL_NOTIFY to serialize all its operations\r | |
80 | // to protect shared data structures.\r | |
81 | //\r | |
82 | #define UHCI_TPL TPL_NOTIFY\r | |
83 | \r | |
84 | #define USB_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')\r | |
913cb9dc | 85 | \r |
86 | #pragma pack(1)\r | |
87 | typedef struct {\r | |
88 | UINT8 PI;\r | |
89 | UINT8 SubClassCode;\r | |
90 | UINT8 BaseCode;\r | |
91 | } USB_CLASSC;\r | |
92 | #pragma pack()\r | |
93 | \r | |
913cb9dc | 94 | #define UHC_FROM_USB2_HC_PROTO(This) CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)\r |
95 | \r | |
96 | //\r | |
97 | // USB_HC_DEV support the UHCI hardware controller. It schedules\r | |
98 | // the asynchronous interrupt transfer with the same method as\r | |
99 | // EHCI: a reversed tree structure. For synchronous interrupt,\r | |
100 | // control and bulk transfer, it uses three static queue head to\r | |
101 | // schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is\r | |
102 | // for LOW speed control transfer, and FsCtrlBulkQh is for FULL\r | |
103 | // speed control or bulk transfer. This is because FULL speed contrl\r | |
104 | // or bulk transfer can reclaim the unused bandwidth. Some USB\r | |
105 | // device requires this bandwidth reclamation capability.\r | |
106 | //\r | |
c52fa98c | 107 | struct _USB_HC_DEV {\r |
913cb9dc | 108 | UINT32 Signature;\r |
913cb9dc | 109 | EFI_USB2_HC_PROTOCOL Usb2Hc;\r |
110 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
68246fa8 | 111 | UINT64 OriginalPciAttributes;\r |
913cb9dc | 112 | \r |
113 | //\r | |
114 | // Schedule data structures\r | |
115 | //\r | |
116 | UINT32 *FrameBase;\r | |
117 | UHCI_QH_SW *SyncIntQh;\r | |
118 | UHCI_QH_SW *CtrlQh;\r | |
119 | UHCI_QH_SW *BulkQh;\r | |
120 | \r | |
121 | //\r | |
122 | // Structures to maintain asynchronus interrupt transfers.\r | |
123 | // When asynchronous interrutp transfer is unlinked from\r | |
124 | // the frame list, the hardware may still hold a pointer\r | |
125 | // to it. To synchronize with hardware, its resoureces are\r | |
126 | // released in two steps using Recycle and RecycleWait.\r | |
127 | // Check the asynchronous interrupt management routines.\r | |
128 | //\r | |
129 | LIST_ENTRY AsyncIntList;\r | |
130 | EFI_EVENT AsyncIntMonitor;\r | |
131 | UHCI_ASYNC_REQUEST *Recycle;\r | |
132 | UHCI_ASYNC_REQUEST *RecycleWait;\r | |
133 | \r | |
134 | \r | |
135 | UINTN RootPorts;\r | |
136 | USBHC_MEM_POOL *MemPool;\r | |
137 | EFI_UNICODE_STRING_TABLE *CtrlNameTable;\r | |
138 | VOID *FrameMapping;\r | |
c52fa98c | 139 | };\r |
913cb9dc | 140 | \r |
f527bce3 | 141 | extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;\r |
142 | extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;\r | |
143 | extern EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2;\r | |
913cb9dc | 144 | \r |
145 | #endif\r |