[Description]:

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / Uhci.h

/** @file\r
\r
Copyright (c) 2004 - 2007, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
  Uhci.h\r
\r
Abstract:\r
\r
  The definition for UHCI driver model and HC protocol routines.\r
\r
Revision History\r
\r
\r
**/\r
\r
#ifndef _UHCI_H\r
#define _UHCI_H\r
\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/Usb2HostController.h>\r
#include <Protocol/UsbHostController.h>\r
#include <Protocol/PciIo.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
\r
#include <IndustryStandard/Pci22.h>\r
\r
typedef struct _USB_HC_DEV  USB_HC_DEV;\r
\r
#include "UsbHcMem.h"\r
#include "UhciQueue.h"\r
#include "UhciReg.h"\r
#include "UhciSched.h"\r
#include "UhciDebug.h"\r
\r
enum {\r
  UHC_1_MICROSECOND             = 1,\r
  UHC_1_MILLISECOND             = 1000 * UHC_1_MICROSECOND,\r
  UHC_1_SECOND                  = 1000 * UHC_1_MILLISECOND,\r
\r
  //\r
  // UHCI register operation timeout, set by experience\r
  //\r
  UHC_GENERIC_TIMEOUT           = UHC_1_SECOND,\r
\r
  //\r
  // Wait for force global resume(FGR) complete, refers to\r
  // specification[UHCI11-2.1.1]\r
  //\r
  UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,\r
\r
  //\r
  // Wait for roothub port reset and recovery, reset stall\r
  // is set by experience, and recovery stall refers to\r
  // specification[UHCI11-2.1.1]\r
  //\r
  UHC_ROOT_PORT_RESET_STALL     = 50 * UHC_1_MILLISECOND,\r
  UHC_ROOT_PORT_RECOVERY_STALL  = 10 * UHC_1_MILLISECOND,\r
\r
  //\r
  // Sync and Async transfer polling interval, set by experience,\r
  // and the unit of Async is 100us.\r
  //\r
  UHC_SYNC_POLL_INTERVAL        = 50 * UHC_1_MICROSECOND,\r
  UHC_ASYNC_POLL_INTERVAL       = 50 * 10000UL,\r
\r
  //\r
  // UHC raises TPL to TPL_NOTIFY to serialize all its operations\r
  // to protect shared data structures.\r
  //\r
  UHCI_TPL                 = TPL_NOTIFY,\r
\r
  USB_HC_DEV_SIGNATURE          = EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')\r
};\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8               PI;\r
  UINT8               SubClassCode;\r
  UINT8               BaseCode;\r
} USB_CLASSC;\r
#pragma pack()\r
\r
#define UHC_FROM_USB2_HC_PROTO(This)  CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)\r
\r
//\r
// USB_HC_DEV support the UHCI hardware controller. It schedules\r
// the asynchronous interrupt transfer with the same method as\r
// EHCI: a reversed tree structure. For synchronous interrupt,\r
// control and bulk transfer, it uses three static queue head to\r
// schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is\r
// for LOW speed control transfer, and FsCtrlBulkQh is for FULL\r
// speed control or bulk transfer. This is because FULL speed contrl\r
// or bulk transfer can reclaim the unused bandwidth. Some USB\r
// device requires this bandwidth reclamation capability.\r
//\r
struct _USB_HC_DEV {\r
  UINT32                    Signature;\r
  EFI_USB2_HC_PROTOCOL      Usb2Hc;\r
  EFI_PCI_IO_PROTOCOL       *PciIo;\r
  UINT64                    OriginalPciAttributes;\r
\r
  //\r
  // Schedule data structures\r
  //\r
  UINT32                    *FrameBase;\r
  UHCI_QH_SW                *SyncIntQh;\r
  UHCI_QH_SW                *CtrlQh;\r
  UHCI_QH_SW                *BulkQh;\r
\r
  //\r
  // Structures to maintain asynchronus interrupt transfers.\r
  // When asynchronous interrutp transfer is unlinked from\r
  // the frame list, the hardware may still hold a pointer\r
  // to it. To synchronize with hardware, its resoureces are\r
  // released in two steps using Recycle and RecycleWait.\r
  // Check the asynchronous interrupt management routines.\r
  //\r
  LIST_ENTRY                AsyncIntList;\r
  EFI_EVENT                 AsyncIntMonitor;\r
  UHCI_ASYNC_REQUEST        *Recycle;\r
  UHCI_ASYNC_REQUEST        *RecycleWait;\r
\r
\r
  UINTN                     RootPorts;\r
  USBHC_MEM_POOL            *MemPool;\r
  EFI_UNICODE_STRING_TABLE  *CtrlNameTable;\r
  VOID                      *FrameMapping;\r
};\r
\r
extern EFI_DRIVER_BINDING_PROTOCOL   gUhciDriverBinding;\r
extern EFI_COMPONENT_NAME_PROTOCOL   gUhciComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL  gUhciComponentName2;\r
\r
#endif\r