Remove some useless EDK_RELEASE_VERSION, EFI_SPECIFICATION_VERSION ,and review VALID_...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciReg.c

/** @file\r
\r
  The UHCI register operation routines.\r
\r
Copyright (c) 2007, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "Uhci.h"\r
\r
\r
/**\r
  Read a UHCI register.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
\r
  @return Content of register.\r
\r
**/\r
UINT16\r
UhciReadReg (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset\r
  )\r
{\r
  UINT16      Data;\r
  EFI_STATUS  Status;\r
\r
  Status = PciIo->Io.Read (\r
                      PciIo,\r
                      EfiPciIoWidthUint16,\r
                      USB_BAR_INDEX,\r
                      Offset,\r
                      1,\r
                      &Data\r
                      );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));\r
\r
    Data = 0xFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
\r
/**\r
  Write data to UHCI register.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
  @param  Data         Data to write.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciWriteReg (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Data\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  Status = PciIo->Io.Write (\r
                      PciIo,\r
                      EfiPciIoWidthUint16,\r
                      USB_BAR_INDEX,\r
                      Offset,\r
                      1,\r
                      &Data\r
                      );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));\r
  }\r
}\r
\r
\r
/**\r
  Set a bit of the UHCI Register.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
  @param  Bit          The bit to set.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciSetRegBit (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Bit\r
  )\r
{\r
  UINT16  Data;\r
\r
  Data = UhciReadReg (PciIo, Offset);\r
  Data = (UINT16) (Data |Bit);\r
  UhciWriteReg (PciIo, Offset, Data);\r
}\r
\r
\r
/**\r
  Clear a bit of the UHCI Register.\r
\r
  @param  PciIo        The PCI_IO protocol to access the PCI.\r
  @param  Offset       Register offset to USB_BAR_INDEX.\r
  @param  Bit          The bit to clear.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciClearRegBit (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Bit\r
  )\r
{\r
  UINT16  Data;\r
\r
  Data = UhciReadReg (PciIo, Offset);\r
  Data = (UINT16) (Data & ~Bit);\r
  UhciWriteReg (PciIo, Offset, Data);\r
}\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits\r
  are Write-Clean.\r
\r
  @param  Uhc          The UHCI device.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciAckAllInterrupt (\r
  IN  USB_HC_DEV          *Uhc\r
  )\r
{\r
  UhciWriteReg (Uhc->PciIo, USBSTS_OFFSET, 0x3F);\r
\r
  //\r
  // If current HC is halted, re-enable it. Host Controller Process Error\r
  // is a temporary error status.\r
  //\r
  if (!UhciIsHcWorking (Uhc->PciIo)) {\r
    DEBUG ((EFI_D_ERROR, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));\r
    Uhc->Usb2Hc.SetState (&Uhc->Usb2Hc, EfiUsbHcStateOperational);\r
  }\r
}\r
\r
\r
/**\r
  Stop the host controller.\r
\r
  @param  Uhc          The UHCI device.\r
  @param  Timeout      Max time allowed.\r
\r
  @retval EFI_SUCCESS  The host controller is stopped.\r
  @retval EFI_TIMEOUT  Failed to stop the host controller.\r
\r
**/\r
EFI_STATUS\r
UhciStopHc (\r
  IN USB_HC_DEV        *Uhc,\r
  IN UINTN             Timeout\r
  )\r
{\r
  UINT16                UsbSts;\r
  UINTN                 Index;\r
\r
  UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_RS);\r
\r
  //\r
  // ensure the HC is in halt status after send the stop command\r
  // Timeout is in us unit.\r
  //\r
  for (Index = 0; Index < (Timeout / 50) + 1; Index++) {\r
    UsbSts = UhciReadReg (Uhc->PciIo, USBSTS_OFFSET);\r
\r
    if ((UsbSts & USBSTS_HCH) == USBSTS_HCH) {\r
      return EFI_SUCCESS;\r
    }\r
\r
    gBS->Stall (50);\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
\r
/**\r
  Check whether the host controller operates well.\r
\r
  @param  PciIo        The PCI_IO protocol to use.\r
\r
  @retval TRUE         Host controller is working.\r
  @retval FALSE        Host controller is halted or system error.\r
\r
**/\r
BOOLEAN\r
UhciIsHcWorking (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo\r
  )\r
{\r
  UINT16                UsbSts;\r
\r
  UsbSts = UhciReadReg (PciIo, USBSTS_OFFSET);\r
\r
  if ((UsbSts & (USBSTS_HCPE | USBSTS_HSE | USBSTS_HCH)) != 0) {\r
    DEBUG ((EFI_D_ERROR, "UhciIsHcWorking: current USB state is %x\n", UsbSts));\r
    return FALSE;\r
  }\r
\r
  return TRUE;\r
}\r
\r
\r
/**\r
  Set the UHCI frame list base address. It can't use\r
  UhciWriteReg which access memory in UINT16.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.\r
  @param  Addr         Address to set.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciSetFrameListBaseAddr (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN VOID                    *Addr\r
  )\r
{\r
  EFI_STATUS              Status;\r
  UINT32                  Data;\r
\r
  Data = (UINT32) ((UINTN) Addr & 0xFFFFF000);\r
\r
  Status = PciIo->Io.Write (\r
                       PciIo,\r
                       EfiPciIoWidthUint32,\r
                       USB_BAR_INDEX,\r
                       (UINT64) USB_FRAME_BASE_OFFSET,\r
                       1,\r
                       &Data\r
                       );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status));\r
  }\r
}\r
\r
\r
/**\r
  Disable USB Emulation.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL protocol to use.\r
\r
  @return None.\r
\r
**/\r
VOID\r
UhciTurnOffUsbEmulation (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo\r
  )\r
{\r
  UINT16            Command;\r
\r
  Command = 0;\r
\r
  PciIo->Pci.Write (\r
               PciIo,\r
               EfiPciIoWidthUint16,\r
               USB_EMULATION_OFFSET,\r
               1,\r
               &Command\r
               );\r
}\r