[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciReg.h

/** @file\r
\r
Copyright (c) 2007 - 2008, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
  UhciReg.h\r
\r
Abstract:\r
\r
  The definition for UHCI register operation routines.\r
\r
Revision History\r
\r
\r
**/\r
\r
#ifndef _EFI_UHCI_REG_H_\r
#define _EFI_UHCI_REG_H_\r
\r
#define BIT(a)  (1 << (a))\r
\r
enum {\r
  UHCI_FRAME_NUM        = 1024,\r
\r
  //\r
  // Register offset and PCI related staff\r
  //\r
  CLASSC_OFFSET         = 0x09,\r
  USBBASE_OFFSET        = 0x20,\r
  USB_BAR_INDEX         = 4,\r
  PCI_CLASSC_PI_UHCI    = 0x00,\r
\r
  USBCMD_OFFSET         = 0,\r
  USBSTS_OFFSET         = 2,\r
  USBINTR_OFFSET        = 4,\r
  USBPORTSC_OFFSET      = 0x10,\r
  USB_FRAME_NO_OFFSET   = 6,\r
  USB_FRAME_BASE_OFFSET = 8,\r
  USB_EMULATION_OFFSET  = 0xC0,\r
\r
  //\r
  // Packet IDs\r
  //\r
  SETUP_PACKET_ID       = 0x2D,\r
  INPUT_PACKET_ID       = 0x69,\r
  OUTPUT_PACKET_ID      = 0xE1,\r
  ERROR_PACKET_ID       = 0x55,\r
\r
  //\r
  // USB port status and control bit definition.\r
  //\r
  USBPORTSC_CCS         = BIT(0),  // Current Connect Status\r
  USBPORTSC_CSC         = BIT(1),  // Connect Status Change\r
  USBPORTSC_PED         = BIT(2),  // Port Enable / Disable\r
  USBPORTSC_PEDC        = BIT(3),  // Port Enable / Disable Change\r
  USBPORTSC_LSL         = BIT(4),  // Line Status Low BIT\r
  USBPORTSC_LSH         = BIT(5),  // Line Status High BIT\r
  USBPORTSC_RD          = BIT(6),  // Resume Detect\r
  USBPORTSC_LSDA        = BIT(8),  // Low Speed Device Attached\r
  USBPORTSC_PR          = BIT(9),  // Port Reset\r
  USBPORTSC_SUSP        = BIT(12), // Suspend\r
\r
  //\r
  // UHCI Spec said it must implement 2 ports each host at least,\r
  // and if more, check whether the bit7 of PORTSC is always 1.\r
  // So here assume the max of port number each host is 16.\r
  //\r
  USB_MAX_ROOTHUB_PORT  = 0x0F,\r
  \r
  //\r
  // Command register bit definitions\r
  //\r
  USBCMD_RS             = BIT(0),  // Run/Stop\r
  USBCMD_HCRESET        = BIT(1),  // Host reset\r
  USBCMD_GRESET         = BIT(2),  // Global reset\r
  USBCMD_EGSM           = BIT(3),  // Global Suspend Mode\r
  USBCMD_FGR            = BIT(4),  // Force Global Resume\r
  USBCMD_SWDBG          = BIT(5),  // SW Debug mode\r
  USBCMD_CF             = BIT(6),  // Config Flag (sw only)\r
  USBCMD_MAXP           = BIT(7),  // Max Packet (0 = 32, 1 = 64)\r
\r
  //\r
  // USB Status register bit definitions\r
  //\r
  USBSTS_USBINT         = BIT(0),  // Interrupt due to IOC\r
  USBSTS_ERROR          = BIT(1),  // Interrupt due to error\r
  USBSTS_RD             = BIT(2),  // Resume Detect\r
  USBSTS_HSE            = BIT(3),  // Host System Error\r
  USBSTS_HCPE           = BIT(4),  // Host Controller Process Error\r
  USBSTS_HCH            = BIT(5),  // HC Halted\r
\r
  USBTD_ACTIVE          = BIT(7),  // TD is still active\r
  USBTD_STALLED         = BIT(6),  // TD is stalled\r
  USBTD_BUFFERR         = BIT(5),  // Buffer underflow or overflow\r
  USBTD_BABBLE          = BIT(4),  // Babble condition\r
  USBTD_NAK             = BIT(3),  // NAK is received\r
  USBTD_CRC             = BIT(2),  // CRC/Time out error\r
  USBTD_BITSTUFF        = BIT(1)  // Bit stuff error\r
};\r
\r
\r
/**\r
  Read a UHCI register\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use\r
  @param  Offset       Register offset to USB_BAR_INDEX\r
\r
  @return Content of register\r
\r
**/\r
UINT16\r
UhciReadReg (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset\r
  )\r
;\r
\r
\r
\r
/**\r
  Write data to UHCI register\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use\r
  @param  Offset       Register offset to USB_BAR_INDEX\r
  @param  Data         Data to write\r
\r
  @return VOID\r
\r
**/\r
VOID\r
UhciWriteReg (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Data\r
  )\r
;\r
\r
\r
\r
/**\r
  Set a bit of the UHCI Register\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use\r
  @param  Offset       Register offset to USB_BAR_INDEX\r
  @param  Bit          The bit to set\r
\r
  @return None\r
\r
**/\r
VOID\r
UhciSetRegBit (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Bit\r
  )\r
;\r
\r
\r
\r
/**\r
  Clear a bit of the UHCI Register\r
\r
  @param  PciIo        The PCI_IO protocol to access the PCI\r
  @param  Offset       Register offset to USB_BAR_INDEX\r
  @param  Bit          The bit to clear\r
\r
  @return None\r
\r
**/\r
VOID\r
UhciClearRegBit (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN UINT32                  Offset,\r
  IN UINT16                  Bit\r
  )\r
;\r
\r
\r
/**\r
  Clear all the interrutp status bits, these bits\r
  are Write-Clean\r
\r
  @param  Uhc          The UHCI device\r
\r
  @return None\r
\r
**/\r
VOID\r
UhciAckAllInterrupt (\r
  IN  USB_HC_DEV          *Uhc\r
  )\r
;\r
\r
\r
/**\r
  Stop the host controller\r
\r
  @param  Uhc          The UHCI device\r
  @param  Timeout      Max time allowed\r
\r
  @retval EFI_SUCCESS  The host controller is stopped\r
  @retval EFI_TIMEOUT  Failed to stop the host controller\r
\r
**/\r
EFI_STATUS\r
UhciStopHc (\r
  IN USB_HC_DEV         *Uhc,\r
  IN UINTN              Timeout\r
  )\r
;\r
\r
\r
\r
/**\r
  Check whether the host controller operates well\r
\r
  @param  PciIo        The PCI_IO protocol to use\r
\r
  @retval TRUE         Host controller is working\r
  @retval FALSE        Host controller is halted or system error\r
\r
**/\r
BOOLEAN\r
UhciIsHcWorking (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo\r
  )\r
;\r
\r
\r
/**\r
  Set the UHCI frame list base address. It can't use\r
  UhciWriteReg which access memory in UINT16.\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL to use\r
  @param  Addr         Address to set\r
\r
  @return VOID\r
\r
**/\r
VOID\r
UhciSetFrameListBaseAddr (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo,\r
  IN VOID                    *Addr\r
  )\r
;\r
\r
\r
/**\r
  Disable USB Emulation\r
\r
  @param  PciIo        The EFI_PCI_IO_PROTOCOL protocol to use\r
\r
  @return VOID\r
\r
**/\r
VOID\r
UhciTurnOffUsbEmulation (\r
  IN EFI_PCI_IO_PROTOCOL     *PciIo\r
  )\r
;\r
#endif\r
Commit	Line	Data
913cb9dc	1	/** @file\r
913cb9dc	2	\r
b4c24e2d	3	Copyright (c) 2007 - 2008, Intel Corporation\r
913cb9dc	4	All rights reserved. This program and the accompanying materials\r
	5	are licensed and made available under the terms and conditions of the BSD License\r
	6	which accompanies this distribution. The full text of the license may be found at\r
	7	http://opensource.org/licenses/bsd-license.php\r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	\r
	12	Module Name:\r
	13	\r
	14	UhciReg.h\r
	15	\r
	16	Abstract:\r
	17	\r
	18	The definition for UHCI register operation routines.\r
	19	\r
	20	Revision History\r
	21	\r
	22	\r
	23	**/\r
	24	\r
	25	#ifndef _EFI_UHCI_REG_H_\r
	26	#define _EFI_UHCI_REG_H_\r
	27	\r
	28	#define BIT(a) (1 << (a))\r
	29	\r
	30	enum {\r
	31	UHCI_FRAME_NUM = 1024,\r
	32	\r
	33	//\r
	34	// Register offset and PCI related staff\r
	35	//\r
	36	CLASSC_OFFSET = 0x09,\r
	37	USBBASE_OFFSET = 0x20,\r
	38	USB_BAR_INDEX = 4,\r
	39	PCI_CLASSC_PI_UHCI = 0x00,\r
	40	\r
	41	USBCMD_OFFSET = 0,\r
	42	USBSTS_OFFSET = 2,\r
	43	USBINTR_OFFSET = 4,\r
	44	USBPORTSC_OFFSET = 0x10,\r
	45	USB_FRAME_NO_OFFSET = 6,\r
	46	USB_FRAME_BASE_OFFSET = 8,\r
	47	USB_EMULATION_OFFSET = 0xC0,\r
	48	\r
	49	//\r
	50	// Packet IDs\r
	51	//\r
	52	SETUP_PACKET_ID = 0x2D,\r
	53	INPUT_PACKET_ID = 0x69,\r
	54	OUTPUT_PACKET_ID = 0xE1,\r
	55	ERROR_PACKET_ID = 0x55,\r
	56	\r
	57	//\r
	58	// USB port status and control bit definition.\r
	59	//\r
	60	USBPORTSC_CCS = BIT(0), // Current Connect Status\r
	61	USBPORTSC_CSC = BIT(1), // Connect Status Change\r
	62	USBPORTSC_PED = BIT(2), // Port Enable / Disable\r
	63	USBPORTSC_PEDC = BIT(3), // Port Enable / Disable Change\r
	64	USBPORTSC_LSL = BIT(4), // Line Status Low BIT\r
	65	USBPORTSC_LSH = BIT(5), // Line Status High BIT\r
	66	USBPORTSC_RD = BIT(6), // Resume Detect\r
	67	USBPORTSC_LSDA = BIT(8), // Low Speed Device Attached\r
68	USBPORTSC_PR = BIT(9), // Port Reset\r
69	USBPORTSC_SUSP = BIT(12), // Suspend\r
70	\r
b4c24e2d	71	//\r
	72	// UHCI Spec said it must implement 2 ports each host at least,\r
	73	// and if more, check whether the bit7 of PORTSC is always 1.\r
	74	// So here assume the max of port number each host is 16.\r
	75	//\r
	76	USB_MAX_ROOTHUB_PORT = 0x0F,\r
	77	\r
913cb9dc	78	//\r
	79	// Command register bit definitions\r
	80	//\r
	81	USBCMD_RS = BIT(0), // Run/Stop\r
	82	USBCMD_HCRESET = BIT(1), // Host reset\r
	83	USBCMD_GRESET = BIT(2), // Global reset\r
	84	USBCMD_EGSM = BIT(3), // Global Suspend Mode\r
	85	USBCMD_FGR = BIT(4), // Force Global Resume\r
	86	USBCMD_SWDBG = BIT(5), // SW Debug mode\r
	87	USBCMD_CF = BIT(6), // Config Flag (sw only)\r
	88	USBCMD_MAXP = BIT(7), // Max Packet (0 = 32, 1 = 64)\r
	89	\r
	90	//\r
	91	// USB Status register bit definitions\r
	92	//\r
	93	USBSTS_USBINT = BIT(0), // Interrupt due to IOC\r
	94	USBSTS_ERROR = BIT(1), // Interrupt due to error\r
	95	USBSTS_RD = BIT(2), // Resume Detect\r
	96	USBSTS_HSE = BIT(3), // Host System Error\r
	97	USBSTS_HCPE = BIT(4), // Host Controller Process Error\r
	98	USBSTS_HCH = BIT(5), // HC Halted\r
	99	\r
	100	USBTD_ACTIVE = BIT(7), // TD is still active\r
	101	USBTD_STALLED = BIT(6), // TD is stalled\r
	102	USBTD_BUFFERR = BIT(5), // Buffer underflow or overflow\r
	103	USBTD_BABBLE = BIT(4), // Babble condition\r
	104	USBTD_NAK = BIT(3), // NAK is received\r
	105	USBTD_CRC = BIT(2), // CRC/Time out error\r
c52fa98c	106	USBTD_BITSTUFF = BIT(1) // Bit stuff error\r
913cb9dc	107	};\r
	108	\r
	109	\r
	110	/**\r
	111	Read a UHCI register\r
	112	\r
	113	@param PciIo The EFI_PCI_IO_PROTOCOL to use\r
	114	@param Offset Register offset to USB_BAR_INDEX\r
	115	\r
	116	@return Content of register\r
	117	\r
	118	**/\r
	119	UINT16\r
	120	UhciReadReg (\r
	121	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	122	IN UINT32 Offset\r
	123	)\r
	124	;\r
	125	\r
	126	\r
	127	\r
	128	/**\r
	129	Write data to UHCI register\r
	130	\r
	131	@param PciIo The EFI_PCI_IO_PROTOCOL to use\r
	132	@param Offset Register offset to USB_BAR_INDEX\r
	133	@param Data Data to write\r
	134	\r
	135	@return VOID\r
	136	\r
	137	**/\r
	138	VOID\r
	139	UhciWriteReg (\r
	140	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	141	IN UINT32 Offset,\r
	142	IN UINT16 Data\r
	143	)\r
	144	;\r
	145	\r
	146	\r
	147	\r
	148	/**\r
	149	Set a bit of the UHCI Register\r
	150	\r
	151	@param PciIo The EFI_PCI_IO_PROTOCOL to use\r
	152	@param Offset Register offset to USB_BAR_INDEX\r
	153	@param Bit The bit to set\r
	154	\r
	155	@return None\r
	156	\r
	157	**/\r
	158	VOID\r
	159	UhciSetRegBit (\r
	160	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
	161	IN UINT32 Offset,\r
	162	IN UINT16 Bit\r
	163	)\r
	164	;\r
	165	\r
	166	\r
	167	\r
	168	/**\r
	169	Clear a bit of the UHCI Register\r
	170	\r
171	@param PciIo The PCI_IO protocol to access the PCI\r
172	@param Offset Register offset to USB_BAR_INDEX\r
173	@param Bit The bit to clear\r
174	\r
175	@return None\r
176	\r
177	**/\r
178	VOID\r
179	UhciClearRegBit (\r
180	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
181	IN UINT32 Offset,\r
182	IN UINT16 Bit\r
183	)\r
184	;\r
185	\r
186	\r
187	/**\r
188	Clear all the interrutp status bits, these bits\r
189	are Write-Clean\r
190	\r
191	@param Uhc The UHCI device\r
192	\r
193	@return None\r
194	\r
195	**/\r
196	VOID\r
197	UhciAckAllInterrupt (\r
198	IN USB_HC_DEV *Uhc\r
199	)\r
200	;\r
201	\r
202	\r
203	/**\r
204	Stop the host controller\r
205	\r
206	@param Uhc The UHCI device\r
207	@param Timeout Max time allowed\r
208	\r
209	@retval EFI_SUCCESS The host controller is stopped\r
210	@retval EFI_TIMEOUT Failed to stop the host controller\r
211	\r
212	**/\r
213	EFI_STATUS\r
214	UhciStopHc (\r
215	IN USB_HC_DEV *Uhc,\r
216	IN UINTN Timeout\r
217	)\r
218	;\r
219	\r
220	\r
221	\r
222	/**\r
223	Check whether the host controller operates well\r
224	\r
225	@param PciIo The PCI_IO protocol to use\r
226	\r
227	@retval TRUE Host controller is working\r
228	@retval FALSE Host controller is halted or system error\r
229	\r
230	**/\r
231	BOOLEAN\r
232	UhciIsHcWorking (\r
233	IN EFI_PCI_IO_PROTOCOL *PciIo\r
234	)\r
235	;\r
236	\r
237	\r
238	/**\r
239	Set the UHCI frame list base address. It can't use\r
240	UhciWriteReg which access memory in UINT16.\r
241	\r
242	@param PciIo The EFI_PCI_IO_PROTOCOL to use\r
243	@param Addr Address to set\r
244	\r
245	@return VOID\r
246	\r
247	**/\r
248	VOID\r
249	UhciSetFrameListBaseAddr (\r
250	IN EFI_PCI_IO_PROTOCOL *PciIo,\r
251	IN VOID *Addr\r
252	)\r
253	;\r
254	\r
255	\r
256	/**\r
257	Disable USB Emulation\r
258	\r
259	@param PciIo The EFI_PCI_IO_PROTOCOL protocol to use\r
260	\r
261	@return VOID\r
262	\r
263	**/\r
264	VOID\r
265	UhciTurnOffUsbEmulation (\r
266	IN EFI_PCI_IO_PROTOCOL *PciIo\r
267	)\r
268	;\r
269	#endif\r