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MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciPei / UhcPeim.h
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4b1bf81c 1/** @file\r
2Private Header file for Usb Host Controller PEIM\r
3\r
ca243131 4Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
4b1bf81c 5 \r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions\r
8of the BSD License which accompanies this distribution. The\r
9full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#ifndef _RECOVERY_UHC_H_\r
18#define _RECOVERY_UHC_H_\r
19\r
20\r
21#include <PiPei.h>\r
22\r
23#include <Ppi/UsbController.h>\r
24#include <Ppi/UsbHostController.h>\r
25\r
26#include <Library/DebugLib.h>\r
27#include <Library/PeimEntryPoint.h>\r
28#include <Library/PeiServicesLib.h>\r
29#include <Library/BaseMemoryLib.h>\r
30#include <Library/TimerLib.h>\r
31#include <Library/IoLib.h>\r
32#include <Library/PeiServicesLib.h>\r
33\r
34#define USB_SLOW_SPEED_DEVICE 0x01\r
35#define USB_FULL_SPEED_DEVICE 0x02\r
36\r
37//\r
38// One memory block uses 16 page\r
39//\r
40#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16\r
41\r
42#define USBCMD 0 /* Command Register Offset 00-01h */\r
43#define USBCMD_RS BIT0 /* Run/Stop */\r
44#define USBCMD_HCRESET BIT1 /* Host reset */\r
45#define USBCMD_GRESET BIT2 /* Global reset */\r
46#define USBCMD_EGSM BIT3 /* Global Suspend Mode */\r
47#define USBCMD_FGR BIT4 /* Force Global Resume */\r
48#define USBCMD_SWDBG BIT5 /* SW Debug mode */\r
49#define USBCMD_CF BIT6 /* Config Flag (sw only) */\r
50#define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */\r
51\r
52/* Status register */\r
53#define USBSTS 2 /* Status Register Offset 02-03h */\r
54#define USBSTS_USBINT BIT0 /* Interrupt due to IOC */\r
55#define USBSTS_ERROR BIT1 /* Interrupt due to error */\r
56#define USBSTS_RD BIT2 /* Resume Detect */\r
57#define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */\r
58#define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */\r
59#define USBSTS_HCH BIT5 /* HC Halted */\r
60\r
61/* Interrupt enable register */\r
62#define USBINTR 4 /* Interrupt Enable Register 04-05h */\r
63#define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */\r
64#define USBINTR_RESUME BIT1 /* Resume interrupt enable */\r
65#define USBINTR_IOC BIT2 /* Interrupt On Complete enable */\r
66#define USBINTR_SP BIT3 /* Short packet interrupt enable */\r
67\r
68/* Frame Number Register Offset 06-08h */\r
69#define USBFRNUM 6\r
70\r
71/* Frame List Base Address Register Offset 08-0Bh */\r
72#define USBFLBASEADD 8\r
73\r
74/* Start of Frame Modify Register Offset 0Ch */\r
75#define USBSOF 0x0c\r
76\r
77/* USB port status and control registers */\r
78#define USBPORTSC1 0x10 /*Port 1 offset 10-11h */\r
79#define USBPORTSC2 0x12 /*Port 2 offset 12-13h */\r
80\r
81#define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */\r
82#define USBPORTSC_CSC BIT1 /* Connect Status Change */\r
83#define USBPORTSC_PED BIT2 /* Port Enable / Disable */\r
84#define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */\r
85#define USBPORTSC_LSL BIT4 /* Line Status Low bit*/\r
86#define USBPORTSC_LSH BIT5 /* Line Status High bit*/\r
87#define USBPORTSC_RD BIT6 /* Resume Detect */\r
88#define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */\r
89#define USBPORTSC_PR BIT9 /* Port Reset */\r
90#define USBPORTSC_SUSP BIT12 /* Suspend */\r
91\r
92#define SETUP_PACKET_ID 0x2D\r
93#define INPUT_PACKET_ID 0x69\r
94#define OUTPUT_PACKET_ID 0xE1\r
95#define ERROR_PACKET_ID 0x55\r
96\r
ca243131 97#define STALL_1_MICRO_SECOND 1\r
4b1bf81c 98#define STALL_1_MILLI_SECOND 1000\r
99\r
100\r
101#pragma pack(1)\r
102\r
103typedef struct {\r
104 UINT32 FrameListPtrTerminate : 1;\r
105 UINT32 FrameListPtrQSelect : 1;\r
106 UINT32 FrameListRsvd : 2;\r
107 UINT32 FrameListPtr : 28;\r
108} FRAMELIST_ENTRY;\r
109\r
110typedef struct {\r
111 UINT32 QHHorizontalTerminate : 1;\r
112 UINT32 QHHorizontalQSelect : 1;\r
113 UINT32 QHHorizontalRsvd : 2;\r
114 UINT32 QHHorizontalPtr : 28;\r
115 UINT32 QHVerticalTerminate : 1;\r
116 UINT32 QHVerticalQSelect : 1;\r
117 UINT32 QHVerticalRsvd : 2;\r
118 UINT32 QHVerticalPtr : 28;\r
119} QUEUE_HEAD;\r
120\r
121typedef struct {\r
122 QUEUE_HEAD QueueHead;\r
123 UINT32 Reserved1;\r
124 UINT32 Reserved2;\r
125 VOID *PtrNext;\r
126 VOID *PtrDown;\r
127 VOID *Reserved3;\r
128 UINT32 Reserved4;\r
129} QH_STRUCT;\r
130\r
131typedef struct {\r
132 UINT32 TDLinkPtrTerminate : 1;\r
133 UINT32 TDLinkPtrQSelect : 1;\r
134 UINT32 TDLinkPtrDepthSelect : 1;\r
135 UINT32 TDLinkPtrRsvd : 1;\r
136 UINT32 TDLinkPtr : 28;\r
137 UINT32 TDStatusActualLength : 11;\r
138 UINT32 TDStatusRsvd : 5;\r
139 UINT32 TDStatus : 8;\r
140 UINT32 TDStatusIOC : 1;\r
141 UINT32 TDStatusIOS : 1;\r
142 UINT32 TDStatusLS : 1;\r
143 UINT32 TDStatusErr : 2;\r
144 UINT32 TDStatusSPD : 1;\r
145 UINT32 TDStatusRsvd2 : 2;\r
146 UINT32 TDTokenPID : 8;\r
147 UINT32 TDTokenDevAddr : 7;\r
148 UINT32 TDTokenEndPt : 4;\r
149 UINT32 TDTokenDataToggle : 1;\r
150 UINT32 TDTokenRsvd : 1;\r
151 UINT32 TDTokenMaxLen : 11;\r
152 UINT32 TDBufferPtr;\r
153} TD;\r
154\r
155typedef struct {\r
156 TD TDData;\r
157 UINT8 *PtrTDBuffer;\r
158 VOID *PtrNextTD;\r
159 VOID *PtrNextQH;\r
160 UINT16 TDBufferLength;\r
161 UINT16 Reserved;\r
162} TD_STRUCT;\r
163\r
164#pragma pack()\r
165\r
166typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;\r
167\r
168struct _MEMORY_MANAGE_HEADER {\r
169 UINT8 *BitArrayPtr;\r
170 UINTN BitArraySizeInBytes;\r
171 UINT8 *MemoryBlockPtr;\r
172 UINTN MemoryBlockSizeInBytes;\r
173 MEMORY_MANAGE_HEADER *Next;\r
174};\r
175\r
176#define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')\r
177typedef struct {\r
178 UINTN Signature;\r
179 PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;\r
180 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
181\r
182 UINT32 UsbHostControllerBaseAddress;\r
183 FRAMELIST_ENTRY *FrameListEntry;\r
184 QH_STRUCT *ConfigQH;\r
185 QH_STRUCT *BulkQH;\r
186 //\r
187 // Header1 used for QH,TD memory blocks management\r
188 //\r
189 MEMORY_MANAGE_HEADER *Header1;\r
190\r
191} USB_UHC_DEV;\r
192\r
193#define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)\r
194\r
195/**\r
196 Submits control transfer to a target USB device.\r
197 \r
198 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
199 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
200 @param DeviceAddress The target device address.\r
201 @param DeviceSpeed Target device speed.\r
202 @param MaximumPacketLength Maximum packet size the default control transfer \r
203 endpoint is capable of sending or receiving.\r
204 @param Request USB device request to send.\r
205 @param TransferDirection Specifies the data direction for the data stage.\r
206 @param Data Data buffer to be transmitted or received from USB device.\r
207 @param DataLength The size (in bytes) of the data buffer.\r
208 @param TimeOut Indicates the maximum timeout, in millisecond.\r
209 @param TransferResult Return the result of this control transfer.\r
210\r
211 @retval EFI_SUCCESS Transfer was completed successfully.\r
212 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.\r
213 @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
214 @retval EFI_TIMEOUT Transfer failed due to timeout.\r
215 @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.\r
216\r
217**/\r
218EFI_STATUS\r
219EFIAPI\r
220UhcControlTransfer (\r
221 IN EFI_PEI_SERVICES **PeiServices,\r
222 IN PEI_USB_HOST_CONTROLLER_PPI * This,\r
223 IN UINT8 DeviceAddress,\r
224 IN UINT8 DeviceSpeed,\r
225 IN UINT8 MaximumPacketLength,\r
226 IN EFI_USB_DEVICE_REQUEST * Request,\r
227 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
228 IN OUT VOID *Data OPTIONAL,\r
229 IN OUT UINTN *DataLength OPTIONAL,\r
230 IN UINTN TimeOut,\r
231 OUT UINT32 *TransferResult\r
232 );\r
233\r
234/**\r
235 Submits bulk transfer to a bulk endpoint of a USB device.\r
236 \r
237 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
238 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
239 @param DeviceAddress Target device address.\r
240 @param EndPointAddress Endpoint number and its direction in bit 7.\r
241 @param MaximumPacketLength Maximum packet size the endpoint is capable of \r
242 sending or receiving.\r
243 @param Data Array of pointers to the buffers of data to transmit \r
244 from or receive into.\r
245 @param DataLength The lenght of the data buffer.\r
246 @param DataToggle On input, the initial data toggle for the transfer;\r
247 On output, it is updated to to next data toggle to use of \r
248 the subsequent bulk transfer.\r
249 @param TimeOut Indicates the maximum time, in millisecond, which the\r
250 transfer is allowed to complete.\r
251 @param TransferResult A pointer to the detailed result information of the\r
252 bulk transfer.\r
253\r
254 @retval EFI_SUCCESS The transfer was completed successfully.\r
255 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r
256 @retval EFI_INVALID_PARAMETER Parameters are invalid.\r
257 @retval EFI_TIMEOUT The transfer failed due to timeout.\r
258 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r
259\r
260**/\r
261EFI_STATUS\r
262EFIAPI\r
263UhcBulkTransfer (\r
264 IN EFI_PEI_SERVICES **PeiServices,\r
265 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
266 IN UINT8 DeviceAddress,\r
267 IN UINT8 EndPointAddress,\r
268 IN UINT8 MaximumPacketLength,\r
269 IN OUT VOID *Data,\r
270 IN OUT UINTN *DataLength,\r
271 IN OUT UINT8 *DataToggle,\r
272 IN UINTN TimeOut,\r
273 OUT UINT32 *TransferResult\r
274 );\r
275\r
276/**\r
277 Retrieves the number of root hub ports.\r
278\r
279 @param[in] PeiServices The pointer to the PEI Services Table.\r
280 @param[in] This The pointer to this instance of the \r
281 PEI_USB_HOST_CONTROLLER_PPI.\r
282 @param[out] PortNumber The pointer to the number of the root hub ports. \r
283 \r
284 @retval EFI_SUCCESS The port number was retrieved successfully.\r
285 @retval EFI_INVALID_PARAMETER PortNumber is NULL.\r
286\r
287**/\r
288EFI_STATUS\r
289EFIAPI\r
290UhcGetRootHubPortNumber (\r
291 IN EFI_PEI_SERVICES **PeiServices,\r
292 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
293 OUT UINT8 *PortNumber\r
294 );\r
295\r
296/**\r
297 Retrieves the current status of a USB root hub port.\r
298 \r
299 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
300 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
301 @param PortNumber The root hub port to retrieve the state from. \r
302 @param PortStatus Variable to receive the port state.\r
303\r
304 @retval EFI_SUCCESS The status of the USB root hub port specified.\r
305 by PortNumber was returned in PortStatus.\r
306 @retval EFI_INVALID_PARAMETER PortNumber is invalid.\r
307\r
308**/\r
309EFI_STATUS\r
310EFIAPI\r
311UhcGetRootHubPortStatus (\r
312 IN EFI_PEI_SERVICES **PeiServices,\r
313 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
314 IN UINT8 PortNumber,\r
315 OUT EFI_USB_PORT_STATUS *PortStatus\r
316 );\r
317\r
318/**\r
319 Sets a feature for the specified root hub port.\r
320 \r
321 @param PeiServices The pointer of EFI_PEI_SERVICES\r
322 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI\r
323 @param PortNumber Root hub port to set.\r
324 @param PortFeature Feature to set.\r
325\r
326 @retval EFI_SUCCESS The feature specified by PortFeature was set.\r
327 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r
328 @retval EFI_TIMEOUT The time out occurred.\r
329\r
330**/\r
331EFI_STATUS\r
332EFIAPI\r
333UhcSetRootHubPortFeature (\r
334 IN EFI_PEI_SERVICES **PeiServices,\r
335 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
336 IN UINT8 PortNumber,\r
337 IN EFI_USB_PORT_FEATURE PortFeature\r
338 );\r
339\r
340/**\r
341 Clears a feature for the specified root hub port.\r
342 \r
343 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
344 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
345 @param PortNumber Specifies the root hub port whose feature\r
346 is requested to be cleared.\r
347 @param PortFeature Indicates the feature selector associated with the\r
348 feature clear request.\r
349\r
350 @retval EFI_SUCCESS The feature specified by PortFeature was cleared \r
351 for the USB root hub port specified by PortNumber.\r
352 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r
353\r
354**/\r
355EFI_STATUS\r
356EFIAPI\r
357UhcClearRootHubPortFeature (\r
358 IN EFI_PEI_SERVICES **PeiServices,\r
359 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
360 IN UINT8 PortNumber,\r
361 IN EFI_USB_PORT_FEATURE PortFeature\r
362 );\r
363\r
364/**\r
365 Initialize UHCI.\r
366\r
367 @param UhcDev UHCI Device.\r
368\r
369 @retval EFI_SUCCESS UHCI successfully initialized.\r
370 @retval EFI_OUT_OF_RESOURCES Resource can not be allocated.\r
371\r
372**/\r
373EFI_STATUS\r
374InitializeUsbHC (\r
375 IN USB_UHC_DEV *UhcDev\r
376 );\r
377\r
378/**\r
379 Create Frame List Structure.\r
380\r
381 @param UhcDev UHCI device.\r
382\r
383 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
384 @retval EFI_SUCCESS Success.\r
385\r
386**/\r
387EFI_STATUS\r
388CreateFrameList (\r
389 USB_UHC_DEV *UhcDev\r
390 );\r
391\r
392/**\r
393 Read a 16bit width data from Uhc HC IO space register.\r
394 \r
395 @param UhcDev The UHCI device.\r
396 @param Port The IO space address of the register.\r
397\r
398 @retval the register content read.\r
399\r
400**/\r
401UINT16\r
402USBReadPortW (\r
403 IN USB_UHC_DEV *UhcDev,\r
404 IN UINT32 Port\r
405 );\r
406\r
407/**\r
408 Write a 16bit width data into Uhc HC IO space register.\r
409 \r
410 @param UhcDev The UHCI device.\r
411 @param Port The IO space address of the register.\r
412 @param Data The data written into the register.\r
413\r
414**/\r
415VOID\r
416USBWritePortW (\r
417 IN USB_UHC_DEV *UhcDev,\r
418 IN UINT32 Port,\r
419 IN UINT16 Data\r
420 );\r
421\r
422/**\r
423 Write a 32bit width data into Uhc HC IO space register.\r
424 \r
425 @param UhcDev The UHCI device.\r
426 @param Port The IO space address of the register.\r
427 @param Data The data written into the register.\r
428\r
429**/\r
430VOID\r
431USBWritePortDW (\r
432 IN USB_UHC_DEV *UhcDev,\r
433 IN UINT32 Port,\r
434 IN UINT32 Data\r
435 );\r
436\r
437/**\r
438 Clear the content of UHCI's Status Register.\r
439 \r
440 @param UhcDev The UHCI device.\r
441 @param StatusAddr The IO space address of the register.\r
442\r
443**/\r
444VOID\r
445ClearStatusReg (\r
446 IN USB_UHC_DEV *UhcDev,\r
447 IN UINT32 StatusAddr\r
448 );\r
449\r
450/**\r
451 Check whether the host controller operates well.\r
452\r
453 @param UhcDev The UHCI device.\r
454 @param StatusRegAddr The io address of status register.\r
455\r
456 @retval TRUE Host controller is working.\r
457 @retval FALSE Host controller is halted or system error.\r
458\r
459**/\r
460BOOLEAN\r
461IsStatusOK (\r
462 IN USB_UHC_DEV *UhcDev,\r
463 IN UINT32 StatusRegAddr\r
464 );\r
465\r
466/**\r
467 Get Current Frame Number.\r
468\r
469 @param UhcDev The UHCI device.\r
470 @param FrameNumberAddr The address of frame list register.\r
471\r
472 @retval The content of the frame list register.\r
473\r
474**/\r
475UINT16\r
476GetCurrentFrameNumber (\r
477 IN USB_UHC_DEV *UhcDev,\r
478 IN UINT32 FrameNumberAddr\r
479 );\r
480\r
481/**\r
482 Set Frame List Base Address.\r
483\r
484 @param UhcDev The UHCI device.\r
485 @param FrameListRegAddr The address of frame list register.\r
486 @param Addr The address of frame list table.\r
487\r
488**/\r
489VOID\r
490SetFrameListBaseAddress (\r
491 IN USB_UHC_DEV *UhcDev,\r
492 IN UINT32 FrameListRegAddr,\r
493 IN UINT32 Addr\r
494 );\r
495\r
496/**\r
497 Create QH and initialize.\r
498\r
499 @param UhcDev The UHCI device.\r
500 @param PtrQH Place to store QH_STRUCT pointer.\r
501\r
502 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
503 @retval EFI_SUCCESS Success.\r
504\r
505**/\r
506EFI_STATUS\r
507CreateQH (\r
508 IN USB_UHC_DEV *UhcDev,\r
509 OUT QH_STRUCT **PtrQH\r
510 );\r
511\r
512/**\r
513 Set the horizontal link pointer in QH.\r
514\r
515 @param PtrQH Place to store QH_STRUCT pointer.\r
516 @param PtrNext Place to the next QH_STRUCT.\r
517\r
518**/\r
519VOID\r
520SetQHHorizontalLinkPtr (\r
521 IN QH_STRUCT *PtrQH,\r
522 IN VOID *PtrNext\r
523 );\r
524\r
525/**\r
526 Get the horizontal link pointer in QH.\r
527\r
528 @param PtrQH Place to store QH_STRUCT pointer.\r
529\r
530 @retval The horizontal link pointer in QH.\r
531\r
532**/\r
533VOID *\r
534GetQHHorizontalLinkPtr (\r
535 IN QH_STRUCT *PtrQH\r
536 );\r
537\r
538/**\r
539 Set a QH or TD horizontally to be connected with a specific QH.\r
540\r
541 @param PtrQH Place to store QH_STRUCT pointer.\r
542 @param IsQH Specify QH or TD is connected.\r
543\r
544**/\r
545VOID\r
546SetQHHorizontalQHorTDSelect (\r
547 IN QH_STRUCT *PtrQH,\r
548 IN BOOLEAN IsQH\r
549 );\r
550\r
551/**\r
552 Set the horizontal validor bit in QH.\r
553\r
554 @param PtrQH Place to store QH_STRUCT pointer.\r
555 @param IsValid Specify the horizontal linker is valid or not.\r
556\r
557**/\r
558VOID\r
559SetQHHorizontalValidorInvalid (\r
560 IN QH_STRUCT *PtrQH,\r
561 IN BOOLEAN IsValid\r
562 );\r
563\r
564/**\r
565 Set the vertical link pointer in QH.\r
566\r
567 @param PtrQH Place to store QH_STRUCT pointer.\r
568 @param PtrNext Place to the next QH_STRUCT.\r
569\r
570**/\r
571VOID\r
572SetQHVerticalLinkPtr (\r
573 IN QH_STRUCT *PtrQH,\r
574 IN VOID *PtrNext\r
575 );\r
576\r
577/**\r
578 Set a QH or TD vertically to be connected with a specific QH.\r
579\r
580 @param PtrQH Place to store QH_STRUCT pointer.\r
581 @param IsQH Specify QH or TD is connected.\r
582\r
583**/\r
584VOID\r
585SetQHVerticalQHorTDSelect (\r
586 IN QH_STRUCT *PtrQH,\r
587 IN BOOLEAN IsQH\r
588 );\r
589\r
590/**\r
591 Set the vertical validor bit in QH.\r
592\r
593 @param PtrQH Place to store QH_STRUCT pointer.\r
594 @param IsValid Specify the vertical linker is valid or not.\r
595\r
596**/\r
597VOID\r
598SetQHVerticalValidorInvalid (\r
599 IN QH_STRUCT *PtrQH,\r
600 IN BOOLEAN IsValid\r
601 );\r
602\r
603/**\r
604 Get the vertical validor bit in QH.\r
605\r
606 @param PtrQH Place to store QH_STRUCT pointer.\r
607\r
608 @retval The vertical linker is valid or not.\r
609\r
610**/\r
611BOOLEAN\r
612GetQHHorizontalValidorInvalid (\r
613 IN QH_STRUCT *PtrQH\r
614 );\r
615\r
616/**\r
617 Allocate TD or QH Struct.\r
618\r
619 @param UhcDev The UHCI device.\r
620 @param Size The size of allocation.\r
621 @param PtrStruct Place to store TD_STRUCT pointer.\r
622\r
623 @return EFI_SUCCESS Allocate successfully.\r
624 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
625\r
626**/\r
627EFI_STATUS\r
628AllocateTDorQHStruct (\r
629 IN USB_UHC_DEV *UhcDev,\r
630 IN UINT32 Size,\r
631 OUT VOID **PtrStruct\r
632 );\r
633\r
634/**\r
635 Create a TD Struct.\r
636\r
637 @param UhcDev The UHCI device.\r
638 @param PtrTD Place to store TD_STRUCT pointer.\r
639\r
640 @return EFI_SUCCESS Allocate successfully.\r
641 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
642\r
643**/\r
644EFI_STATUS\r
645CreateTD (\r
646 IN USB_UHC_DEV *UhcDev,\r
647 OUT TD_STRUCT **PtrTD\r
648 );\r
649\r
650/**\r
651 Generate Setup Stage TD.\r
652\r
653 @param UhcDev The UHCI device.\r
654 @param DevAddr Device address.\r
655 @param Endpoint Endpoint number.\r
656 @param DeviceSpeed Device Speed.\r
657 @param DevRequest Device reuquest.\r
658 @param RequestLen Request length.\r
659 @param PtrTD TD_STRUCT generated.\r
660\r
661 @return EFI_SUCCESS Generate setup stage TD successfully.\r
662 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
663\r
664**/\r
665EFI_STATUS\r
666GenSetupStageTD (\r
667 IN USB_UHC_DEV *UhcDev,\r
668 IN UINT8 DevAddr,\r
669 IN UINT8 Endpoint,\r
670 IN UINT8 DeviceSpeed,\r
671 IN UINT8 *DevRequest,\r
672 IN UINT8 RequestLen,\r
673 OUT TD_STRUCT **PtrTD\r
674 );\r
675\r
676/**\r
677 Generate Data Stage TD.\r
678\r
679 @param UhcDev The UHCI device.\r
680 @param DevAddr Device address.\r
681 @param Endpoint Endpoint number.\r
682 @param PtrData Data buffer.\r
683 @param Len Data length.\r
684 @param PktID PacketID.\r
685 @param Toggle Data toggle value.\r
686 @param DeviceSpeed Device Speed.\r
687 @param PtrTD TD_STRUCT generated.\r
688\r
689 @return EFI_SUCCESS Generate data stage TD successfully.\r
690 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
691\r
692**/\r
693EFI_STATUS\r
694GenDataTD (\r
695 IN USB_UHC_DEV *UhcDev,\r
696 IN UINT8 DevAddr,\r
697 IN UINT8 Endpoint,\r
698 IN UINT8 *PtrData,\r
699 IN UINT8 Len,\r
700 IN UINT8 PktID,\r
701 IN UINT8 Toggle,\r
702 IN UINT8 DeviceSpeed,\r
703 OUT TD_STRUCT **PtrTD\r
704 );\r
705\r
706/**\r
707 Generate Status Stage TD.\r
708\r
709 @param UhcDev The UHCI device.\r
710 @param DevAddr Device address.\r
711 @param Endpoint Endpoint number.\r
712 @param PktID PacketID.\r
713 @param DeviceSpeed Device Speed.\r
714 @param PtrTD TD_STRUCT generated.\r
715\r
716 @return EFI_SUCCESS Generate status stage TD successfully.\r
717 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
718\r
719**/\r
720EFI_STATUS\r
721CreateStatusTD (\r
722 IN USB_UHC_DEV *UhcDev,\r
723 IN UINT8 DevAddr,\r
724 IN UINT8 Endpoint,\r
725 IN UINT8 PktID,\r
726 IN UINT8 DeviceSpeed,\r
727 OUT TD_STRUCT **PtrTD\r
728 );\r
729\r
730/**\r
731 Set the link pointer validor bit in TD.\r
732\r
733 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
734 @param IsValid Specify the linker pointer is valid or not.\r
735\r
736**/\r
737VOID\r
738SetTDLinkPtrValidorInvalid (\r
739 IN TD_STRUCT *PtrTDStruct,\r
740 IN BOOLEAN IsValid\r
741 );\r
742\r
743/**\r
744 Set the Link Pointer pointing to a QH or TD.\r
745\r
746 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
747 @param IsQH Specify QH or TD is connected.\r
748\r
749**/\r
750VOID\r
751SetTDLinkPtrQHorTDSelect (\r
752 IN TD_STRUCT *PtrTDStruct,\r
753 IN BOOLEAN IsQH\r
754 );\r
755\r
756/**\r
757 Set the traverse is depth-first or breadth-first.\r
758\r
759 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
760 @param IsDepth Specify the traverse is depth-first or breadth-first.\r
761\r
762**/\r
763VOID\r
764SetTDLinkPtrDepthorBreadth (\r
765 IN TD_STRUCT *PtrTDStruct,\r
766 IN BOOLEAN IsDepth\r
767 );\r
768\r
769/**\r
770 Set TD Link Pointer in TD.\r
771\r
772 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
773 @param PtrNext Place to the next TD_STRUCT.\r
774\r
775**/\r
776VOID\r
777SetTDLinkPtr (\r
778 IN TD_STRUCT *PtrTDStruct,\r
779 IN VOID *PtrNext\r
780 );\r
781\r
782/**\r
783 Get TD Link Pointer.\r
784\r
785 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
786\r
787 @retval Get TD Link Pointer in TD.\r
788\r
789**/\r
790VOID*\r
791GetTDLinkPtr (\r
792 IN TD_STRUCT *PtrTDStruct\r
793 );\r
794\r
795/**\r
796 Get the information about whether the Link Pointer field pointing to\r
797 a QH or a TD.\r
798\r
799 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
800\r
801 @retval whether the Link Pointer field pointing to a QH or a TD.\r
802\r
803**/\r
804BOOLEAN\r
805IsTDLinkPtrQHOrTD (\r
806 IN TD_STRUCT *PtrTDStruct\r
807 );\r
808\r
809/**\r
810 Enable/Disable short packet detection mechanism.\r
811\r
812 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
813 @param IsEnable Enable or disable short packet detection mechanism.\r
814\r
815**/\r
816VOID\r
817EnableorDisableTDShortPacket (\r
818 IN TD_STRUCT *PtrTDStruct,\r
819 IN BOOLEAN IsEnable\r
820 );\r
821\r
822/**\r
823 Set the max error counter in TD.\r
824\r
825 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
826 @param MaxErrors The number of allowable error.\r
827\r
828**/\r
829VOID\r
830SetTDControlErrorCounter (\r
831 IN TD_STRUCT *PtrTDStruct,\r
832 IN UINT8 MaxErrors\r
833 );\r
834\r
835/**\r
836 Set the TD is targeting a low-speed device or not.\r
837\r
838 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
839 @param IsLowSpeedDevice Whether The device is low-speed.\r
840\r
841**/\r
842VOID\r
843SetTDLoworFullSpeedDevice (\r
844 IN TD_STRUCT *PtrTDStruct,\r
845 IN BOOLEAN IsLowSpeedDevice\r
846 );\r
847\r
848/**\r
849 Set the TD is isochronous transfer type or not.\r
850\r
851 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
852 @param IsIsochronous Whether the transaction isochronous transfer type.\r
853\r
854**/\r
855VOID\r
856SetTDControlIsochronousorNot (\r
857 IN TD_STRUCT *PtrTDStruct,\r
858 IN BOOLEAN IsIsochronous\r
859 );\r
860\r
861/**\r
862 Set if UCHI should issue an interrupt on completion of the frame\r
863 in which this TD is executed\r
864\r
865 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
866 @param IsSet Whether HC should issue an interrupt on completion.\r
867\r
868**/\r
869VOID\r
870SetorClearTDControlIOC (\r
871 IN TD_STRUCT *PtrTDStruct,\r
872 IN BOOLEAN IsSet\r
873 );\r
874\r
875/**\r
876 Set if the TD is active and can be executed.\r
877\r
878 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
879 @param IsActive Whether the TD is active and can be executed.\r
880\r
881**/\r
882VOID\r
883SetTDStatusActiveorInactive (\r
884 IN TD_STRUCT *PtrTDStruct,\r
885 IN BOOLEAN IsActive\r
886 );\r
887\r
888/**\r
889 Specifies the maximum number of data bytes allowed for the transfer.\r
890\r
891 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
892 @param MaxLen The maximum number of data bytes allowed.\r
893\r
894 @retval The allowed maximum number of data.\r
895**/\r
896UINT16\r
897SetTDTokenMaxLength (\r
898 IN TD_STRUCT *PtrTDStruct,\r
899 IN UINT16 MaxLen\r
900 );\r
901\r
902/**\r
903 Set the data toggle bit to DATA1.\r
904\r
905 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
906\r
907**/\r
908VOID\r
909SetTDTokenDataToggle1 (\r
910 IN TD_STRUCT *PtrTDStruct\r
911 );\r
912\r
913/**\r
914 Set the data toggle bit to DATA0.\r
915\r
916 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
917\r
918**/\r
919VOID\r
920SetTDTokenDataToggle0 (\r
921 IN TD_STRUCT *PtrTDStruct\r
922 );\r
923\r
924/**\r
925 Set EndPoint Number the TD is targeting at.\r
926\r
927 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
928 @param EndPoint The Endport number of the target.\r
929\r
930**/\r
931VOID\r
932SetTDTokenEndPoint (\r
933 IN TD_STRUCT *PtrTDStruct,\r
934 IN UINTN EndPoint\r
935 );\r
936\r
937/**\r
938 Set Device Address the TD is targeting at.\r
939\r
940 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
941 @param DevAddr The Device Address of the target.\r
942\r
943**/\r
944VOID\r
945SetTDTokenDeviceAddress (\r
946 IN TD_STRUCT *PtrTDStruct,\r
947 IN UINTN DevAddr\r
948 );\r
949\r
950/**\r
951 Set Packet Identification the TD is targeting at.\r
952\r
953 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
954 @param PacketID The Packet Identification of the target.\r
955\r
956**/\r
957VOID\r
958SetTDTokenPacketID (\r
959 IN TD_STRUCT *PtrTDStruct,\r
960 IN UINT8 PacketID\r
961 );\r
962\r
963/**\r
964 Set the beginning address of the data buffer that will be used\r
965 during the transaction.\r
966\r
967 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
968\r
969**/\r
970VOID\r
971SetTDDataBuffer (\r
972 IN TD_STRUCT *PtrTDStruct\r
973 );\r
974\r
975/**\r
976 Detect whether the TD is active.\r
977\r
978 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
979\r
980 @retval The TD is active or not.\r
981\r
982**/\r
983BOOLEAN\r
984IsTDStatusActive (\r
985 IN TD_STRUCT *PtrTDStruct\r
986 );\r
987\r
988/**\r
989 Detect whether the TD is stalled.\r
990\r
991 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
992\r
993 @retval The TD is stalled or not.\r
994\r
995**/\r
996BOOLEAN\r
997IsTDStatusStalled (\r
998 IN TD_STRUCT *PtrTDStruct\r
999 );\r
1000\r
1001/**\r
1002 Detect whether Data Buffer Error is happened.\r
1003\r
1004 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1005\r
1006 @retval The Data Buffer Error is happened or not.\r
1007\r
1008**/\r
1009BOOLEAN\r
1010IsTDStatusBufferError (\r
1011 IN TD_STRUCT *PtrTDStruct\r
1012 );\r
1013\r
1014/**\r
1015 Detect whether Babble Error is happened.\r
1016\r
1017 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1018\r
1019 @retval The Babble Error is happened or not.\r
1020\r
1021**/\r
1022BOOLEAN\r
1023IsTDStatusBabbleError (\r
1024 IN TD_STRUCT *PtrTDStruct\r
1025 );\r
1026\r
1027/**\r
1028 Detect whether NAK is received.\r
1029\r
1030 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1031\r
1032 @retval The NAK is received or not.\r
1033\r
1034**/\r
1035BOOLEAN\r
1036IsTDStatusNAKReceived (\r
1037 IN TD_STRUCT *PtrTDStruct\r
1038 );\r
1039\r
1040/**\r
1041 Detect whether CRC/Time Out Error is encountered.\r
1042\r
1043 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1044\r
1045 @retval The CRC/Time Out Error is encountered or not.\r
1046\r
1047**/\r
1048BOOLEAN\r
1049IsTDStatusCRCTimeOutError (\r
1050 IN TD_STRUCT *PtrTDStruct\r
1051 );\r
1052\r
1053/**\r
1054 Detect whether Bitstuff Error is received.\r
1055\r
1056 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1057\r
1058 @retval The Bitstuff Error is received or not.\r
1059\r
1060**/\r
1061BOOLEAN\r
1062IsTDStatusBitStuffError (\r
1063 IN TD_STRUCT *PtrTDStruct\r
1064 );\r
1065\r
1066/**\r
1067 Retrieve the actual number of bytes that were tansferred.\r
1068\r
1069 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1070\r
1071 @retval The actual number of bytes that were tansferred.\r
1072\r
1073**/\r
1074UINT16\r
1075GetTDStatusActualLength (\r
1076 IN TD_STRUCT *PtrTDStruct\r
1077 );\r
1078\r
1079/**\r
1080 Retrieve the information of whether the Link Pointer field is valid or not.\r
1081\r
1082 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1083\r
1084 @retval The linker pointer field is valid or not.\r
1085\r
1086**/\r
1087BOOLEAN\r
1088GetTDLinkPtrValidorInvalid (\r
1089 IN TD_STRUCT *PtrTDStruct\r
1090 );\r
1091\r
1092/**\r
1093 Count TD Number from PtrFirstTD.\r
1094\r
1095 @param PtrFirstTD Place to store TD_STRUCT pointer.\r
1096\r
1097 @retval The queued TDs number.\r
1098\r
1099**/\r
1100UINTN\r
1101CountTDsNumber (\r
1102 IN TD_STRUCT *PtrFirstTD\r
1103 );\r
1104\r
1105/**\r
1106 Link TD To QH.\r
1107\r
1108 @param PtrQH Place to store QH_STRUCT pointer.\r
1109 @param PtrTD Place to store TD_STRUCT pointer.\r
1110\r
1111**/\r
1112VOID\r
1113LinkTDToQH (\r
1114 IN QH_STRUCT *PtrQH,\r
1115 IN TD_STRUCT *PtrTD\r
1116 );\r
1117\r
1118/**\r
1119 Link TD To TD.\r
1120\r
1121 @param PtrPreTD Place to store TD_STRUCT pointer.\r
1122 @param PtrTD Place to store TD_STRUCT pointer.\r
1123\r
1124**/\r
1125VOID\r
1126LinkTDToTD (\r
1127 IN TD_STRUCT *PtrPreTD,\r
1128 IN TD_STRUCT *PtrTD\r
1129 );\r
1130\r
1131/**\r
1132 Execute Control Transfer.\r
1133\r
1134 @param UhcDev The UCHI device.\r
1135 @param PtrTD A pointer to TD_STRUCT data.\r
1136 @param ActualLen Actual transfer Length.\r
1137 @param TimeOut TimeOut value.\r
1138 @param TransferResult Transfer Result.\r
1139\r
1140 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
1141 @return EFI_TIMEOUT The transfer failed due to time out.\r
1142 @return EFI_SUCCESS The transfer finished OK.\r
1143\r
1144**/\r
1145EFI_STATUS\r
1146ExecuteControlTransfer (\r
1147 IN USB_UHC_DEV *UhcDev,\r
1148 IN TD_STRUCT *PtrTD,\r
1149 OUT UINTN *ActualLen,\r
1150 IN UINTN TimeOut,\r
1151 OUT UINT32 *TransferResult\r
1152 );\r
1153\r
1154/**\r
1155 Execute Bulk Transfer.\r
1156\r
1157 @param UhcDev The UCHI device.\r
1158 @param PtrTD A pointer to TD_STRUCT data.\r
1159 @param ActualLen Actual transfer Length.\r
1160 @param DataToggle DataToggle value.\r
1161 @param TimeOut TimeOut value.\r
1162 @param TransferResult Transfer Result.\r
1163\r
1164 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
1165 @return EFI_TIMEOUT The transfer failed due to time out.\r
1166 @return EFI_SUCCESS The transfer finished OK.\r
1167\r
1168**/\r
1169EFI_STATUS\r
1170ExecBulkTransfer (\r
1171 IN USB_UHC_DEV *UhcDev,\r
1172 IN TD_STRUCT *PtrTD,\r
1173 IN OUT UINTN *ActualLen,\r
1174 IN UINT8 *DataToggle,\r
1175 IN UINTN TimeOut,\r
1176 OUT UINT32 *TransferResult\r
1177 );\r
1178\r
1179/**\r
1180 Delete Queued TDs.\r
1181\r
1182 @param UhcDev The UCHI device.\r
1183 @param PtrFirstTD Place to store TD_STRUCT pointer.\r
1184\r
1185**/\r
1186VOID\r
1187DeleteQueuedTDs (\r
1188 IN USB_UHC_DEV *UhcDev,\r
1189 IN TD_STRUCT *PtrFirstTD\r
1190 );\r
1191\r
1192/**\r
1193 Check TDs Results.\r
1194\r
1195 @param PtrTD A pointer to TD_STRUCT data.\r
1196 @param Result The result to return.\r
1197 @param ErrTDPos The Error TD position.\r
1198 @param ActualTransferSize Actual transfer size.\r
1199\r
1200 @retval The TD is executed successfully or not.\r
1201\r
1202**/\r
1203BOOLEAN\r
1204CheckTDsResults (\r
1205 IN TD_STRUCT *PtrTD,\r
1206 OUT UINT32 *Result,\r
1207 OUT UINTN *ErrTDPos,\r
1208 OUT UINTN *ActualTransferSize\r
1209 );\r
1210\r
1211/**\r
1212 Create Memory Block.\r
1213\r
1214 @param UhcDev The UCHI device.\r
1215 @param MemoryHeader The Pointer to allocated memory block.\r
1216 @param MemoryBlockSizeInPages The page size of memory block to be allocated.\r
1217\r
1218 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1219 @retval EFI_SUCCESS Success.\r
1220\r
1221**/\r
1222EFI_STATUS\r
1223CreateMemoryBlock (\r
1224 IN USB_UHC_DEV *UhcDev,\r
1225 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
1226 IN UINTN MemoryBlockSizeInPages\r
1227 );\r
1228\r
1229/**\r
1230 Initialize UHCI memory management.\r
1231\r
1232 @param UhcDev The UCHI device.\r
1233\r
1234 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1235 @retval EFI_SUCCESS Success.\r
1236\r
1237**/\r
1238EFI_STATUS\r
1239InitializeMemoryManagement (\r
1240 IN USB_UHC_DEV *UhcDev\r
1241 );\r
1242\r
1243/**\r
1244 Initialize UHCI memory management.\r
1245\r
1246 @param UhcDev The UCHI device.\r
1247 @param Pool Buffer pointer to store the buffer pointer.\r
1248 @param AllocSize The size of the pool to be allocated.\r
1249\r
1250 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1251 @retval EFI_SUCCESS Success.\r
1252\r
1253**/\r
1254EFI_STATUS\r
1255UhcAllocatePool (\r
1256 IN USB_UHC_DEV *UhcDev,\r
1257 OUT UINT8 **Pool,\r
1258 IN UINTN AllocSize\r
1259 );\r
1260\r
1261/**\r
1262 Alloc Memory In MemoryBlock.\r
1263\r
1264 @param MemoryHeader The pointer to memory manage header.\r
1265 @param Pool Buffer pointer to store the buffer pointer.\r
1266 @param NumberOfMemoryUnit The size of the pool to be allocated.\r
1267\r
1268 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1269 @retval EFI_SUCCESS Success.\r
1270\r
1271**/\r
1272EFI_STATUS\r
1273AllocMemInMemoryBlock (\r
1274 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
1275 OUT VOID **Pool,\r
1276 IN UINTN NumberOfMemoryUnit\r
1277 );\r
1278\r
1279/**\r
1280 Uhci Free Pool.\r
1281\r
1282 @param UhcDev The UHCI device.\r
1283 @param Pool A pointer to store the buffer address.\r
1284 @param AllocSize The size of the pool to be freed.\r
1285\r
1286**/\r
1287VOID\r
1288UhcFreePool (\r
1289 IN USB_UHC_DEV *UhcDev,\r
1290 IN UINT8 *Pool,\r
1291 IN UINTN AllocSize\r
1292 );\r
1293\r
1294/**\r
1295 Insert a new memory header into list.\r
1296\r
1297 @param MemoryHeader A pointer to the memory header list.\r
1298 @param NewMemoryHeader A new memory header to be inserted into the list.\r
1299\r
1300**/\r
1301VOID\r
1302InsertMemoryHeaderToList (\r
1303 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
1304 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
1305 );\r
1306\r
1307/**\r
1308 Judge the memory block in the memory header is empty or not.\r
1309\r
1310 @param MemoryHeaderPtr A pointer to the memory header list.\r
1311\r
1312 @retval Whether the memory block in the memory header is empty or not.\r
1313\r
1314**/\r
1315BOOLEAN\r
1316IsMemoryBlockEmptied (\r
1317 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
1318 );\r
1319\r
1320/**\r
1321 remove a memory header from list.\r
1322\r
1323 @param FirstMemoryHeader A pointer to the memory header list.\r
1324 @param FreeMemoryHeader A memory header to be removed into the list.\r
1325\r
1326**/\r
1327VOID\r
1328DelinkMemoryBlock (\r
1329 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
1330 IN MEMORY_MANAGE_HEADER *FreeMemoryHeader\r
1331 );\r
1332\r
1333#endif\r
EFI Development Kit II mirror for PVE