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1/** @file\r
2\r
3 This file contains the definination for host controller memory management routines.\r
4\r
d1102dba 5Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
9d510e61 6SPDX-License-Identifier: BSD-2-Clause-Patent\r
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7\r
8**/\r
9\r
10#ifndef _EFI_XHCI_MEM_H_\r
11#define _EFI_XHCI_MEM_H_\r
12\r
13#define USB_HC_BIT(a) ((UINTN)(1 << (a)))\r
14\r
15#define USB_HC_BIT_IS_SET(Data, Bit) \\r
16 ((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))\r
17\r
18typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;\r
19struct _USBHC_MEM_BLOCK {\r
20 UINT8 *Bits; // Bit array to record which unit is allocated\r
21 UINTN BitsLen;\r
22 UINT8 *Buf;\r
23 UINT8 *BufHost;\r
24 UINTN BufLen; // Memory size in bytes\r
25 VOID *Mapping;\r
26 USBHC_MEM_BLOCK *Next;\r
27};\r
28\r
29//\r
30// USBHC_MEM_POOL is used to manage the memory used by USB\r
31// host controller. XHCI requires the control memory and transfer\r
32// data to be on the same 4G memory.\r
33//\r
34typedef struct _USBHC_MEM_POOL {\r
35 EFI_PCI_IO_PROTOCOL *PciIo;\r
36 BOOLEAN Check4G;\r
37 UINT32 Which4G;\r
38 USBHC_MEM_BLOCK *Head;\r
39} USBHC_MEM_POOL;\r
40\r
41//\r
42// Memory allocation unit, must be 2^n, n>4\r
43//\r
44#define USBHC_MEM_UNIT 64\r
45\r
46#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)\r
47#define USBHC_MEM_DEFAULT_PAGES 16\r
48\r
49#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))\r
50\r
51//\r
52// Advance the byte and bit to the next bit, adjust byte accordingly.\r
53//\r
54#define NEXT_BIT(Byte, Bit) \\r
55 do { \\r
56 (Bit)++; \\r
57 if ((Bit) > 7) { \\r
58 (Byte)++; \\r
59 (Bit) = 0; \\r
60 } \\r
61 } while (0)\r
62\r
63\r
64\r
65/**\r
66 Initialize the memory management pool for the host controller.\r
67\r
68 @param PciIo The PciIo that can be used to access the host controller.\r
69\r
70 @retval EFI_SUCCESS The memory pool is initialized.\r
71 @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.\r
72\r
73**/\r
74USBHC_MEM_POOL *\r
75UsbHcInitMemPool (\r
76 IN EFI_PCI_IO_PROTOCOL *PciIo\r
77 );\r
78\r
79\r
80/**\r
81 Release the memory management pool.\r
82\r
83 @param Pool The USB memory pool to free.\r
84\r
85 @retval EFI_SUCCESS The memory pool is freed.\r
86 @retval EFI_DEVICE_ERROR Failed to free the memory pool.\r
87\r
88**/\r
89EFI_STATUS\r
90UsbHcFreeMemPool (\r
91 IN USBHC_MEM_POOL *Pool\r
92 );\r
93\r
94\r
95/**\r
96 Allocate some memory from the host controller's memory pool\r
97 which can be used to communicate with host controller.\r
98\r
99 @param Pool The host controller's memory pool.\r
100 @param Size Size of the memory to allocate.\r
101\r
102 @return The allocated memory or NULL.\r
103\r
104**/\r
105VOID *\r
106UsbHcAllocateMem (\r
107 IN USBHC_MEM_POOL *Pool,\r
108 IN UINTN Size\r
109 );\r
110\r
111\r
112/**\r
113 Free the allocated memory back to the memory pool.\r
114\r
115 @param Pool The memory pool of the host controller.\r
116 @param Mem The memory to free.\r
117 @param Size The size of the memory to free.\r
118\r
119**/\r
120VOID\r
121UsbHcFreeMem (\r
122 IN USBHC_MEM_POOL *Pool,\r
123 IN VOID *Mem,\r
124 IN UINTN Size\r
125 );\r
126\r
127/**\r
128 Calculate the corresponding pci bus address according to the Mem parameter.\r
129\r
130 @param Pool The memory pool of the host controller.\r
131 @param Mem The pointer to host memory.\r
132 @param Size The size of the memory region.\r
133\r
134 @return The pci memory address\r
135\r
136**/\r
137EFI_PHYSICAL_ADDRESS\r
138UsbHcGetPciAddrForHostAddr (\r
139 IN USBHC_MEM_POOL *Pool,\r
140 IN VOID *Mem,\r
141 IN UINTN Size\r
142 );\r
143\r
144/**\r
145 Calculate the corresponding host address according to the pci address.\r
146\r
147 @param Pool The memory pool of the host controller.\r
148 @param Mem The pointer to pci memory.\r
149 @param Size The size of the memory region.\r
150\r
151 @return The host memory address\r
152\r
153**/\r
154EFI_PHYSICAL_ADDRESS\r
155UsbHcGetHostAddrForPciAddr (\r
156 IN USBHC_MEM_POOL *Pool,\r
157 IN VOID *Mem,\r
158 IN UINTN Size\r
159 );\r
160\r
d1102dba 161/**\r
1847ed0b 162 Allocates pages at a specified alignment that are suitable for an EfiPciIoOperationBusMasterCommonBuffer mapping.\r
d1102dba 163\r
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164 If Alignment is not a power of two and Alignment is not zero, then ASSERT().\r
165\r
166 @param PciIo The PciIo that can be used to access the host controller.\r
167 @param Pages The number of pages to allocate.\r
168 @param Alignment The requested alignment of the allocation. Must be a power of two.\r
169 @param HostAddress The system memory address to map to the PCI controller.\r
d1102dba 170 @param DeviceAddress The resulting map address for the bus master PCI controller to\r
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171 use to access the hosts HostAddress.\r
172 @param Mapping A resulting value to pass to Unmap().\r
173\r
174 @retval EFI_SUCCESS Success to allocate aligned pages.\r
175 @retval EFI_INVALID_PARAMETER Pages or Alignment is not valid.\r
176 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to allocate memory.\r
d1102dba 177\r
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178\r
179**/\r
180EFI_STATUS\r
181UsbHcAllocateAlignedPages (\r
182 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
183 IN UINTN Pages,\r
184 IN UINTN Alignment,\r
185 OUT VOID **HostAddress,\r
186 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
187 OUT VOID **Mapping\r
188 );\r
d1102dba 189\r
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190/**\r
191 Frees memory that was allocated with UsbHcAllocateAlignedPages().\r
d1102dba 192\r
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193 @param PciIo The PciIo that can be used to access the host controller.\r
194 @param HostAddress The system memory address to map to the PCI controller.\r
195 @param Pages The number of pages to free.\r
196 @param Mapping The mapping value returned from Map().\r
197\r
198**/\r
199VOID\r
200UsbHcFreeAlignedPages (\r
201 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
202 IN VOID *HostAddress,\r
203 IN UINTN Pages,\r
204 VOID *Mapping\r
205 );\r
206\r
207#endif\r