MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.c

/** @file\r
\r
  The XHCI register operation routines.\r
\r
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "Xhci.h"\r
\r
/**\r
  Read 1-byte width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 1-byte width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFF.\r
\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  )\r
{\r
  UINT8                   Data;\r
  EFI_STATUS              Status;\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint8,\r
                             XHC_BAR_INDEX,\r
                             (UINT64) Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));\r
    Data = 0xFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Read 4-bytes width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  )\r
{\r
  UINT32                  Data;\r
  EFI_STATUS              Status;\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             (UINT64) Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Read 4-bytes width XHCI Operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width operational register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadOpReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  )\r
{\r
  UINT32                  Data;\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Xhc->CapLength != 0);\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->CapLength + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the 4-bytes width XHCI operational register.\r
\r
  @param  Xhc      The XHCI Instance.\r
  @param  Offset   The offset of the 4-bytes width operational register.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Xhc->CapLength != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->CapLength + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
\r
\r
\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Xhc->DBOff != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->DBOff + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  )\r
{\r
  UINT32                  Data;\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Xhc->RTSOff != 0);\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->RTSOff + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Xhc->RTSOff != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->RTSOff + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
/**\r
  Read XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  )\r
{\r
  UINT32                  Data;\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Xhc->ExtCapRegBase != 0);\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->ExtCapRegBase + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteExtCapReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  ASSERT (Xhc->ExtCapRegBase != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->ExtCapRegBase + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  )\r
{\r
  UINT32                  Data;\r
\r
  Data  = XhcReadRuntimeReg (Xhc, Offset);\r
  Data |= Bit;\r
  XhcWriteRuntimeReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  )\r
{\r
  UINT32                  Data;\r
\r
  Data  = XhcReadRuntimeReg (Xhc, Offset);\r
  Data &= ~Bit;\r
  XhcWriteRuntimeReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  )\r
{\r
  UINT32                  Data;\r
\r
  Data  = XhcReadOpReg (Xhc, Offset);\r
  Data |= Bit;\r
  XhcWriteOpReg (Xhc, Offset, Data);\r
}\r
\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  )\r
{\r
  UINT32                  Data;\r
\r
  Data  = XhcReadOpReg (Xhc, Offset);\r
  Data &= ~Bit;\r
  XhcWriteOpReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to become set (or clear).\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operation register.\r
  @param  Bit          The bit of the register to wait for.\r
  @param  WaitToSet    Wait the bit to set or clear.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT  The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit,\r
  IN BOOLEAN              WaitToSet,\r
  IN UINT32               Timeout\r
  )\r
{\r
  UINT32                  Index;\r
  UINT64                  Loop;\r
\r
  Loop   = Timeout * XHC_1_MILLISECOND;\r
\r
  for (Index = 0; Index < Loop; Index++) {\r
    if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
      return EFI_SUCCESS;\r
    }\r
\r
    gBS->Stall (XHC_1_MICROSECOND);\r
  }\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Set Bios Ownership\r
\r
  @param  Xhc          The XHCI Instance.\r
\r
**/\r
VOID\r
XhcSetBiosOwnership (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  )\r
{\r
  UINT32                    Buffer;\r
\r
  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
    return;\r
  }\r
\r
  DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));\r
\r
  Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
  Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);\r
  XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);\r
}\r
\r
/**\r
  Clear Bios Ownership\r
\r
  @param  Xhc       The XHCI Instance.\r
\r
**/\r
VOID\r
XhcClearBiosOwnership (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  )\r
{\r
  UINT32                    Buffer;\r
\r
  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
    return;\r
  }\r
\r
  DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));\r
\r
  Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
  Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);\r
  XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);\r
}\r
\r
/**\r
  Calculate the offset of the XHCI capability.\r
\r
  @param  Xhc     The XHCI Instance.\r
  @param  CapId   The XHCI Capability ID.\r
\r
  @return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetCapabilityAddr (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT8                CapId\r
  )\r
{\r
  UINT32 ExtCapOffset;\r
  UINT8  NextExtCapReg;\r
  UINT32 Data;\r
\r
  ExtCapOffset = 0;\r
\r
  do {\r
    //\r
    // Check if the extended capability register's capability id is USB Legacy Support.\r
    //\r
    Data = XhcReadExtCapReg (Xhc, ExtCapOffset);\r
    if ((Data & 0xFF) == CapId) {\r
      return ExtCapOffset;\r
    }\r
    //\r
    // If not, then traverse all of the ext capability registers till finding out it.\r
    //\r
    NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);\r
    ExtCapOffset += (NextExtCapReg << 2);\r
  } while (NextExtCapReg != 0);\r
\r
  return 0xFFFFFFFF;\r
}\r
\r
/**\r
  Whether the XHCI host controller is halted.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  )\r
{\r
  return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);\r
}\r
\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Xhc      The XHCI Instance.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  )\r
{\r
  return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);\r
}\r
\r
/**\r
  Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set.\r
\r
  The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller Reset(HCRST).\r
  This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
\r
  @param Xhc            The XHCI Instance.\r
\r
**/\r
VOID\r
XhcSetHsee (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  )\r
{\r
  EFI_STATUS            Status;\r
  EFI_PCI_IO_PROTOCOL   *PciIo;\r
  UINT16                XhciCmd;\r
\r
  PciIo = Xhc->PciIo;\r
  Status = PciIo->Pci.Read (\r
                        PciIo,\r
                        EfiPciIoWidthUint16,\r
                        PCI_COMMAND_OFFSET,\r
                        sizeof (XhciCmd),\r
                        &XhciCmd\r
                        );\r
  if (!EFI_ERROR (Status)) {\r
    if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {\r
      XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);\r
    }\r
  }\r
}\r
\r
/**\r
  Reset the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The XHCI host controller is reset.\r
  @return Others       Failed to reset the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  Status = EFI_SUCCESS;\r
\r
  DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));\r
  //\r
  // Host can only be reset when it is halt. If not so, halt it\r
  //\r
  if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {\r
    Status = XhcHaltHC (Xhc, Timeout);\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
      ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {\r
    XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
    //\r
    // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.\r
    // Otherwise there may have the timeout case happened.\r
    // The below is a workaround to solve such problem.\r
    //\r
    gBS->Stall (XHC_1_MILLISECOND);\r
    Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
\r
    if (!EFI_ERROR (Status)) {\r
      //\r
      // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.\r
      // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
      //\r
      XhcSetHsee (Xhc);\r
    }\r
  }\r
\r
  return Status;\r
}\r
\r
\r
/**\r
  Halt the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is halt.\r
  @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
  IN USB_XHCI_INSTANCE   *Xhc,\r
  IN UINT32              Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r
  Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);\r
  return Status;\r
}\r
\r
\r
/**\r
  Set the XHCI host controller to run.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is running.\r
  @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r
  Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);\r
  return Status;\r
}\r
\r